Embedded Systems Design: A Unified Hardware/Software Introduction

7/7/2011
Embedded Systems Design: A Unified Hardware/Software Introduction
Introduction
General-Purpose Processor
Processor designed for a variety of computation tasks Low unit cost, in part because manufacturer spreads NRE over large numbers of units
Motorola sold half a billion 68HC05 microcontrollers in 1996 alone
Chapter 3 General-Purpose Processors: Software
Carefully designed since higher NRE is acceptable

Can yield good performance, size and power
Low NRE cost, short time-to-market/prototype, high flexibility

User just writes software; no processor design
a.k.a. microprocessor micro used when they were implemented on one or a few chips rather than entire rooms
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Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Basic Architecture
Control unit and datapath
Note similarity to single-purpose processor
Processor Control unit Datapath ALU Controller Control /Status Registers
Datapath Operations
Load
Read memory location into register
Control unit Processor Datapath ALU Controller Control /Status
ALU operation
Input certain registers through ALU, store back in register
+1
Key differences
Datapath is general Control unit doesnt store the algorithm the algorithm is programmed into the memory
PC IR
Registers
Store
Write register to memory location
I/O Memory Memory PC IR
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11
I/O
...
10 11 ...
Control Unit
Control unit: configures the datapath operations
Sequence of desired operations (instructions) stored in memory program
Control unit Processor Datapath ALU Controller Control /Status Registers
Control Unit Sub-Operations

Fetch
Get next instruction into IR PC: program counter, always points to next instruction IR: holds the fetched instruction
Control unit Controller Processor Datapath ALU Control /Status Registers
Instruction cycle broken into several sub-operations, each one clock cycle, e.g.:
Fetch: Get next instruction into IR Decode: Determine what the instruction means Fetch operands: Move data from memory to datapath register Execute: Move data through the ALU Store results: Write data from register to memory
PC
IR
R0
R1
PC
100
IR load R0, M[500]
R0
R1
I/O 100 load R0, M[500] 101 inc R1, R0 102 store M[501], R1 Memory 500 501
...
10
I/O 100 101 load R0, M[500] inc R1, R0 Memory 500 501
...
10
...
5
102 store M[501], R1
...
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Decode
Determine what the instruction means
Control unit Controller Processor Datapath ALU Control /Status

Fetch operands
Move data from memory to datapath register
Registers
Registers
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PC 100 IR load R0, M[500] R0 R1 PC 100 IR load R0, M[500] R0 R1
...
10
...
10
102 store M[501], R1 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
...
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102 store M[501], R1
...
8

Execute
Move data through the ALU This particular instruction does nothing during this sub-operation

Store results
Write data from register to memory This particular instruction does nothing during this sub-operation
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PC 100 IR load R0, M[500] R0 R1
10
PC 100 IR load R0, M[500] R0 R1
...
10
...
10
102 store M[501], R1 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
...
9
102 store M[501], R1
...
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Instruction Cycles
PC=100
clk Processor Control unit Datapath ALU Controller Control /Status Registers
Instruction Cycles
PC=100
clk Processor Control unit Datapath ALU Controller Control /Status
Fetch Decode Fetch Exec. Store ops results
+1
PC=101
clk

PC 101 IR inc R1, R0 R0
Registers
10
PC 100 IR load R0, M[500] R0 R1
10
11
R1
I/O 100 load R0, M[500] 101 inc R1, R0 102 store M[501], R1 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Memory 500 501
...
10
I/O 100 load R0, M[500] 101 inc R1, R0 102 store M[501], R1 Memory 500 501
...
10
...
11
...
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Instruction Cycles
PC=100
clk Processor Control unit Datapath ALU Controller Control /Status
Architectural Considerations
N-bit processor
N-bit ALU, registers, buses, memory data interface Embedded: 8-bit, 16bit, 32-bit common Desktop/servers: 32bit, even 64
PC=101
clk

PC 102 IR store M[501], R1 R0
Registers
Registers
10
11
R1
PC
IR
PC=102
clk

100 load R0, M[500] 101 inc R1, R0 102 store M[501], R1
I/O Memory 500
10 501 11
... ...
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PC size determines address space

I/O Memory
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Architectural Considerations
Clock frequency
Inverse of clock period Must be longer than longest register to register delay in entire processor Memory access is often the longest
Control unit Controller Processor Datapath ALU Control /Status Registers Dry Wash
Pipelining: Increasing Instruction Throughput

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 8 Non-pipelined Pipelined
non-pipelined dish cleaning
Time
pipelined dish cleaning
Time
Fetch-instr. Decode PC IR Fetch ops. Execute I/O Memory Store res.
2 1
3 2 1
4 3 2 1
5 4 3 2 1
6 5 4 3 2
7 6 5 4 3
8 7 6 5 4 8 7 6 5 8 7 6 8 7 8 Pipelined
Instruction 1
pipelined instruction execution
Time
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Superscalar and VLIW Architectures

Performance can be improved by:
Faster clock (but theres a limit) Pipelining: slice up instruction into stages, overlap stages Multiple ALUs to support more than one instruction stream
Superscalar
Scalar: non-vector operations Fetches instructions in batches, executes as many as possible May require extensive hardware to detect independent instructions VLIW: each word in memory has multiple independent instructions Relies on the compiler to detect and schedule instructions Currently growing in popularity
Two Memory Architectures

Processor Processor
Princeton
Fewer memory wires
Harvard
Simultaneous program and data memory access
Program memory Data memory Memory (program and data)
Harvard
Princeton
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Cache Memory
Memory access may be slow Cache is small but fast memory close to processor
Holds copy of part of memory Hits and misses
Fast/expensive technology, usually on the same chip
Programmers View
Programmer doesnt need detailed understanding of architecture
Instead, needs to know what instructions can be executed
Processor
Two levels of instructions:

Assembly level Structured languages (C, C++, Java, etc.)
Cache
Most development today done using structured languages

But, some assembly level programming may still be necessary Drivers: portion of program that communicates with and/or controls (drives) another device
Often have detailed timing considerations, extensive bit manipulation Assembly level may be best for these
Memory
Slower/cheaper technology, usually on a different chip
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Assembly-Level Instructions
Instruction 1 Instruction 2 Instruction 3 Instruction 4 opcode opcode opcode opcode operand1 operand1 operand1 operand1 ... operand2 operand2
A Simple (Trivial) Instruction Set

Assembly instruct. MOV Rn, direct First byte 0000 0001 0010 0011 0100 0101 0110 opcode Rn Rn Rn Rn Rn Rn Rn Rm immediate Rm Rm relative operands Second byte direct direct Operation Rn = M(direct) M(direct) = Rn M(Rn) = Rm Rn = immediate Rn = Rn + Rm Rn = Rn - Rm PC = PC+ relative (only if Rn is 0)
operand2 MOV direct, Rn operand2 MOV @Rn, Rm MOV Rn, #immed. ADD Rn, Rm
Instruction Set
Defines the legal set of instructions for that processor
Data transfer: memory/register, register/register, I/O, etc. Arithmetic/logical: move register through ALU and back Branches: determine next PC value when not just PC+1
SUB Rn, Rm JZ Rn, relative
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Addressing Modes
Addressing mode Operand field Register-file contents Memory contents C program
Sample Programs
Equivalent assembly program 0 1 2 3 MOV R0, #0; MOV R1, #10; MOV R2, #1; MOV R3, #0; JZ R1, Next; ADD R0, R1; SUB R1, R2; JZ R3, Loop; // next instructions... // total = 0 // i = 10 // constant 1 // constant 0 // Done if i=0 // total += i // i-// Jump always
Immediate Register-direct
Data
Register address
Data int total = 0; for (int i=10; i!=0; i--) total += i; // next instructions...
Register indirect
Loop: 5 6 7 Next:
Register address
Memory address
Data
Direct
Memory address
Data
Try some others

Handshake: Wait until the value of M[254] is not 0, set M[255] to 1, wait until M[254] is 0, set M[255] to 0 (assume those locations are ports). (Harder) Count the occurrences of zero in an array stored in memory locations 100 through 199.
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Indirect
Memory address
Memory address
Data
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Programmer Considerations
Program and data memory space
Embedded processors often very limited
e.g., 64 Kbytes program, 256 bytes of RAM (expandable)
Microprocessor Architecture Overview

If you are using a particular microprocessor, now is a good time to review its architecture
Registers: How many are there?

Only a direct concern for assembly-level programmers
I/O
How communicate with external signals?
Interrupts
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Example: parallel port driver

LPT Connection Pin 1 2-9 10,11,12,13,15 14,16,17 I/O Direction Output Output Input Output Register Address 0th bit of register #2 0th bit of register #2 6,7,5,4,3th bit of register #1 1,2,3th bit of register #2
Parallel Port Example

Pin 13
; This program consists of a sub-routine that reads ; the state of the input pin, determining the on/off state ; of our switch and asserts the output pin, turning the LED ; on/off accordingly .386 CheckPort push push dx mov in and cmp jne SwitchOff: mov in and out jmp SwitchOn: mov in or out Done: pop pop CheckPort proc ax extern C CheckPort(void); void main(void) { while( 1 ) { CheckPort(); } } // defined in // assembly
PC Parallel port
Pin 2 LED
Sw itch
; save the content ; save the content dx, 3BCh + 1 ; base + 1 for register #1 al, dx ; read register #1 al, 10h ; mask out all but bit # 4 al, 0 ; is it 0? SwitchOn ; if not, we need to turn the LED on
Pin 13
Using assembly language programming we can configure a PC parallel port to perform digital I/O
write and read to three special registers to accomplish this table provides list of parallel port connector pins and corresponding register location Example : parallel port monitors the input switch and turns the LED on/off accordingly
PC Parallel port
Pin 2 LED
Sw itch
dx, 3BCh + 0 ; base + 0 for register #0 al, dx ; read the current state of the port al, f7h ; clear first bit (masking) dx, al ; write it out to the port Done ; we are done
LPT Connection Pin

dx, 3BCh + 0 ; base + 0 for register #0 al, dx ; read the current state of the port al, 01h ; set first bit (masking) dx, al ; write it out to the port dx ax endp ; restore the content ; restore the content
I/O Direction Output Output Input Output
Register Address 0th bit of register #2 0th bit of register #2 6,7,5,4,3th bit of register #1 1,2,3th bit of register #2
1 2-9 10,11,12,13,15 14,16,17
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Operating System
Optional software layer providing low-level services to a program (application).
File management, disk access Keyboard/display interfacing Scheduling multiple programs for execution
Or even just multiple threads from one program
Development Environment
Development processor
The processor on which we write and debug our programs
Usually a PC
Target processor
DB file_name out.txt -- store file name MOV R0, 1324 MOV R1, file_name INT 34 JZ R0, L1 -- system call open id -- address of file-name -- cause a system call -- if zero -> error
The processor that the program will run on in our embedded system
Often different from the development processor
Program makes system calls to the OS

. . . read the file JMP L2 -- bypass error cond. L1: . . . handle the error L2:
Development processor 29
Target processor 30
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Software Development Process

Compilers
C File C File Asm. File
Running a Program
If development processor is different than target, how can we run our compiled code? Two options:
Download to target processor Simulate
Cross compiler
Runs on one processor, but generates code for another
Debugger Profiler
Compiler Binary File Binary File
Assemble r Binary File
Simulation
One method: Hardware description language
But slow, not always available
Linker Library Exec. File Implementation Phase
Verification Phase
Assemblers Linkers Debuggers Profilers

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Another method: Instruction set simulator (ISS)

Runs on development processor, but executes instructions of target processor
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Instruction Set Simulator For A Simple Processor

#include <stdio.h>
typedef struct { unsigned char first_byte, second_byte; } instruction; instruction program[1024]; //instruction memory unsigned char memory[256]; //data memory void run_program(int num_bytes) { int pc = -1; unsigned char reg[16], fb, sb; while( ++pc < (num_bytes / 2) ) { fb = program[pc].first_byte; sb = program[pc].second_byte; switch( fb >> 4 ) { case 0: reg[fb & 0x0f] = memory[sb]; break; case 1: memory[sb] = reg[fb & 0x0f]; break; case 2: memory[reg[fb & 0x0f]] = reg[sb >> 4]; break; case 3: reg[fb & 0x0f] = sb; break; case 4: reg[fb & 0x0f] += reg[sb >> 4]; break; case 5: reg[fb & 0x0f] -= reg[sb >> 4]; break; case 6: pc += sb; break; default: return 1; If( argc != 2 || (ifs = fopen(argv[1], rb) == NULL ) { return 1; } if (run_program(fread(program, sizeof(program) == 0) { print_memory_contents(); return(0); } else return(-1); } } } return 0; } int main(int argc, char *argv[]) { FILE* ifs; (a)
Testing and Debugging

(b)
ISS
Implementation Phase
Implementation Phase
Verification Phase
Development processor
Debugger / ISS
Emulator
Gives us control over time set breakpoints, look at register values, set values, step-by-step execution, ... But, doesnt interact with real environment
Download to board
Use device programmer Runs in real environment, but not controllable
External tools
Compromise: emulator
Programmer
Verification Phase
Runs in real environment, at speed or near Supports some controllability from the PC
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Application-Specific Instruction-Set Processors (ASIPs)

General-purpose processors
Sometimes too general to be effective in demanding application
e.g., video processing requires huge video buffers and operations on large arrays of data, inefficient on a GPP
A Common ASIP: Microcontroller

For embedded control applications
Reading sensors, setting actuators Mostly dealing with events (bits): data is present, but not in huge amounts e.g., VCR, disk drive, digital camera (assuming SPP for image compression), washing machine, microwave oven
But single-purpose processor has high NRE, not programmable
Microcontroller features
On-chip peripherals
Timers, analog-digital converters, serial communication, etc. Tightly integrated for programmer, typically part of register space
ASIPs targeted to a particular domain

Contain architectural features specific to that domain
e.g., embedded control, digital signal processing, video processing, network processing, telecommunications, etc.
Still programmable
On-chip program and data memory Direct programmer access to many of the chips pins Specialized instructions for bit-manipulation and other low-level operations
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Another Common ASIP: Digital Signal Processors (DSP)

For signal processing applications
Large amounts of digitized data, often streaming Data transformations must be applied fast e.g., cell-phone voice filter, digital TV, music synthesizer
Trend: Even More Customized ASIPs

In the past, microprocessors were acquired as chips Today, we increasingly acquire a processor as Intellectual Property (IP)
e.g., synthesizable VHDL model
DSP features
Several instruction execution units Multiple-accumulate single-cycle instruction, other instrs. Efficient vector operations e.g., add two arrays
Vector ALUs, loop buffers, etc.
Opportunity to add a custom datapath hardware and a few custom instructions, or delete a few instructions
Can have significant performance, power and size impacts Problem: need compiler/debugger for customized ASIP
Remember, most development uses structured languages One solution: automatic compiler/debugger generation
e.g., www.tensillica.com
Another solution: retargettable compilers

e.g., www.improvsys.com (customized VLIW architectures)
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Selecting a Microprocessor
Issues
Technical: speed, power, size, cost Other: development environment, prior expertise, licensing, etc.
Processor Intel PIII 1GHz
General Purpose Processors

Clock speed Periph. 2x16 K L1, 256K L2, MMX 2x32 K L1, 256K L2 2x32 K 2 way set assoc. None Bus Width MIPS General Purpose Processors 32 ~900 Power 97W Trans. ~7M Price $900
Speed: how evaluate a processors speed?

Clock speed but instructions per cycle may differ Instructions per second but work per instr. may differ Dhrystone: Synthetic benchmark, developed in 1984. Dhrystones/sec.
MIPS: 1 MIPS = 1757 Dhrystones per second (based on Digitals VAX 11/780). A.k.a. Dhrystone MIPS. Commonly used today.
So, 750 MIPS = 750*1757 = 1,317,750 Dhrystones per second
IBM PowerPC 750X MIPS R5000 StrongARM SA-110 Intel 8051 Motorola 68HC811
550 MHz
32/64
~1300
5W
~7M
$900
250 MHz 233 MHz
32/64 32
NA 268
NA 1W
3.6M 2.1M
NA NA
12 MHz 3 MHz
4K ROM, 128 RAM, 32 I/O, Timer, UART 4K ROM, 192 RAM, 32 I/O, Timer, WDT, SPI 128K, SRAM, 3 T1 Ports, DMA, 13 ADC, 9 DAC 16K Inst., 2K Data, Serial Ports, DMA
8 8
Microcontroller ~1 ~.5
~0.2W ~0.1W
~10K ~10K
$7 $5
SPEC: set of more realistic benchmarks, but oriented to desktops EEMBC EDN Embedded Benchmark Consortium, www.eembc.org
Suites of benchmarks: automotive, consumer electronics, networking, office automation, telecommunications
TI C5416
160 MHz
Digital Signal Processors 16/32 ~600
NA
NA
$34
Lucent DSP32C
80 MHz
32
40
NA
NA
$75
Sources: Intel, Motorola, MIPS, ARM, TI, and IBM Website/Datasheet; Embedded Systems Programming, Nov. 1998
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Designing a General Purpose Processor

FSMD
Architecture of a Simple Microprocessor

Storage devices for each declared variable
register file holds each of the variables
Control unit
To all input control signals
Not something an embedded system designer normally would do

But instructive to see how simply we can build one top down Remember that real processors arent usually built this way
Much more optimized, much more bottom-up design
Aliases: op IR[15..12] rn IR[11..8] rm IR[7..4]
Declarations: bit PC[16], IR[16]; bit M[64k][16], RF[16][16];
Reset Fetch
PC=0;
Datapath
RFs
IR=M [PC]; PC=PC+1 from states below
2x1 mux
RFw
Decode
Mov1
op = 0000
RF[rn] = M [dir] to Fetch M [dir] = RF[rn] to Fetch M [rn] = RF[rm] to Fetch RF[rn]= imm to Fetch RF[rn] =RF[rn]+RF[rm] to Fetch RF[rn] = RF[rn]-RF[rm] to Fetch PC=(RF[rn]=0) ?rel :PC to Fetch
Functional units to carry out the FSMD operations

One ALU carries out every required operation
PCld PCinc PCclr 2 Ms
Controller (Next-state and control logic; state register)
RFwa RFwe
From all output control signals Irld
RF (16)
RFr1a RFr1e RFr2a RFr1 RFr2e ALUs ALU ALUz RFr2
Mov2
0001
16 PC IR
Mov3
0010
0011
Mov4
0100
Add
Sub
0101 dir IR[7..0] imm IR[7..0] rel IR[7..0]
Connections added among the components ports corresponding to the operations required by the FSM Unique identifiers created for every control signal
3x1 mux
M re M we
Memory
Jz
0110
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A Simple Microprocessor
Reset Fetch Decode
PC=0; IR=M [PC]; PC=PC+1 from states below PCclr=1; M S=10; Irld=1; M re=1; PCinc=1; RFwa=rn; RFwe=1; RFs=01; M s=01; Mre=1; RFr1a=rn; RFr1e=1; M s=01; Mwe=1; RFr1a=rn; RFr1e=1; M s=10; Mwe=1; PCld 0011 0100 0101 0110 RFwa=rn; RFwe=1; RFs=10; RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=00 RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=01 PCld= ALUz; RFrla=rn; RFrle=1; PCinc PCclr 2 Ms 1 0 PC
Chapter Summary
General-purpose processors
Datapath
RFs
Control unit
Mov1
op = 0000 0001 0010
RF[rn] = M [dir] to Fetch M [dir] = RF[rn] to Fetch M [rn] = RF[rm] to Fetch RF[rn]= imm to Fetch RF[rn] =RF[rn]+RF[rm] to Fetch RF[rn] = RF[rn]-RF[rm] to Fetch PC=(RF[rn]=0) ?rel :PC to Fetch
Mov2 Mov3 Mov4 Add Sub Jz FSMD
Controller (Next-state and control logic; state register) 16
To all input contro l signals From all output control signals Irld
Good performance, low NRE, flexible
2x1 mux
RFw
RFwa RFwe
Controller, datapath, and memory Structured languages prevail

But some assembly level programming still necessary
RF (16)
RFr1a RFr1e RFr2a RFr2e ALUs ALU ALUz RFr1 RFr2
Many tools available

Including instruction-set simulators, and in-circuit emulators
IR
ASIPs
Microcontrollers, DSPs, network processors, more customized ASIPs
3x1 mux
M re M we
FSM operations that replace the FSMD operations after a datapath is created
Memory
You just built a simple microprocessor!

Choosing among processors is an important step Designing a general-purpose processor is conceptually the same as designing a single-purpose processor
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7/7/2011

Embedded Systems Design: A Unified Hardware/Software Introduction

Chapter 3 General-Purpose Processors: Software

Carefully designed since higher NRE is acceptable

Low NRE cost, short time-to-market/prototype, high flexibility

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Control Unit Sub-Operations

IR load R0, M[500]

102 store M[501], R1

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Control Unit Sub-Operations

Control Unit Sub-Operations

102 store M[501], R1

Control Unit Sub-Operations

Control Unit Sub-Operations

102 store M[501], R1

Fetch Decode Fetch Exec. Store ops results

Fetch Decode Fetch Exec. Store ops results

Fetch Decode Fetch Exec. Store ops results

Fetch Decode Fetch Exec. Store ops results

Fetch Decode Fetch Exec. Store ops results

Fetch Decode Fetch Exec. Store ops results

I/O Memory 500

PC size determines address space

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Pipelining: Increasing Instruction Throughput

non-pipelined dish cleaning

pipelined dish cleaning

Fetch-instr. Decode PC IR Fetch ops. Execute I/O Memory Store res.

pipelined instruction execution

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Superscalar and VLIW Architectures

Two Memory Architectures

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Two levels of instructions:

Most development today done using structured languages

Slower/cheaper technology, usually on a different chip

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

A Simple (Trivial) Instruction Set

SUB Rn, Rm JZ Rn, relative

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Try some others

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Microprocessor Architecture Overview

Registers: How many are there?

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Example: parallel port driver

Parallel Port Example

LPT Connection Pin

I/O Direction Output Output Input Output

1 2-9 10,11,12,13,15 14,16,17

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Program makes system calls to the OS