Int. J. Electron. Commun.

(AEÜ) 108 (2019) 226–234

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

Improving the electrical characteristics of nanoscale triple-gate

junctionless FinFET using gate oxide engineering
Nazanin Baghban Bousari a, Mohammad K. Anvarifard b,⇑, Saeed Haji-Nasiri a
a
Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
b
Department of Engineering Sciences, Faculty of Technology and Engineering, East of Guilan, University of Guilan, Rudsar-Vajargah, Iran

a r t i c l e i n f o a b s t r a c t

Article history: This paper is about the compared performance investigation of various structures of Hetero-Dielectric
Received 10 April 2019 (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate Oxide (DHGO),
Accepted 17 June 2019 Triple Hetero Gate Oxide (THGO) and Quadruple Hetero Gate Oxide (QHGO) to produce lower leakage
current, higher Ion/Ioff ratio, higher gm/gd and also lower Drain Induced Barrier Lowering (DIBL) than those
of a conventional triple-gate FinFET. Among all of them, the best results are explored for the DHGO FinFET
Keywords: structure. In DHGO FinFET structure, a high-j dielectric (j = 22) is used on the top oxide to increase the
Triple-gate junctionless FinFET
gate control and a low-k dielectric (j = 3.9) is used over silicon body owing to the compatibility of lattice
Gate oxide engineering
DD_MS approach
constant of SiO2 and silicon. Mode-space drift-diffusion (DD_MS) model coupled with Schrodinger equa-
tion has been utilized in order to analyze the proposed and conventional structures in three dimensional
(3D) simulation domain. Interestingly, by decreasing the thickness of the oxide layer and increasing the
permittivity coefficient, the leakage current decreases, thus increasing the Ion/Ioff ratio. The DHGO FinFET
structure is found to exhibit higher Ion/Ioff, lower DIBL and higher gm/gd ratio, thus proving performance
superiority over the other conventional junctionless FinFET and also MOSFETs.
Ó 2019 Elsevier GmbH. All rights reserved.

1. Introduction Among all multi-gate FETs, Triple Gate (TG) FETs with three
gates have been recognized as the best candidates for sub-
Scaling the planar MOSFETs in recent decades has been aggres- 100 nm scaling of MOSFETs owing to higher gate control and there-
sively performed to increase electrical performance of integrated fore producing less leakage current. In trigate FETs architecture,
circuits. If this procedure continues in the nano-scale, it will be three sides; one top side and two lateral sides of the silicon body
faced with many challenges due to the rise in the subthreshold are surrounded by the front-gate. The third gate complicates the
leakage current. The most critical performance parameters of pla- manufacturing process, although it has some advantages such as
nar MOSFETs in the sub-micron regime are Drain Induced Barrier reducing the side capacitors [11–14].
Lowering (DIBL), Sub-threshold Slope (SS) and leakage current, In order to shrink the size of the transistors, it is very difficult to
which are affected by decreasing the length of the channel. To fabricate junction based transistors. Due to the complexity of the
overcome these challenges, a new group of transistors, named Fin- manufacturing process, new structures were introduced called
FET was introduced which is based on multi-gate transistors. Due Junctionless (JL) transistors. Unlike Inversion Mode (IM) transis-
to the shorter length of the channel in the MOSFET scaling, not only tors, in which drain current flows through the channel surface, in
the channel region is controlled by the gate but also the drain the JL transistors, the current flows in bulk of the semiconductor
effects on the channel electrostatic [1–7]. By scaling down of the [11,15]. The operation of JL transistors is the same as that of the
transistor, the leakage current is enhanced. Therefore, good gate accumulation transistors which have three working areas: full
control is becoming critical requirement to increase the electrical depletion, semi-depletion and accumulation. When the gate-
performance [1,8–10]. source voltage is zero, the channel is completely depleted and no
carriers flow and therefore the transistor is in off mode. When
the gate voltage exceeds the threshold voltage, the transistor
works in the semi-depletion mode. When the semi-depletion is
⇑ Corresponding author. reduced from the center of the semiconductor, the flow in the body
E-mail addresses: m.anvarifard@guilan.ac.ir (M.K. Anvarifard), s.nasiri@qiau.ac.ir is established and the transistor is turned on. For gate voltages lar-
(S. Haji-Nasiri).

https://doi.org/10.1016/j.aeue.2019.06.017
1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.
 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234 227

ger than the flat band voltage, the carriers are accumulated at the 2. Proposed structures configuration
surface and there is no depletion; thus, the current flows in the
channel [16,17]. Narendar et al. studied on the impact of high-j In this work, we divided the oxides in the direction of x and y
dielectrics to control short channel effects. They revealed that the axes to reach the reduced leakage current and also a higher Ion/Ioff
mobility degradation problem in gate stack high-j dielectrics can ratio, where Wfin is the fin width, Hfin is the fin height, and L is the
be controlled by high-j dielectric materials in between metal gate channel length which are set to 5, 5 and 14 nm in all structures,
and semiconductor [8]. Baidya et al. studied on high-j dielectrics respectively. The gate electrode surrounds the silicon body on
as the gate insulator in junctionless transistors. They showed that three sides with a gate oxide thickness of 1.5 nm. The body of
using high-j materials can improve transconductance, drain con- the silicon is doped with acceptor concentration (ND) and the gate
ductance, output resistance and intrinsic gain [18]. Akbari et al. material is metal with a work function of 5 ev.
investigated two different insulators in graphene nanoribbon field A schematic view of the conventional TG FinFET is shown in
effect transistor [19]. They revealed that using high and low dielec- Fig. 1, which illustrates the cross section of conventional TG JL
tric constants offers lower Off-current, higher On-current and FinFET, in which the thickness of oxide is assumed to be
higher transconductance. 1.5 nm. Fig. 2 illustrates the three-dimensional schematic and
Owing to the shrinking transistors, the thickness of the gate cross-sectional view of the DHGO TG FinFET structure in yx and
oxide should be reduced so as to have better electrical perfor- yz planes and also 3D schematic view of the structure is pre-
mance. When the thickness of the gate oxide reaches below one sented. In this case, we have divided the gate oxide into two parts
nanometer, due to quantum tunneling, the problem of leakage of along the y axis. At the bottom oxide, a low-j material (j = 3.9)
the gate occurs [20]. Therefore, as a gate insulator, silicon dioxide and at the toper oxide a high-j material (j = 22) are used. The
(SiO2) should be replaced by a material with a high dielectric con- reason why SiO2 at the bottom part can be used with silicon is
stant. Increasing the thickness of the dielectric can prevent leakage the compatibility of their lattice constant. Also, the reason that
of the gate. From this perspective, the JL TG FinFETs with Hetero- a material with high-j is used at the toper part is to increase
Dielectrics (HD) are studied. the gate capacitance which raises the gate control [19,21]. Triple
In order to solve the electron transport equation, 3D poisson Hetero Gate Oxide (THGO) has been illustrated in Fig. 3. The toper
equation using DD_MS method has been used, and the results oxide has divided into two parts along y axis and used two mate-
are compared with conventional structure. This manuscript is rials with high-j dielectric (j = 9, j = 22) to increase the gate
divided into several sections: In Section 2, the devices geometry control, because the lattice constant of silicon is compatible with
is presented. In Section 3, the calculation methods involved in SiO2, thus we used SiO2 over silicon body. In the final structure,
the simulation domain of the device are presented. In Section 4, Quadruple Gate Hetero Oxide (QHGO) has been illustrated in
the results and discussions are reported and the conclusions is pre- Fig. 4. We divide the gate oxide into two parts along x and y axes.
sented in Section 5, finally. The oxides we have used at the bottom parts have low dielectric

Fig. 1. (a) Cross section view of a conventional JL TG FinFET in xy direction. (b) Side view in zy direction.
228 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234

Fig. 2. (a) Cross section view of DHGO JL TG FinFET in xy direction. (b) Side view in zy direction. (c) 3D schematic view.

constants (j = 7.5, j = 3.9) compare to the upper oxides (j = 9, capacitor between the gate metal and the channel, and the gate
j = 22), but the oxide on the right side has a lower dielectric con- voltage on the drain side has less effect on the channel. Also, by
stant in comparison to the left one. We used the oxide with a using insulators with a higher dielectric constant at the toper
lower dielectric constant on the right side to create a weaker part, we have higher capacitor under the gate.
 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234 229

Fig. 3. (a) Cross section view of THGO JL TG FinFET in xy direction. (b) Side view in zy direction. (c) 3D schematic view.
230 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234

Fig. 4. (a) Cross section view of QHGO JL TG FinFET in xy direction. (b) Side view in zy direction. (c) 3D schematic view.
 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234 231

Table 1 where Jmb(x) is subband current, nmb(x) is subband carrier density to

Dimensions of the proposed and conventional structures. be found, and Emb(x) is subband eigen energy as found by Schrodin-
Parameter Value ger solver in transverse direction. Mobility lmb(x) is defined by the
Channel length (LG) 14 nm
use of the ATLAS Mobility Models and generally depends on mate-
Fin height (HFin) 5 nm rial, doping, local longitudinal electric field and temperature. The
Fin width (WFin) 5 nm Diffusion coefficient Dmb(x) is related to the mobility function and
Thickness oxide (Tox) 1.5 nm is calculated from the following equation:
Top oxide thickness (Tox,top) 1 nm
Bottom oxide thickness (Tox,bottom) 0.5 nm
1
@nv b
Source and drain length (LG,S/D) 10 nm Dv b ¼ lv b ð4Þ
Source/drain doping concentration (ND) 5  1019 cm3 @Ev b
Gate workfunction (W.F) 5.00 ev
The relation between the densities of the subband carriers,
quasi-fermi levels and the eigen energies is obtained from Eq. (5)
[26]:
It is worth mentioning that by increasing the Cgs/Cgd ratio, elec-
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 

trostatic control of the gate increases. Therefore, by decreasing the kB T X v b mv b ln 1 þ exp  Ev b  EF;v b
nv b ¼ 2 m ð5Þ
Cgd, we must have a lower j on the drain side according to the for- Aph
2 v x z
KBT
mula (1) [22]. The relation between the gate oxide capacitor and
the relative constant of dielectric insulation is as follows: Recombination rate is computed by calculating the recombina-
tion of a specific electron subband with all the hole subbands [26]:
je0 A
c¼ ð1Þ X X nv b p 0  n2
tox Rv b ¼ Rv bkb0  kb i
ð6Þ
sv bkb0
In the above formula, j is relative dielectric constant coefficient, kb0 kb0

e0 is air dielectric constant, A is capacitance area and tox is thick- where Rmbkb’(x), are calculated by using Atlas Recombination Mod-
ness of the oxide [22,23]. Due to this, we used a lower dielectric els with the substitution of the density of the subband carriers for
constant on the drain side. In fact, the oxide that is between the bulk densities, subband eigen energies for conduction and valence
gate and the semiconductor affects this capacitor, which increases bands, and subband fermi levels for bulk fermi levels. When a single
the control of the gate and therefore increases the drain current. carrier is solved (electron or hole only), the recombination rate is
In order to have a lower leakage current and therefore a higher considered zero.
Ion/Ioff ratio, uniform n-type doping concentration is assumed as The total impact ionization generation rates are calculated by
5  1019 cm3. In this work, the conventional structure is similar using the sum of all electron and hole subbands [26]:
to the proposed structures, with the consequence lacking of
X 
anv b jJv b j þ akb
0
Hetero-Dielectrics (HD). The length of the channel is considered Gtotal ¼ ð7Þ
p jJ v b j
0

as 14 nm and the thickness of the silicon is 5 nm. In Table 1, the v bkb0

needed parameters for evaluating of the proposed structures have
been listed. As indicated in Table 1, the thickness of the bottom an and ap, the Impact ionization coefficients are calculated by using
oxide is 0.5 nm and the thickness of the upper oxide is 1 nm in pro- ATLAS bulk impact ionization models. The generation rate in each
posed structures. It is significant that all the parameters of the con- subband is calculated by using Gtotal. After solving the one-
ventional device are similar to those of the proposed devices unless dimensional transfer equations in each subband and extracting
otherwise stated. quasi-formal surfaces, the density of the current of the 3-D band
carriers is calculated [26]. Some models such as the Band Gap Nar-
rowing (BGN) model is used to calculate heavy doping. Also, the
3. Computational method
Fermi model is considered to specify Fermi-Dirac carrier statistics.
Since the performance of the device prediction is valid with
In order to evaluate the structures characteristics, ATLAS-3D is
SILVACO-ATLAS software, many researchers have used this software
used to solve the charge transport equations in the conventional
as reported in Refs. [27–29].
and proposed devices. In three-dimensional (3D) calculations, a
mode space approach is used to reduce computational costs. The
coupled-mode-space approach with Schrodinger Poisson is one of 4. Results and discussions
the most efficient 3D simulation techniques due to reducing too
much computational time, compare to real-space approach, while, In this paper, we have used commercially SILVACO-ATLAS soft-
at the same time, providing sufficient accuracy. Mode Space Drift- ware to develop and optimize our devices. The purpose of this
diffusion (DD_MS) is a semi-classical approach for transitions that paper is to gain knowledge on the JL TG FinFET leakage current,
have a strong cross-section and is a simple substitute for the Non- On-to-Off current ratio, DIBL, Subthreshold-Slope and gm/gd ratio.
Equilibrium Green’s Function (NEGF). In this model, similar to The drain bias is fixed at VDS = 0.6 V. It is worth mentioning that
NEGF_MS model, in the transverse direction the solution is decou- the On-state current is evaluated at VGS = 1 V and the Off-state cur-
pled into Schrodinger equation and the one-dimensional transmis- rent is measured at VGS = 0 V.
sion equation in each subband. Nevertheless, in this model, the Tables 1 and 2 demonstrate On-state current, Off-state current,
classical drift-diffusion equation is solved instead of the quantum ratio of On-to-Off current and gm/gd ratio for proposed and conven-
transmission equation [24,25]. One-dimensional drift-diffusion tional structures. Fig. 5(a) and (b) illustrate the drain current as a
transfer in each subband, with substrate indicator v and effective function of the gate voltage for the conventional and proposed
mass index b, are calculated from the following formulas [26]: structures in linear and logarithmic scale. It is observed from the
table and figure that in DHGO TG JL FinFET, the off-state current
1 @J v b
¼ Rv b  Gv b ð2Þ is received 1.16  1017 and the on-state current is received
q @x
4.8  105. Therefore, the highest value for Ion/Ioff parameter is
obtained in this structure. Thus, the switching speed of this transis-
@Ev b @nv b
J v b ¼ qlv b nv b  qDv b ð3Þ tor is higher than those of the proposed structures, resulting in less
@x @x
power dissipation. It must be added that by increasing dielectric
232 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234

Table 2
On-state current, Off-state current, On-to-Off state current and voltage gain for new and conventional structures.

Structure Electrical characteristics

On-state Current (mA/µm) Off-state Current (mA/µm) Ion/Ioff (mA/µm) gm/gd (µA/V)
Conventional Structure 8.95  105 8.5  1014 1  109 153.94
DHGO Structure 4.8  105 1.16  1017 4.13  1012 5111.6
THGO Structure 5.18  105 2.48  1017 2.08  1012 2967.1
QHGO Structure 8.37  105 3.1  1016 2.7  1011 391.95

Fig. 6 illustrated the IDS-VDS characteristic of the proposed and

conventional structures at VGS = 1 V. The DHGO architecture offers
slightly lower value of deriving current compare to the conven-
tional and other proposed structures. The presents of a low-j
material which is compatible with silicon channel and also a
high-j material to raises the gate control are introduced as the
most important factors for the reduction of the drain current. It
should be emphasized that the effective resistance of the channel
region will increase in the DHGO structure resulting in the reduc-
tion of the drain current, as a result, exhibits higher output resis-
tance [32].
Fig. 7 illustrated the electric field at VDS = 0.6 V and VGS = 1 V
along the surface channel. It is clearly seen from the figure that
applying a low-j material in the bottom oxide and a high-j mate-
rial in the upper oxide degrade the maximum electric field at the

Fig. 6. Drain current versus drain voltage for the proposed and conventional
structures at VGS = 1 V, w.f = 5 ev.

Fig. 5. Drain current versus gate voltage in linear and logarithmic scale for the
proposed and the conventional structures at VDS = 0.6 V, w.f = 5 ev.

constant, the leakage current decreases, because based on the rela-

tion e2 = const.DE that has been pointed out first by Moss [30], the
higher dielectric constant material is the smaller band gap that can
be seen. A smaller band gap causes more tunneling in gate oxide.
For this reason, we used a low-j material at the bottom oxide,
which has a larger band gap, so that we can have less leakage. It
is seen that in the proposed structures the leakage current has
decreased and thus the Ion/Ioff ratio has increased. Thus, the switch-
ing speed of this transistor is higher, resulting in less power dissi-
pation which means that better switching of the transistor has Fig. 7. Electric field versus distance from source to drain for the proposed and
been received as compared to the conventional structure [31]. conventional structures at LG = 14 nm along cutline AA0 .
 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234 233

channel end. It should be noticed that the peak electric field in

DHGO structure near the drain contact causes the increment of
accelerating the electrons in the channel and reaching maximum
velocity. This modification of the electric field near the drain,
reduces the hot carriers. Therefore, the proposed structures have
more reliability than the conventional one [28,29].
DIBL has been calculated according to the following equation as
reported in [27,33,34]:

V T1ðVD1Þ  V T2ðVD2Þ
DIBL ðmV=VÞ ¼ ð8Þ
V D2  V D1
According to the Eq. (8), at VDS = 0.6 V and VDS = 0.05 V for the
conventional structure, the DIBL is about 52 mv/v and Also, for
the proposed structures, it is about 20 mv/v. The DHGO structure
has lower DIBL as compared to the other structures. Indeed, using
both low-j and high-j materials in the gate oxide, controls the Fig. 9. On-to-Off current ratio value for the proposed and conventional structures
at VDS = 0.6 V and VGS = 1 V.
channel region of proposed structures. Consequently, the proposed
structures demonstrate a desirable performance for low power
applications.
Sub-threshold slope is defined as the inverse of logarithmic
slope in sub-threshold slope drain current. Sub-threshold slope
has been calculated according to the following equation as
reported in [28,33]:
 1
@log10 ðID Þ
SS ¼ ð9Þ
@V GS
In the proposed structures, sub-threshold slope is obtained 61,
63 and 64 mv/decade for DHGO, THGO and QHGO respectively as
illustrated in Fig. 8, which is very close to the ideal value [28].
Fig. 9 illustrates the Ion/Ioff ratio for the conventional and pro-
posed structures. It is observed in the figure, Ion/Ioff current ratio
is higher in the DHGO structure. the proposed structures demon-
strates higher Ion/Ioff current ratio than the conventional one. As
a result, the DHGO structure experiences lower power dissipation
in standby mode as compared to the other structures. Fig. 10. Voltage gain (gm/gd) value for the proposed and conventional structures at
VDS = 0.6 V and VGS = 1 V.
The small signal drain conductance is an important parameter
in AC applications. The small value of this parameter indicates
the high isolation between the input (gate) and the out-put ports
(drain) of the device in small signal applications. The (gd) is
owing to the lower drain conductance and making it more suitable
obtained from the slope of IDS–VDS at VD = 0.6 V and VG = 1 V. The
for analog applications [32].
small value of drain conductance demonstrates that the isolation
between the input and out-put ports in the DHGO structure is
higher. Transconductance is a parameter describing the device
5. Conclusion
ability to control the barrier height as the gate voltage is applied
in the saturation mode. Also, The (gm) is obtained from the slope
In this paper, Hetero-Dielectric (HD) triple-gate FinFETs with
of IDS–VGS at VD = 0.6 V and VG = 1 V. As it is observed in Fig. 10,
different gate oxides are presented. Three structures named Dou-
the DHGO structure had produced superior voltage gain (gm/gd)
ble Hetero Gate Oxide (DHGO), Triple Hetero Gate Oxide (THGO)
and Quadruple Hetero Gate Oxide (QHGO) are studied. In all three
devices, materials with higher dielectric constants are used for top
gate oxides and materials with lower dielectric constants are used
for the oxides deposited on the silicon body to improve On-current
and reduce leakage current. In order to simulate the electrical
properties of the proposed structures, three dimensional modeling
of TG JL FinFET has been simulated by the use of the Commercial
SILVACO-ATLAS simulator. In order to solve the charge transport,
Mode Space Drift-diffusion (DD_MS) model coupled with
Schrödinger method has been used. The results indicated that the
DHGO structure have been shown better Off-state current, On-
state current, On-to-off ratio, voltage gain (gm/gd) and DIBL com-
pared to the conventional structure with low dielectric constant.

Declaration of Competing Interest

Fig. 8. Sub-threshold slope (SS) value for the proposed and the conventional
structures. The authors declared that there is no conflict of interest.
234 N.B. Bousari et al. / Int. J. Electron. Commun. (AEÜ) 108 (2019) 226–234

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