Transmission Digital Signal Processor IC for Infrared Spatial Digital Audio Communication

CXD4016R
Description

The CXD4016R is an IC that processes the transmitted digital signals used for infrared spatial digital audio
communication (based on the IEC61603-8-1 standard) in consumer products. This IC contains the digital-to-
analog converter (DAC) and a PLL circuit for RF signal. RF signal is processed by digital signal processing, so
the operation is stable without any adjustments.

Features

Æ Performs all the transmitted digital signal processing on a single chip

Æ Supports the infrared spatial digital audio communication system formats for consumer uses
Æ Support the three audio sampling frequencies (32kHz, 44.1kHz, 48kHz)
Æ Direct output of RF signals enabled by on-chip DAC
Æ External RAM and PLL circuit not required

< Audio I/F Block >

̶ Interfaces for various audio ADCs

< Parity Generator Block >

̶ Automatic generation of Reed-Solomon parity for the infrared spatial digital audio communication
system format
< Modulator Block >

̶ Digital processing throughout enables the transmitted RF signals in the infrared spatial digital audio
communication system formats to be processed directly
̶ External analog circuit can be simplified by on-chip digital filter and on-chip DAC for RF signal
applications
̶ Generation of subcarrier processed digitally
< Controller Block >

̶ Simple pin setting mode

̶ Serial interface provided by serial bus
< PLL Block >
̶ On-chip analog PLL circuit for generating the clock signals (640fs) required by the infrared spatial digital
audio communication system formats

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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 CXD4016R

Package

64 pin LQFP (Plastic)

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

̶ Supply voltage VDD – 0.5 to + 3.0 V

̶ Input voltage VI – 0.5 to VDD + 0.5 V
( ≤ 3.0V)
̶ Output voltage VO – 0.5 to VDD + 0.5 V
( ≤ 3.0V)
̶ Storage temperature Tstg – 55 to + 125 °C

Recommended Operating Conditions

̶ Supply voltage VDD 2.5 ± 0.2 V

̶ D/A supply voltage VDA 2.5 ± 0.2 V
̶ PLL supply voltage VPLL 2.5 ± 0.2 V
̶ Operating temperature Topr – 40 to + 85 °C

̶ Sampling frequency precision Within ± 0.1%

Input/Output Capacitance

Æ Input capacitance CIN 16 (max.) pF

Æ Output capacitance COUT 16 (max.) pF
Æ Input/Output capacitance CI/O 16 (max.) pF

Note) Measurement conditions : Tj = 25°C, VDD = VI = 0V, f = 1MHz

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 CXD4016R

Block Diagram

APCPO
APVGS
PLVAR
PLREF

APS
36 37 41 42 43

44 APAVD
PLL 45 APAVS
OSCI 57
Clock 38 APX
OSCO 59
Generator
CK12 53 Clock
Selector 46 VCOT
XRST 64

21 DAAOUT
LRCK 49
22 DAAVD
BCK 50
Reed- D/A 23 DAAVS
DTIN 48 Solomon Converter
Audio I/F Buffer RAM Modulator 24 DAVREF
Parity
BCKOUT 51 Generator 25 DAVRO
LRCKOUT 52

3 IFEXMD
4 IIFSEL1
5 IIFSEL0
6 EXCKSEL
7 CHNM_BL
8 DIVCODE
Controller
9 PCMID
10 EMPIN
14 XSCEN
13 SCLK
15 SWDT
16 CSOD

12 20 27 40 55 58 11 19 26 39 56
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD

* Test pins not shown.

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 CXD4016R

Pin Configuration

DT2_INF

APCPO

APVGS
APAVD
APAVS

PLVAR

PLREF

TEST7

TEST6

TEST5
VCOT
DTIN

APS

APX
VDD
VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

LRCK 49 32 TEST4

BCK 50 31 TEST3

BCKOUT 51 30 TEST2

LRCKOUT 52 29 TEST1

CK12 53 28 TEST0

CSST 54 27 VSS

VSS 55 26 VDD

VDD 56 25 DAVRO

OSCI 57 24 DAVREF

VSS 58 23 DAAVS

OSCO 59 22 DAAVD

XTCK4 60 21 DAAOUT

XSM 61 20 VSS

MST 62 19 VDD

XTST 63 18 DACK

XRST 64 17 DAPD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TESTMD

SMCK

IFEXMD

IIFSEL1

IIFSEL0

EXCKSEL

CHNM_BL

DIVCODE

PCMID

EMPIN

VDD

VSS

SCLK

XSCEN

SWDT

CSOD

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 CXD4016R

Pin Description

Pin
Symbol I/O Description
No.
1 TESTMD I Test mode selector, normally fixed “L”.
2 SMCK I SCAN test pin, normally fixed “H”.
3 IFEXMD I IIF extension mode. (L : Normal mode, H : Extension mode)
4 IIFSEL1 I Audio input mode selection.
5 IIFSEL0 I Audio input mode selection.
6 EXCKSEL I Clock selection for modulation. (L : APX internal connection, H : VCOT pin input)
Half-band : Channel number selection. (L : 0ch, H : 1ch)
7 CHNM_BL I
Full-band : Bit length control. (L : Full bit, H : 16-bit limited)
8 DIVCODE I Full/Half-band mode selection. (L : Full-band, H : Half-band)
9 PCMID I Source_info pcm_id input, normally fixed “L”. (L : PCM data)
10 EMPIN I Source_info emphasis input, (L : No emphasis, H : Emphasis)
11 VDD — Digital power supply.
12 VSS — Digital GND.
13 SCLK I Serial interface data clock input.
14 XSCEN I Serial interface enable input (negative logic).
15 SWDT I Serial interface data write input.
16 CSOD O Chapter start delay output.
17 DAPD O Test pin.
18 DACK O Test pin.
19 VDD — Digital power supply.
20 VSS — Digital GND.
21 DAAOUT O RF DAC output.
22 DAAVD — Analog power supply for RF DAC.
23 DAAVS — Analog GND for RF DAC.
24 DAVREF I RF DAC reference voltage input, apply 1.1V (typ.)
25 DAVRO I/O RF DAC internal current setting.
26 VDD — Digital power supply.
27 VSS — Digital GND.
28 TEST0 O Test output pin.
29 TEST1 O Test output pin.
30 TEST2 O Test output pin.
31 TEST3 O Test output pin.
32 TEST4 O Test output pin.
33 TEST5 O Test output pin.
34 TEST6 O Test output pin.
35 TEST7 O Test output pin.
36 PLREF O PLL reference output.

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 CXD4016R

Pin
Symbol I/O Description
No.
37 PLVAR O PLL frequency-divided output (APX output or VCOT input divided by 640).
38 APX O PLL VCO output, 640fs.
39 VDD — Digital power supply.
40 VSS — Digital GND.
41 APS I PLL reset pin.
42 APVGS — PLL guard band GND.
43 APCPO O PLL charge pump output.
44 APAVD — PLL power supply.
45 APAVS — PLL GND.
46 VCOT I External clock input for modulation.
47 DT2_INF I Test pin, normally fixed “L”.
48 DTIN I Audio data input.
49 LRCK I LR clock input.
50 BCK I Bit clock input.
51 BCKOUT O Bit clock output (3.072MHz).
52 LRCKOUT O LR clock output (48kHz).
53 CK12 O Frequency-divided clock output for master clock (12.288MHz).
54 CSST I Test pin, normally fixed “L”.
55 VSS — Digital GND.
56 VDD — Digital power supply.
57 OSCI I Crystal oscillator circuit input for master clock (24.576MHz).
58 VSS Digital GND.
59 OSCO O Crystal oscillator circuit output for master clock (24.576MHz).
60 XTCK4 I Test pin, normally fixed “L”.
61 XSM I Test pin for SCAN, normally fixed “H”.
62 MST I Test pin for SCAN, normally fixed “L”.
63 XTST I Test pin for SCAN, normally fixed “H”.
Asynchronous reset input. While power supply is “ON”, be sure to reset by fixing
64 XRST I
“L” after power supply is stabilized.

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 CXD4016R

Electrical Characteristics

1. DC characteristics
(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Conditions Min. Typ. Max. Unit Applicable pins
High level input voltage VIH 1.7 — VDD + 0.3
*1
Low level input voltage VIL – 0.3 — 0.7
V
High level output voltage VOH IOH = – 100µA VDD – 0.2 — VDD
*2
Low level output voltage VOL IOL = 100µA 0 — 0.2
High level output current IOH VOH = VDD – 0.4V – 4.0 — — *2
mA
Low level output current IOL VOL = 0.4V 4.0 — — *2

Input leakage current IL — — ±5 µA *1

PLL supply voltage VPLL 2.3 2.5 2.7 V *3

PLL charge pump output

ICPO 500 µA *4
current
DAC supply voltage VDA 2.3 2.5 2.7 V *5

DAC reference voltage VREF 1.05 1.10 1.15 V *6

DAC full-scale adjusting Between DAVRO *7

RREF 2.4 2.7 kΩ
resistor and DAAVS
VREF = 1.10V,
RREF = 2.7kΩ
DAC output current IDAC Full-scale 4.67 5.194 5.71 mA *8
Zero-scale 0 2 20 µA
LSB-scale 20.3 µA
Between DAAOUT
DAC load resistance RL 150 160 Ω *8
and DAAVS
VDD = 2.5V
Supply current of *9
IDD fs = 44.1kHz 12 mA
digital block
Full-band mode
V (DAAVD) = 2.5V
Supply current of *5
IDA fs = 44.1kHz 6.5 mA
D/A block
Full-band mode
V (APAVD) = 2.5V
Supply current of *3
IPLL fs = 44.1kHz 3.5 mA
PLL block
Full-band mode

Applicable pins

*1 TESTMD, SMCK, IFEXMD, IIFSEL1, IIFSEL0, EXCKSEL, CHNM_BL, DIVCODE, PCMID, EMPIN, SCLK,
XSCEN, SWDT, APS, VCOT, DT2_INF, DTIN, LRCK, BCK, CSST, XTCK4, XSM, MST, XTST, XRST
*2 CSOD, DAPD, DACK, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, PLREF, PLVAR,
APX, BCKOUT, LRCKOUT, CK12
*3 APAVD
*4 APCPO
*5 DAAVD
*6 DAVREF
*7 DAVRO
*8 DAAOUT
*9 VDD (Pins 11, 19, 26, 39, 56)

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 CXD4016R

2. AC characteristics

(1) OSCI, OSCO pins

(a) When using self-excited oscillation

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)

Item Symbol Min. Typ. Max. Unit

Oscillation frequency fSYS — 24.576 — MHz

(b) When inputting pulses to OSCI

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
Pulse frequency fSYS 24.330 24.576 24.600 MHz
High level pulse width tWHX — 20.345 — ns
Low level pulse width tWLX — 20.345 — ns
Rise time/fall time tR, tF 2 ns

tCX (1/fSYS)
tWHX tWLX

VIH
VIH × 0.9

OSCI VDD/2

VIH × 0.1
VIL

tR tF

(2) VCOT pin

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
Pulse frequency fCXR 20.275 — 31.027 MHz
High level pulse width tWHXS 0.45 × tCXR — 0.55 × tCXR ns
Low level pulse width tWLXR 0.45 × tCXR — 0.55 × tCXR ns

tCXR (1/fCXR)
tWHXR tWLXR

VIH
VIH × 0.9

VCOT VDD/2

VIH × 0.1
VIL

tR tF

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 CXD4016R

(3) SCLK, XSCEN, SWDT, SRDT pins

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
Clock period tCW 200 — — ns
Clock pulse width, high tCWH 100 — — ns
Clock pulse width, low tCWL 100 — — ns
Enable signal pulse width tCSWH 170 — — ns
Enable signal setup time tCSS 0 — — ns
Enable signal hold time tCSH 100 — — ns
SWDT Setup time tWSU 20 — — ns
SWDT Hold time tWHD 100 — — ns

tCW
tCSH tCSWH
tCSS tCWL tCWH

XSCEN

SCLK

tWSU tWHD

SWDT An example of data read phase

(4) CSOD pin

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
CSOD pulse width tCSOD 260 — — µs

CSOD
tCSOD

(5) XRST pin

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
XRST pulse width tXRST 100.0 — — ns

XRST
tXRST

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 CXD4016R

(6) BCK, DTIN, LRCK pins

(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item Symbol Min. Typ. Max. Unit
DTIN setup time tDTS 10 — — ns
DTIN hold time tDTH 100 — — ns
LRCK skew time tLRSK — — ± 20 ns

BCK VDD/2

tDTS tDTH

DTIN VDD/2

tLRSK

LRCK VDD/2

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 CXD4016R

Description of Functions

Description of clock generator

1. This LSI chip can generate the system clock pulse by connecting a 24.576MHz crystal oscillator to the OSCI
pin and OSCO pin. Also, it incorporates 1MΩ (typ.) feedback resistor between the OSCI and OSCO pins.
2. It functions as the system clock by inputting a 24.576MHz external oscillation clock pulse to the OSCI pin
while keeping the OSCO pin open.
3. Please keep the frequency precision for system clock within 24.576MHz ± 100ppm.

Description of PLL circuit

1. In addition to supplying the system clock pulse using the OSCI pin, this LSI requires the modulation clock
pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this
purpose.
2. If the sampling frequency of the digital audio input signals is fs, then the modulation clock pulse provided
by the PLL circuit has a frequency of 640fs.
3. When the PLL circuit on the LSI is used, input a low level to the EXCKSEL pin and VCOT pin. Furthermore,
an external lag-lead filter must be connected to the LSI for the charge pump current output APCPO pin of
the PLL circuit. Ensure that the wiring involved is kept as short as possible.
4. When the PLL circuit on the LSI is not used, the LSI chip must be provided with an external PLL circuit.
Input a high level to the EXCKSEL pin and the modulation clock pulse to the VCOT pin. The reference
signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set
to fs. At this time, the frequency of the clock pulse which has been input to the VCOT pin is divided by 640
inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin.

Pin setting/serial data interface

The setting modes of this LSI can be broadly classified into two : the pin setting mode and the serial data
interface mode. By setting serial data interface mode, switching between pin setting mode and serial data
interface mode is enabled. For example, setting SCEN01 bit to “0” validate pin setting mode and setting it to
“1” validate serial data interface setting mode during Address 01 in serial data interface mode. (See “(3) Serial
setting command table” on the next page.) Followings are pins which can be set even in the serial data
interface mode.

EXCKSEL pin, DIVCODE pin, CHNM_BL pin, IFEXMD pin, IIFSEL1 pin, IIFSEL0 pin, PCMID pin, EMPIN pin.

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 CXD4016R

Description of serial data interface

1. Serial data interface timings
This LSI enables the various LSI operations to be changed by the SCLK pin, SWDT pin and XSCEN pin.
The interface timing chart for each code group is presented below. Also, the SCLK pin should not be used
with other devices. Normal communication cannot be performed.

2. XRST pin
All the internal registers are initialized to “Default value” presented in the “Serial data interface setting
command table” when reset by setting the XRST pin to low.

XSCEN

SCLK

SWDT A7 A6 A5 A4 A3 A2 A1 A0 Dn – 1 Dn – 2 Dn – 3 D2 D3 D2 D1 D0

Internal
registers Valid

3. Method for disabling the CXD4016R's FSLOCK signal

The LRCK input to the CXD4016R must be a stable clock with no jitter. A PLL that uses LRCK as the
reference is formed inside the CXD4016R, and this PLL generates a 640fs clock. However, the signal
(FSLOCK) that indicates the PLL lock status is generated inside this LSI, and RF generation is temporarily
stopped when the lock is lost. This lock detection logic has strict conditions, so if the LRCK jitter is large,
the jitter of the clock generated by the PLL is also large, and the lock may be judged as lost.
Using a LRCK with large jitter is not recommended, but when a LRCK with large jitter must be used, this
LSI has a test mode that can reduce the RF generation stoppage frequency by disabling the FSLOCK
signal as follows.
FSLOCK can be enabled or disabled by sending the command indicated in the Serial Setting Command Table.
At the default setting, FSLOCK operates according to the lock detection logic.
To forcibly set the FSLOCK status, send address 71h and data 0Fh by the serial setting command.
In addition, to return to the default setting, send address 71h and data 03h by the serial setting command.
Performing this process is highly recommended.

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 CXD4016R

4. Serial setting command table

Signal
Address Default Length
Signal name length Value Effect
(HEX) value [bit]
[bit]
0 Invalidate serial setting of Address 01.
SCEN01 1
1 Validate serial setting of Address 01.
0 APX internal connection.
EXCKSEL 1
1 VCOT pin input.
0 Full-band mode.
DIVCODE 1
1 Half-band mode.

01h 00h 8 0 0ch/full-bit.

CHNM_BL 1
1 1ch/16-bit limited.
0 Normal mode.
IFEXMD 1
1 Extension mode.
IIFSEL1 1 — Audio input interface mode select 1.
IIFSEL0 1 — Audio input interface mode select 0.
res. 1 0 Be sure to set the value to “0”.
0 Invalidate serial setting mode of Address 02.
SCEN02 1
1 Validate serial setting mode of Address 02.
0 CRC off.
CRC_FLG 1
1 CRC on (default).
0 Source_block is error free.
VALID_FLG 1
1 Source_block contains some errors.
02h 40h 8 0 Data is Linear PCM.
PCM_ID 1
1 Data is used for other purposes.
0 Copyright is asserted.
CPRGT_FLG 1
1 No copyright is asserted.
0 No emphasis.
EMPHASIS 1
1 Emphasis.
res. 2 00 Reserved.
03h 69h 8 CATEGORY 8 — Source_info Byte 3 category codes.
res. 4 0000 Be sure to set the value to “0000”.
0 Invalidate serial setting mode of FSLOCK.
FSLOCK_EN 1
1 Validate serial setting mode of FSLOCK.
71h 03h 8
0 Set to unlocked logic forcibly.
FSLOCK 1
1 Set to locked logic forcibly.
res. 2 11 Be sure to set the value to “11”.

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 CXD4016R

Description of audio I/F

1. As shown below, the audio ADC can be directly coupled in this LSI.
DTIN : Connect the data output from ADC
BCK : Connect the bit clock output from ADC (64fs)
LRCK : Connect the sample clock output from ADC (fs)

The sampling frequencies (fs) which can correspond to this LSI are 32kHz, 44.1kHz, 48kHz. Also, the
precision of fs is within ± 1000ppm. If it gets beyond this range even for a second, the normal operation
might not be performed. So care should be taken.

2. This LSI has the LRCKOUT pin, BCKOUT pin and CK12 pin in order to use the audio ADC into which
sample clock and bit clock are required to be input.
LRCKOUT pin : sample clock (48kHz)
BCKOUT pin : bit clock (48kHz × 64)
CK12 pin : master clock (12.288MHz (48kHz × 256) )

Connect the LRCKOUT pin to the sample clock of ADC and the LRCK pin of this LSI. And connect the
BCKOUT pin to the bit clock pin of ADC and the BCK pin of this LSI.

3. Sixty-four BCK cycles are contained in one LRCK cycle.

4. The DTIN input format can be changed by the setting of resistor with address 01h, or the IFEXMD pin,
IIFSEL1 pin and IIFSEL0 pin.
Name of iif_mode IFEXMD IIFSEL [1 : 0] Data input format
mode-0 0 00 MSB first, Left Justified 24 bits
mode-1 0 01 I2S 24 bits
mode-2 0 10 LSB first, Right Justified 24 bits
mode-3 0 11 MSB first, Right Justified 24 bits
mode-4 1 00 MSB first, Right Justified 20 bits
mode-5 1 01 MSB first, Right Justified 16 bits

Note) 1. When CHNM_BL is set to “1” by the CHNM_BL pin or address 01h of serial data interface, only
high-order 16 bits are validated during Full-band mode.
2. Only high-order 16 bits are validated during Half-band mode.

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 CXD4016R

Timing charts covering what has been described above are presented below.

Audio ADC interface timing charts

LRCK Left channel

BCK

DAOUT MSB LSB

mode-0

LRCK Left channel

BCK

DAOUT MSB LSB

mode-1

LRCK Left channel

BCK

DAOUT LSB MSB

mode-2

LRCK Left channel

BCK

DAOUT MSB LSB

mode-3

LRCK Left channel

BCK

DAOUT MSB LSB

mode-4

LRCK Left channel

BCK

DAOUT MSB LSB

mode-5

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 Application Circuit
C1
R1
2.5VA 2.5VD
C2 Rx

Reset
circuit
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DTIN

DT2_INF

VCOT

APAVS

APAVD

APCPO

APVGS

APS

VSS

VDD

APX

PLVAR

PLREF

TEST7

TEST6

TEST5
C1 = 0.1µF
49 LRCK 32 R1 = 2.2kΩ
TEST4 C2 = 4700pF
Audio 50 BCK TEST3 31 Rx = 4.7MΩ

51 BCKOUT TEST2 30

A/D converter 52 LRCKOUT TEST1 29

53 CK12 TEST0 28

54 CSST VSS 27
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55 VSS VDD 26
RREF
56 VDD DAVRO 25
1.1V reference voltage
57 OSCI DAVREF 24
X'tal
24.576MHz 58 VSS DAAVS 23
2.5VA
59 OSCO DAAVD 22
RF
60 XTCK4 DAAOUT 21 LPF
output
RL
61 XSM VSS 20

62 MST VDD 19

63 XTST DACK 18
CHNM_BL
EXCKSEL

DIVCODE
TESTMD

DAPD
IFEXMD

IIFSEL1

IIFSEL0

XSCEN
PCMID
64 XRST 17

EMPIN

SWDT
SMCK

CSOD
SCLK
VDD

VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CXD4016R
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these
circuits or for any infringement of third party patent and other right due to same.
 CXD4016R

Notes on Operation

Æ The loop filter portion of the PLL block is important for the characteristics. Therefore, the loop filter should
be located as close to the IC pin as possible and surrounded by AGND. In addition, temperature
compensation parts should be used for the loop filter capacitor and resistor.

Æ The CXD4016R generates a delay during transmission. Labeling the sampling frequency as fs, the delay
time is 192/fs [s] in full-band mode. For example, when fs = 48kHz, the delay time is 4ms. In addition, in half-
band mode the delay time is 384/fs [s]. In this case for example, when fs = 48kHz, the delay time is 8ms.
Note that a delay is also generated during reception by the receive side IC CXD4017R. See the CXD4017R
data sheet for details.

CXD4016R Evaluation Board

Description
The CXD4016R evaluation board is a dedicated board designed to allow easy evaluation of the CXD4016R
which was developed for transmission of infrared spatial digital audio communication. Optical digital and
analog (pin jack) circuits are mounted, and can be switched by a switch.
The input audio signal is converted to an infrared spatial digital audio communication system format RF signal
by the CXD4016R, and output from a SMB connector.

Features
Æ Supply voltage : + 5V single power supply
Æ Analog and optical digital audio input can be selected

Operating Conditions
Æ Supply voltage : + 5V (typ.)
Æ Current consumption : 150mA (typ.)
Æ Input signal : Analog or optical digital audio signal

Operation Method
The CXD4016R evaluation board allows easy evaluation simply by providing the power supply and inputting
an analog or optical digital audio signal. The evaluation procedure is as follows.
1. Connect the power supply to the power supply connection pin J5.
2. SW1 is the manual reset switch. A reset is applied automatically during power-on, but this switch is used
to perform reset manually.
3. The DIVCODE pin can be set by DIP switch S2-1. The DIVCODE pin is set low when this switch is OFF,
and high when ON.
4. The CHNM_BL pin can be set by DIP switch S2-2. The CHNM_BL pin is set low when this switch is OFF,
and high when ON.
5. The IFEXMD pin can be set by DIP switch S2-4. The IFEXMD pin is set low when this switch is OFF, and
high when ON
6. The IIFSEL1 pin can be set by DIP switch S2-5. The IIFSEL1 pin is set low when this switch is OFF, and
high when ON.
7. The IIFSEL0 pin can be set by DIP switch S2-6. The IIFSEL0 pin is set low when this switch is OFF, and
high when ON.
8. The audio signal can be selected by DIP switch S2-7. The optical digital audio signal is selected when this
switch is OFF, and the analog audio signal when ON.
9. Connect the optical digital audio signal to the U8 square optical connector.
10. Connect the analog audio signal to the J1 pin jack.

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 CXD4016R

11. When the analog audio signal is selected, the sampling frequency can be changed by DIP switch S2-8.
48kHz is set when this switch is OFF, and 44.1kHz when ON.
12. Always set DIP switches other than noted above to OFF. The above contents are listed in the tables below
for reference.
S1 Mode
1 Always OFF
2 Always OFF
3 Always OFF
4 Always OFF
5 Always OFF
6 Always OFF
7 Always OFF
8 Always OFF

S2 Mode
1 OFF : DIVCODE = L, ON : DIVCODE = H
2 OFF : CHNM_BL = L, ON : CHNM_BL = H
3 Always OFF
4 OFF : IFEXMD = L, ON : IFEXMD = H
5 OFF : IIFSEL1 = L, ON : IIFSEL1 = H
6 OFF : IIFSEL0 = L, ON : IIFSEL0 = H
7 OFF : Optical digital, ON : Analog
8 OFF : 48kHz, ON : 44.1kHz (only when the analog audio signal is selected)

13. Light emitting diode D1 is off when DIVCODE is low, and lighted when DIVCODE is high.
14. Light emitting diode D2 is off when CHNM_BL is low, and lighted when CHNM_BL is high.
15. Light emitting diodes D3 and D4 indicate the sampling frequency of the audio signal. This relationship is
shown in the table below.

D3, D4 Sampling frequency

Off, off 44.1kHz
Off, lighted 48kHz
Lighted, lighted 32kHz
Flashing, flashing Unlock

16. Light emitting diodes D5 to D8 are not used.

17. The infrared spatial digital audio communication system format RF signal is output from SMB connector J8.
18. J2 and J3 are not used.

- 18 -
 CXD4016R

CXD4016R EVB Semiconductor Parts List

Parts No. Product name Manufacturer

U1, 3 NJM2100M New Japan Radio
U2 AK5353VT Asahi Kasei Microsystems
U4, 21 TC74LCX541F Toshiba
U5 CXD4016R SONY
U6 TC74VHC04F Toshiba
U7 CS8415A-CZ Cirrus Logic
U8 TORX141P Toshiba
U9 FXO-31FL 24.576MHz Kyocera Kinseki
U10 EP1K100QI208-2 ALTERA
U11 EPC2LI20 ALTERA
U12 FXO-31FL 22.5792MHz Kyocera Kinseki
U13, 14, 15, 16, 17, 18 LM317A National Semiconductor
U19, 20 TL7705CP Texas Instruments
U22 AD8057ART Analog Devices
Q1 2SC2223L NEC
D1, 2 TLG124 Toshiba
D3, 4 TLY124 Toshiba
D5, 6 TLO124 Toshiba
D7, 8 TLR124 Toshiba
D9 to 20 1S1588 Toshiba

FPGA Operation
1. Selects the optical digital audio signal or the analog audio signal selected by S2-7.
2. Converts the selected audio signal to the DTIN pin input format set by S2-4, S2-5 and S2-6.
3. Detects the sampling frequency.

- 19 -
 Circuit Diagram
PLD1 CXD4016R
AIF

SDTO_1 SDTO_1
LRCK_AD LRCK_AD
MCLK MCLK
(High-speed Signal)
SCLK_AD SCLK_AD
PDN PDN DT2_INF DT2_INF
DTIN DTIN
LRCK LRCK
APS_XRST APS_XRST
DIF BCK (High-speed Signal)
BCK
BCKOUT BCKOUT
COPY COPY
LRCKOUT LRCKOUT
EMPH EMPH
CSOD CSOD
RST RST
CK12 (High-speed Signal)
CK12
RERR RERR
CSST CSST
RCBL RCBL
XRST XRST
PRO PRO
IFEXMD IFEXMD
CHS CHS
IIFSEL1 IIFSEL1
NVERR NVERR
IIFSEL0 IIFSEL0
OSCLK OSCLK
- 20 -

EXCKSEL EXCKSEL
OLRCK OLRCK
CHNM_BL CHNM_BL
SDOUT SDOUT
DIVCODE DIVCODE
AUDIO AUDIO
PCMID PCMID
U U
EMPIN EMPIN
C C

ORIG ORIG
SCLK SCLK
RMCK RMCK (Middle-speed Signal)
(High-speed Signal)
XSCEN XSCEN
RFOUT
DAPD DAPD

SWDT SWDT
DAAOUT DAAOUT

PWXRST

XRSTPW1 XRSTPW1

XRSTPW2 XRSTPW2

POWER

CXD4016R
CXD4016R EVB circuit diagram (TOP)
 VA5

C1 C2
22µ/16V 0.1µ R1 R2
20k 10k
A A
AINL1 AINR1
TP1 TP2
C3 R3 LC-2S-W LC-2S-R DGND
R4 A

8
22µ/16V 20k TP3

4
2 10k R5 R6 LC-2S-BK
1 6 330 470 VD5
3 7

1
VA5 5
R7

1
U1A C4 C5
330k 4.7µ/16V T R9 D
R8 NJM2100M U1B 2200p
4.7k 10k
J1 NJM2100M U2
RCA JACK 2P A A
C6 C7 1 16
Rch_1 3 4.7µ/16V T AINR TST
(RED) RV1A C8 C9 R10 0.1µ 2 15
AINL TTL
50k 22µ/16V 0.1µ 4.7k 3 14
2 VREF DIF
3

Lch_1 2 A 4 13
(WHITE) VCOM PDN
A A A C10 C11 5 12
AGND SCLK
1

4.7µ/16V T 0.1µ
1

6 11
VA MCLK
A C13 7 10
A VA5 C12 VD LRCK
0.1µ 8 9
A 10µ/16V T DGND SDTO
- 21 -

C14 C15 R11 R12 AK5353VT

22µ/16V 0.1µ 20k 10k
A D
A A
VA5
RV1B C16 R13
50k A MCLK
8

22µ/16V 20k R14

6

TP4
4

5 2 10k R15 R16 VD5 R19

1 6 330 470 LC-2S-Y
3 7 100
VA5 5 SDTO_1
4

R17
C17

1
330k U3A C20 C18 C19
R18 NJM2100M U3B 4.7µ/16V T 2200p 10µ/16V T 0.1µ
A 4.7k NJM2100M
A A SCLK U4
AGND TP6 11 10
TP5 D Y8 GND
LC-2S-G 12 9
C21 C22 R20 LC-2S-BK Y7 A8
0.1µ R21 100 13 8
22µ/16V 4.7k Y6 A7
R22 100 14 7

1
Y5 A6 PDN

1
R23 22 15 6
A A A A
Y4 A5 SCLK_AD
R24 100 16 5
Y3 A4 MCLK
17 4
Y2 A3 LRCK_AD
18 3
Y1 A2
19 2
G2 A1
20 1
VCC G1
TC74LCX541F
D

VD33 C23
0.1µ

CXD4016R EVB Circuit Diagram (AUDIO)

CXD4016R
 PLVAR PLREF
R25 TP7 TP8
2.2k LC-2S-BL LC-2S-Y
R26 C24
4.7M 4700p

1
C25
0.1µ

A APS APX
TP9 TP10
LC-2S-Y LC-2S-Y
D

1
APS_XRST

DT2_INF VA25P
R28
DTIN TP11 0
TP12 LC-2S-BL R27 R29 R30 R31 VD25D
LC-2S-Y 22 C26 C27 0 100 100
0.1µ 0.1µ

1
A

1
DT2_INF A
DTIN
TP17 TP18

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LRCKOUT BCKOUT BCK LRCK
TP13 TP14 TP15 TP16 LC-2S-BK LC-2S-BK
AGND DGND

DTIN
DT2_INF
VCOT
APAVS
APAVD
APCPO
APVGS
APS
VSS
VDD
APX
PLVAR
PLREF
TEST7
TEST6
TEST5
LC-2S-G LC-2S-BL LC-2S-Y LC-2S-Y
1

1
49 32
LRCK LRCK TEST4
A D
50 31
BCK BCK TEST3
R32 100 51 30
BCKOUT BCKOUT TEST2
R33 100 52 29
LRCKOUT LRCKOUT TEST1 VA25A
R34 22 53 28
- 22 -

CK12 CK12 TEST0

C28
54 27 0.1µ DAVREF
CSST CSST VSS
C29 0.1µ TP21 R35
TP19 TP20 55 26
1

VSS VDD R36 LC-2S-G 1.2k

LC-2S-BL LC-2S-Y
CK12 C30 CSST U5 2.7k

A
56 25
18p VDD DAVRO

3
1
57 CXD4016R 24 2
OSCI DAVREF VR1
D

C31 200

A
58 23 0.1µ
CX-49G_24.576MHz Y1 VSS DAAVS VA25D

1
59 22 C32
OSCO DAAVD R38
DAAOUT 0.1µ

A
60 21 910
D

C33 XTCK4 DAAOUT TP22

27pF 61 20 C34 R39 LC-2S-Y
XSM VSS 0.1µ 150

1
A A
62 19
R37 is missing number. MST VDD R40
63 18 0
XTST DACK VA5 VA5
64 17
XRST XRST DAPD DAPD

CHNM_BL
EXCKSEL

DIVCODE
R41

1
TESTMD

IFEXMD
IIFSEL1
IIFSEL0
0

XSCEN
C35

PCMID
EMPIN

SWDT
SMCK

CSOD
SCLK
0.1µ

VDD
TP23

VSS
TP24
DAPD DACK R42 A
IFEXMD IIFSEL1 IIFSEL0 EXCKSEL LC-2S-Y LC-2S-Y 4.7k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TP25 TP26 TP27 TP28
LC-2S-Y LC-2S-G LC-2S-G LC-2S-BL DAAOUT_Buf
C36 TP29
0.01µ LC-2S-Y
Q1
1

2SC2223L

1
IFEXMD C37 R43 C38
0.1µ 100 D
0.01µ
IIFSEL1
CSOD DAAOUT
1
IIFSEL0 TP30
LC-2S-G
EXCKSEL 1 SCLK
TP31 R44 R45
CHNM_BL LC-2S-Y 10k 1k
1 XSCEN
DIVCODE TP32
LC-2S-Y
PCMID 1 SWDT
TP33 A A
EMPIN LC-2S-Y
1

CXD4016R
SCLK
XSCEN
SWDT
CSOD
TP34 TP35 TP36 TP37
EMPIN PCMID DIVCODE CHNM_BL
LC-2S-BL LC-2S-BL LC-2S-Y LC-2S-Y

CXD4016R EVB Circuit Diagram (MAIN)

 VD33

VD33 VD33
C39 C40
U6 0.1µ SPDIF 0.01µ

D
1 1A VCC 14 TP38 R47 R46
2 1Y 6A 13 LC-2S-Y 100 47k D
3 12 U7 D
2A 6Y COPY
4 2Y 5A 11
5 3A 10 1 COPY ORIG 28
5Y EMPH ORIG

1
6 9 2 VL2+ VL3+ 27
7 3Y 4A 8 3 26
GND 4Y EMPH C C
C42 0.01µ 4 RXP0 U 25
R48 C41 5 24 U
74VHC04F RXN0 H/S R49 R50
D D 47k 0.01µ VA5 6 23 100

D
7 VA+ VL+ 22 100
AGND DGND R51
VD33 D 8 21 47k
FILT DGND2

A
RST 9 20 D
R52 22 10 RSTx DGND3 19 R53 100
RMCK RMCK AUDIOx AUDIO
R54 100 11 18 R55 100 SDOUT
RERR R56 100 12 RERR SDOUT 17 R57 100
L1 RCBL 0 RCBL OLRCK 16 OLRCK
R58 13 R59 100
47µH PRO 14 PRO OSCLK 15 R60 100 OSCLK
CHS CHS NVERR NVERR
- 23 -

U8 CS8415A-CZ
OUT 1 R61
GND 2 1.2k
3 C43 C44
VCC 4 C45
NC 0.1µ 1000p 4700p
5 C46
NC C47
0.1µ 0.1µ
TORX141P

A A
D

AGND DGND
TP39 TP40
LC-2S-BK LC-2S-BK

1
1

A D

CXD4016R EVB Circuit Diagram (DIGITAL INTERFACE)

CXD4016R
 J2
U9

IFdata10
VD33 10

IFdata9

IFdata8
IFdata7
IFdata6
4 3 IFdata10 9 GND
VDD OUT A9

IFdata5
IFdata4
IFdata3
IFdata2
IFdata1
22
C48 8
1 2 VD25B IFdata9 7 GND
0.1µ INHX GND 6 A7
IFdata8 GND

R62
D FXO-31FL_24.576MHz D 5
4 A5
IFdata7 3 GND
2 A3
IFdata6 1 GND
A1
TH1 TH2 TH3 TH4 TH5 TH6
TH TH TH TH TH TH IL-10P-S3EN2

9
8
7
6
5
4
3
2
1
COM
R8
R7
R6
R5
R4
R3
R2
R1
D
C49 C50 C51 C52
0.1µ 0.1µ 0.1µ 0.1µ VD33
VD33 RA1 J3
M9-1-103J 10
R64 IFdata5 9 GND
A9

208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
1k 8
IFdata4 7 GND
R63 6 A7

nCS
CS
nWS
IFdata10
nRS
IFdata9
I_O
VCCINT
IFdata8
I_O
IFdata7
I_O
IFdata6
I_O
VCCIO
I_O
I_O
I_O
I_O
I_O
GND
I_O
DEV_OE
VCCINT
Ded_Input
CRYST24M
Ded_Input
GND
DEV_CLRn
I_O
VCCIO
I_O
I_O
I_O
IFdata5
I_O
IFdata4
GND
IFdata3
I_O
IFdata2
IFdata1
DATA7
VCCIO
DATA6
I_O
DATA5
DATA4
I_O
DATA3
DATA2
DATA1
10k IFdata3 5 GND
4 A5
1 156 IFdata2 3 GND
TP41 TP42 TP43 TP44L TCK DATA0 A3
LC-2S-G LC-2S-Y LC-2S-BL C-2S-Y 2 155 2
3 CONF_DONE DCLK 154 IFdata1 1 GND
SCLK_AD MCLK LRCK_AD SDTO1 nCEO nCE A1
4 153
5 TDO TDI 152
C53 VCCIO VCCINT IL-10P-S3EN2

9
8
7
6
5
4
3
2
1
6 151 C54
1

1
0.1µ 7 GND GND 150 0.1µ R65 100

COM
R8
R7
R6
R5
R4
R3
R2
R1
SDTO_1 SDTO_1 DT2_INF DT2_INF D
8 149 R66 100 DTIN
R67 100 9 I_O DTIN 148 R68 100
LRCK_AD LRCK_AD LRCK 147 LRCK
10 RA2
R69 22 11 CLKUSR_I_O USER_IO 146
MCLK MCLK VCCIO C55 M9-1-103J
TH7 12 145
R70 100 TH 13 I_O GND 144 0.1µ R71 0
SCLK_AD SCLK_AD APS_XRST 143 100 APS_XRST
14 R72 BCK
R73 100 15 I_O BCK 142
PDN PDN BCKOUT BCKOUT
16 141 TP45 TP46
17 RDYnBUSY I_O 140
I_O LRCKOUT LRCKOUT LC-2S-BK LC-2S-BK
COPY 18 139 CSOD DGND DGND
19 COPY CSOD 138
C56 20 INIT_DONE VCCIO 137 C57
0.1µ 21 GND GND 136 0.1µ
VCCINT CK12 CK12

1
22 135
C58 23 VCCIO I_O 134 R74 100
GND CSST CSST D D
0.1µ 24 133
EMPH EMPHx I_O R76 100
RST R75 100 25 132 XRST
26 RSTx XRST 131
- 24 -

RERR RERR IFEXMD IFEXMD

RCBL 27 U10 130
28 RCBL VCCINT 129 C59
PRO PRO EP1K100QI208-2_1 GND 0.1µ
29 128 IIFSEL1
R77 100 30 I_O IIFSEL1 127
CHS CHS IIFSEL0 IIFSEL0
NVERR 31 126 EXCKSEL
32 NVERR EXCKSEL 125
SDOUT OLRCK OSCLK C60 GND CHNM_BL CHNM_BL
LC-2S-Y 0.1µ 33 124
LC-2S-BL LC-2S-G 34 VCCINT VCCINT 123 C61
TP47 TP48 TP49 C62 35 VCCIO GND 122 0.1µ
0.1µ GND DIVCODE DIVCODE
1

OSCLK 36 121
37 OSCLK I_O 120
OLRCK OLRCK PCMID PCMID
TH8 38 119 TH9
TH 39 I_O I_O 118
SDOUT SDOUT VCCIO TH
TH10 40 117 C63
TH 41 I_O GND 116 0.1µ
AUDIO AUDIOx EMPIN 100 EMPIN
42 115 R78 SCLK
C64 43 VCCIO SCLK 114
0.1µ 44 GND I_O 113 R79 100
U U XSCEN XSCEN
C 45 112 DAPD
46 C DAPD 111 R80 100
TH11 I_O SWDT SWDT
ORIG TH 47 110
48 ORIG VCCIO 109 C65
C66 49 VCCINT GND 108 0.1µ
0.1µ 50 GND MSEL0 107
TMS MSEL1 C67

GlobalCLK1
CRYST22M
51 106

VCC_CKLK
TRST VCCINT 0.1µ

GND_CLK
Ded_Input
Ded_Input
GL_CLK1
52 105
DSW1_1
DSW1_2
DSW1_3
DSW1_4
DSW1_5
DSW1_6
DSW1_7
DSW1_8

DSW2_1
DSW2_2
DSW2_3
DSW2_4
DSW2_5

DSW2_6
DSW2_7
DSW2_8
nSTATUS nCONFIG
VCCINT

VCCINT
RMCK
VCCIO

VCCIO

VCCIO
LOCK
LED1
LED2
LED3
LED4

LED5
LED6
LED7
LED8
GND

GND

GND
I_O
I_O

I_O

I_O

I_O

I_O

I_O
I_O

I_O
I_O
I_O
D
RA3
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
M5-1-102J
TH12

COM
20
19
TH VD33

3
2
1

R1
R2
R3
R4
U11
DSW2_1
DSW2_2
DSW2_3
DSW2_4
DSW2_5
DSW2_6
DSW2_7
DSW2_8

XRSTPW1 VD33

TCK
DATA
TDO
VCC
TMS
TH13 VD33

1
2
3
4
5
LED1
LED2
LED3
LED4

TH14 TH
TH R82 4 18
TH15 5 DCLK VPP 17
10k VCCSEL NC 16
C68 R81 C73 C69 C70 C71 C72 TH 6 1 2
7 NC NC 15 3 TCK GND 4
0.1µ 22 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ NC
8 NC 14 5 TDO Vcc 6 C74
RA4 OE VppSel 7 TMS NC 8

nInt_Conf
100 LED1

100 LED2

100 LED3

100 LED4

RA5 DSW2_1
DSW2_2
DSW2_3
DSW2_4

DSW2_5
DSW2_6
DSW2_7
DSW2_8
NC NC 0.1µ

100 LED5

100 LED6

100 LED7

100 LED8
9 9 9 10

nCASC
RMCK
LED5
LED6
LED7
LED8

R8 8 R8 8 1
TDI GND

GND
R7 R7 C75

nCS
7 7 J4

TDI
R6 R6 LC-2S-Y 0.1µ XG4C-1031
6 6 EPC2LI20 D
R5 5 R5 5 TP50 R91

9
10
11
12
13
R4 4 R4 4 1k
R3 R3 D
3 3

R87

R88

R89

R90
RMCK XRSTPW2
R83

R84

R85

R86

R2 2 R2 2 VD33
R1 1 R1 1 U12 D
D1

D2

D3

D4

D5

D6

D7

D8
COM COM 3 4
OUT VDD
1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

M9-1-103J D M9-1-103J C76

D 2 1
FULL/HALF

GND INHX 0.1µ

CXD4016R
A6E-8104 ON ON
CHNM_BL

A6E-8104 D

TLO124

TLO124

TLR124

TLR124
TLG124A

TLG124A

STA_5

STA_6

STA_7

STA_8
S1 S2
TLY124

TLY124

VD25B FXO-31FL_22.5792MHz VD25B

D
Fs_1

Fs_0

VD25B VD25B
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

CXD4016R EVB Circuit Diagram (PLD)

 TP51
LC-2S-R
+5V

1
L2 VD5
SN3-200

C77 C78 C79 C80

J5 22µ/16V 0.1µ 0.1µ 47µ/16V
1
2 D D
JP1 L3 VA5
IL-2P-S3EN2 SN3-200
A D

C81 C82
0.1µ 47µ/16V
TP52 TP53
LC-2S-BK LC-2S-BK A A
AGND AGND
1

A A

D9 D10 D1
1S1588 1S1588 1S15881 A2.5V_P
D2.5V_B VD25B D2.5V_D VD25D VA25P
TP54 TP55 TP56
LC-2S-G L4 RM1 LC-2S-G L5 RM2 LC-2S-O L6 RM3
U13 LM317A SN3-200 U14 LM317A U15 LM317A SN3-200 0
0 SN3-200 0

1
1

1
3 2 3 2 3 2
VIN VOUT VIN VOUT VIN VOUT
ADJ

ADJ

ADJ
R92 D12 C83 C84 R93 D13 C85 C86 R94 D14 C87 C88
- 25 -

240 1S1588 0.1µ 47µ/16V 240 1S1588 0.1µ 47µ/16V 240 1S1588 0.1µ 47µ/16V

1
C92 C94
1

1
C89 C90 C91 C93
0.1µ 0.1µ 0.1µ
47µ/16V 47µ/16V 47µ/16V
D D D D A A

3
3

2 VR2 R95 C95 2 VR3 R96 C96 2 VR4 R97 C97

500 270 10µ/16V D D 500 270 10µ/16V D D 500 270 10µ/16V A A
R98 R99 R100

1
1

1
750 750 750
A A A
R101 R102 R103
270 270 270

A A A A A A

D15 D16 D17

1S1588 D3.3V 1S1588 A2.5V_D VA25D 1S1588 A2.5V_A
VD33 TP58 TP59 VA25A
TP57
LC-2S-R L7 RM4 LC-2S-O L8 RM5 LC-2S-O L9 RM6
U16 LM317A SN3-200 U17 LM317A SN3-200 U18 LM317A SN3-200
0 0

1
0

1
1

3 2 3 2 3 2
VIN VOUT VIN VOUT VIN VOUT
ADJ

ADJ

ADJ
R104 D18 C98 C99 R105 D19 C100 C101 R106 D20 C102 C103
240 1S1588 0.1µ 47µ/16V 240 1S1588 0.1µ 47µ/16V 240 1S1588 0.1µ 47µ/16V

1
C107
1

C109
1

C104 C105 C106 C108

0.1µ 0.1µ 0.1µ
47µ/16V 47µ/16V 47µ/16V
D D A A A A
3

3
3

2 VR5 C110 2 VR6 R107 C111 2 VR7 R108 C112

R111 R112 50 10µ/16V D D 500 270 10µ/16V A A 500 270 10µ/16V A A
270 100 R109 R110
1

1
750 750
A A A
R113 R114
270 270

A A A A A

CXD4016R
CXD4016R EVB Circuit Diagram (POWER)
 VD5 VD5 VD5 XRSTPW1 VD5 VD5
TP60
LC-2S-Y

1
R115
10k U19 C113 U20 C114
0.1µ R116 0.1µ XRSTPW2
1 Vref 8 1 Vref VCC 8 R117 TP61
2 VCC 7 10k 2 7 10k
RESIN VsSENSE 6 C115 VD25B RESIN VsSENSE LC-2S-Y
SW1 3 D 3 Ct RESET 6 D
Ct RESET 5

1
AB-15AH 4 0.1µ 4 GND 5
GND RESET RESET
TL7705CP TL7705CP
C117 U21
0.1µ R118 1 20 R119
1

G1 VCC C119 10k

- 26 -

C116 10k 2 19 C118

4.7µ/16V T A1 G2 4.7µ/16V T 0.1µ
3 18
4 A2 Y1 17
5 A3 Y2 16
td = 60ms 6 A4 Y3 15 td = 60ms
D A5 Y4 D
7 14 XRSTPW1
8 A6 Y5 13
9 A7 Y6 12
10 A8 Y7 11
GND Y8 XRSTPW2
TC74LCX541F

CXD4016R EVB Circuit Diagram (RESET)

CXD4016R
 TP62
LC-2S-BK
AGND

1
Emitter Voltage Source
A
J6
1
VA5 2
C120
0.1µ IL-2P-S3EN2
C121
3p A

3
U22 A
1 5 2 L10
OUT VCC TP63 68µH
2 C122 VR8 LC-2S-Y (Large Size)
VEE 3p 10k

1
TP64 TX_LED J7
3 4
- 27 -

LC-2S-BK IN+ IN– F-CONNECTOR

AGND VA5 C123
A 0.1µ NF-R-2
AD8057ART

1
1
1

R120
1k

2
A R121 C124
2.2k 0.1µ
A
R122 L11 L12 R123 C126 C125
300 6.8µH 12µH 0 2200p 2200p
DAAOUT J8
R124 SMB
75
3

A A RF OUT
2 R125
C127 C128 C129 C130
27p 120p 120p 10p VR9 2.2k
10k
1

A
A A A A A A

CXD4016R EVB Circuit Diagram (RFOUT)

CXD4016R
 CXD4016R

Pattern Diagram

CXD4016R EVB A Side Pattern Diagram

CXD4016R EVB B Side Pattern Diagram

- 28 -
 CXD4016R

CXD4016R EVB GND Layer Pattern Diagram

CXD4016R EVB Power Supply Layer Pattern Diagram

- 29 -
 CXD4016R

CXD4016R EVB A Side Silk Diagram

CXD4016R EVB B Side Silk Diagram

- 30 -
 CXD4016R

Package Outline

(Unit : mm)

64PIN LQFP (PLASTIC)

12.0 ± 0.2
+ 0.2
10.0 ± 0.1 1.5 – 0.1

48 33

49 32

A
64 17

1 16
0.5 b
0.08 M 0.08 S

0.25
0.1 ± 0.1 0.20 ± 0.05
0.6 ± 0.15

0.145 ± 0.055
0.5 ± 0.2

DETAIL B
0° to 8°

DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-64P-L023 TERMINAL TREATMENT SOLDER PLATING

JEITA CODE P-LQFP64-10X10-0.5 TERMINAL MATERIAL 42 ALLOY

JEDEC CODE PACKAGE MASS 0.32g

LEAD PLATING SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL 42 ALLOY
SOLDER COMPOSITION Sn-2%Bi
PLATING THICKNESS 5-20µm

- 31 - Sony Corporation