Introduction to Verilog HDL

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Digital Systems Design

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 Modeling Digital Systems
• HDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost and
time
– avoid design errors!

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Generation of ICs

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IC Design Flow

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IC Design Flow

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Hardware Description Languages
• HDL can be used to describe any digital
system:
• For example, a computer or a component.
• A digital system can be described at several
levels:
• Switch level: wires, resistors and transistors
• Gate level: logic gates and flip flops
• Register Transfer Level (RTL): registers and
the transfers of information between registers.
Basic Limitation of HDL
Description of digital systems only
 Application Areas of HDL
System Specification
Suitable for all levels
Behavioral level
Not suitable
HW/SW
Partition

Hardware Softwre
Spec Spec

ASIC

FPGA Boards
Software
&
PLD Systems

Std Parts
 Why use HDL?
• Text-based
• Allows simulation before building
circuit
• Can be compiled (synthesized)
into logic circuit
• Much easier to write test
benches
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 Why use HDL?
• More abstract models of circuits
▪Easier to write
▪Simulates faster
• More flexible
• Provides sequencing
• A major par of Verilog’s success:
▪It allowed both the model and the
testbench to be described together
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 Two Major HDLs
• VHDL
• Verilog HDL
• Virtually every chip (FPGA, ASIC,
etc.):
▪ Designed in part using one of these
two languages
• Combines structural and behavioral
modeling styles. 12
 VHDL
• “V” is short for Very High Speed
Integrated Circuits.
• Designed for and sponsored by US
Department of Defense.
• Designed by a committee (1981-1985).
• Syntax based on Ada programming
language.
• Was made an IEEE Standard in 1987.
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 Verilog HDL
• Introduced in 1985 by Gateway
Design System Corporation:
▪ Now a part of Cadence Design
Systems, Inc.
• Became an IEEE Standard in 1995
• Syntax based on C programming
language.
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 Verilog Compared to VHDL
• Verilog and VHDL are comparable languages
• VHDL has a slightly wider scope
▪ System-level modeling
▪ Fewer sources of nondeterminism (e.g., no
shared variables)
• VHDL is harder to simulate quickly
• VHDL has fewer built-in facilities for
hardware modelling
• VHDL is a much more verbose language
▪ Most examples don’t fit on slides
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Design Methodology

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 Introduction to Verilog
• Verilog is Hardware description language(HDL).
• It describes digital system like MP, FF, Registers, Memory etc.
• HDL descriptions provide technology-independent documentation of
a design and its functionality.
• Design style :
→ Bottom-up -- Each design is performed at gate level
→ Top Down -- Desired style of all designers- early testing is done.
 Abstraction Levels in HDLs

Behavioral

RTL Our focus

Gate

Layout (VLSI)
Concept of Verilog “Module”

• In Verilog, the basic unit of hardware is called a module.

module module_name (list_of_ports);

input/output declarations;

local net declarations;

parallel statements;

endmodule
Example 1 :: simple AND gate

module simpleand (f, x, y);

input x, y;
output f;
assign f = x & y;
endmodule
Example 2 :: two-level circuit

module two_level (a, b, c, d, f);

input a, b, c, d;
output f;
wire t1, t2;
assign t1 = a & b;
assign t2 = (c | d);
assign f = t1 ^ t2;
endmodule
Variable Data Types

• A variable belongs to one of two data types:

–Net
• Must be continuously driven
• Used to model connections between continuous
assignments & instantiations
–Register
•Retains the last value assigned to it
•Often used to represent storage elements
Net data type

– Different ‘net’ types supported for synthesis:

– wire, supply0, supply1

– ‘supply0’ / ‘supply1’ model power supply connections.

Register data type

–Different ‘register’ types supported for synthesis:

reg, integer

–The ‘reg’ declaration explicitly specifies the size.

reg x, y; // single-bit register variables
reg [15:0] bus; // 16-bit bus, bus[15] MSB

–For ‘integer’, it takes the default size, usually 32-bits

Specifying Constant Values

A value may be specified in either the ‘sized’ or the ‘un-sized’

form.
Syntax for ‘sized’ form:
<size>’ <base> <number>
•Examples:
8’b01110011 // 8-bit binary number
12’hA2D // 12-bit hexadecimal number
1’b0 // Logic 0
1’b1 // Logic 1
Primitive Gates

• Primitive logic gates (instantiations):

• and G (out, in1, in2);
• nand G (out, in1, in2);
• or G (out, in1, in2);
• nor G (out, in1, in2);
• xor G (out, in1, in2);
• xnor G (out, in1, in2);
• not G (out1, in);
• buf G (out1, in);
Verilog Operators

• Arithmetic operators
*, /, +, -, %
• Logical operators
! logical negation
&& logical AND
|| logical OR
• Relational operators
>, <, >=, <=, ==, !=
• Bitwise operators
~, &, |, ^, ~^
Description Styles in Verilog

• Three different styles of description:

1.Gate Level
• Gate Level assignment
2.Data flow
• Continuous assignment
3.Behavioral
• Procedural assignment
Gate Level Modeling

• Logic gates can be used to design logic circuits

• Basic Logic gates defined by Verilog – Primitives

• Not, And, Or, Xor, Xnor, Buf

• Examples
module generate_sum (a, b, c);
input a, b;
output c;
xor (c, a, b);
endmodule
Data-flow Modeling

• Identified by the keyword “assign”.

assign a = b & c;
assign f[2] = c[0];

• The assignment is continuously active.

• Almost exclusively used to model combinational logic.

module generate_sum (a, b, c);
input a, b;
output c;
assign c = a+b;
endmodule
Behavioral Modeling

• The procedural block defines

–A region of code containing sequential statements.
• Two types of procedural blocks in Verilog
–The “always” block
•A continuous loop that never terminates.
–The “initial” block
•Executed once at the beginning of simulation (used in
Test-benches).
module AND_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule
module OR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule
 HDL Compiler and the Design Process
➢ HDL Compiler translates Verilog language hardware descriptions to the Synopsys
internal design format.
➢ Design Compiler can then optimize the design and map it to a specific ASIC
technology library.
Logic Values
• 0: zero, logic low, false, ground

• 1: one, logic high, power

• X: unknown

• Z: high impedance, unconnected, tri-state

 Operators
{} concatenation ~ bit-wise NOT
+ - * / arithmetic & bit-wise AND
% modulus | bit-wise OR
> >= < <= relational ^ bit-wise XOR
^~ ~^ bit-wise XNOR
! logical NOT
& reduction AND
&& logical AND
| reduction OR
|| logical OR ~& reduction NAND
== logical equality ~| reduction NOR
!= logical inequality ^ reduction XOR
?: conditional ~^ ^~ reduction XNOR
<< shift left
>> shift right
 Operator Precedence
[ ] bit-select or part-select >, >=, <, <=relational
( ) parentheses ==, != logical equality
!, ~ logical and bit-wise & bit-wise AND
negation ^, ^~, ~^
&, |, ~&, ~|, ^, ~^, ^~ bit-wise XOR and XNOR
reduction operators
| bit-wise OR
+, - unary arithmetic
&& logical AND
{ } concatenation
|| logical OR
*, /, % arithmetic
?: conditional
+, - arithmetic
<<, >> shift
Data Types
• Nets.
• Nets are physical connections between devices.
• Nets always reflect the logic value of the driving device.
• Many types of nets, but all we care about is wire.
• Registers & Parameters.
• Implicit storage – unless variable of this type is modified it retains previously assigned
value.
• Does not necessarily imply a hardware register.
• Register type is denoted by reg .

➢A register holds its value until a new value is assigned to it.

➢Registers are used extensively in behavior modeling and in applying
stimuli.
➢Parameters are not variables, they are constants.
Variable Declaration
• Declaring a net
wire [<range>] <net_name> [<net_name>*];
Range is specified as [MSb:LSb]. Default is one bit wide

• Declaring a register
reg [<range>] <reg_name> [<reg_name>*];

• Declaring memory
reg [<range>] <memory_name> [<start_addr> : <end_addr>];

• Examples
reg r; // 1-bit reg variable
wire w1, w2; // 2 1-bit wire variable
reg [7:0] vreg; // 8-bit register
reg [7:0] memory [0:1023]; a 1 KB memory
1. Introduction

➢ ModelSim is a verification and simulation tool for

VHDL, Verilog, SystemVerilog, and mixed-
language designs.

➢ Software : ModelSim-Altera 6.6d Starter Edition

➢ References :
▪ Introduction to Simulation of Verilog Designs Using ModelSim
Graphical Waveform Editor (Altera).

▪ ModelSim Tutorial (Mentor Graphics).

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2. Design Project
Simple example : f(x1, x2, x3) = x1x2 + x2x3 + x3x1

Verilog code :

module majority(x1, x2 ,x3 ,f);

input : x1, x2, x3;

output: f;

assign f = (x1&x2)|(x2&x3)|(x3&x1);

endmodule;

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2. Design Project
Open the ModelSim simulator. In the displayed
window select File > New > Project

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2. Design Project
A Create Project pop-up box will appear…

1.Enter the name

of the project

Choose Project
Location

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2. Design Project
Create new file…

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2. Design Project

Double click

Text Editor

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2. Design Project
Or add existing file…

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2. Design Project
After completed coding, select Compile > Compile all

Compile of majority.v was successfull

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3. Simulate without testbench
Select Simulate > Start simulation…, Start Simulation
window will appear…

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3. Simulate without testbench
Simulation window…

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3. Simulate without testbench
Create waveforms for Simulation…

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3. Simulate without testbench
Modify waveforms for Simulation…

Right click

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3. Simulate without testbench
Waveform window…

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3. Simulate without testbench
Waveform window…

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3. Simulate without testbench
With output signal…

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3. Simulate without testbench
Simulate…Select Run all

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3. Simulate without testbench
Result…

To stop simulation, slect Simulate > End simulation

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