AD82587D EliteSemiconductor

ESMT AD82587D
2X20W Stereo / 1X40W Mono Digital Audio Amplifier
Features
2
 16/18/20/24-bit input with I S, Left-alignment  Anti-pop design
 Short circuit and over-temperature protection
and Right-alignment data format 2
 I C control interface with selectable device address
 PSNR & DR(A-weighting)
 Internal PLL
Loudspeaker: 97dB (PSNR), 105dB (DR) @ 24V
 LV Under-voltage shutdown and HV Under-voltage
 Multiple sampling frequencies (Fs)
detection
32kHz / 44.1kHz / 48kHz and
64kHz / 88.2kHz / 96kHz and  Power saving mode
128kHz/176.4kHz/192kHz  Dynamic temperature control
 System clock = 64x, 128x, 256x, 384x, 512x, 768x,
1024x Fs Applications
256x~1024x Fs for 32kHz / 44.1kHz / 48kHz  TV audio
128x~512x Fs for 64kHz / 88.2kHz / 96kHz  Boom-box, CD and DVD receiver, docking system
64x~256x Fs for 128kHz /176.4kHz/192kHz  Powered speaker
 Supply voltage  Wireless audio
3.3V for digital circuit
10V~26V for loudspeaker driver Description
 Loudspeaker output power for Stereo@ 24V
AD82587D is a digital audio amplifier capable of
10W x 2ch into 8Ω @ 0.16% THD+N
driving a pair of 8Ω,20W or a single 4Ω,40W speaker,
both which operate with play music at a 24V supply
without external heat-sink or fan requirement.
 Loudspeaker output power for Mono@ 24V
20W x 1ch into 4Ω @ 0.17% THD+N 2
Using I C digital control interface, the user can control
AD82587D’s input format selection, mute and volume
control functions. AD82587D has many built-in
 Sounds processing including:
protection circuits to safeguard AD82587D from
Volume control (+24dB~-103dB, 0.125dB/step)
connection errors.
Dynamic range control
Power clipping
Channel mixing
User programmed noise gate with hysteresis window
DC-blocking high-pass filter
ORDERING INFORMATION
Product ID Package Packing code Packing / MPQ Comments
2.5K Units / Small Box

E-LQFP-48L
AD82587D-LG48NA Y (250 Units / Tray, 10 Trays / Green
(7x7 mm)
Small Box
62 Units / Tube
AD82587D-QG24NA T Green
E-TSSOP 24L 100 Tubes / Small Box
AD82587D-QG24NA R 2.5K Units Tape & Reel Green
Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Revision: 1.6 1/45
ESMT AD82587D
Pin Assignment (Top View)
VDDRB
VDDLB
GNDR
GNDL
N.C.
N.C.
N.C.
N.C.
RB
RA
LA
LB
48 AD82587D
47
46
45
44
43
42
41
40
39
38
37
PD 1 24 VDDLA
VDDLA 1 36 VDDRA
ERROR 2 23 NC
N.C. 2 35 N.C.
SDATA 3 22 LA
N.C. 3 34 N.C.
N.C. 4 33 N.C. LRCIN 4 21 GNDL
N.C. 5 32 N.C. SDA 5 20 LB
PLL 6
AD82587D 31 N.C. SCL 6 19 VDDLB
MCLK 7 30 N.C. RESET 7 18 VDDRB
CLK_OUT 8 E-LQFP-48L 29 N.C.
VSS 8 17 RB
DGND 9 28 N.C.
VDD GNDR
DVDD 10 DVDD
9 16
27
DEF 11 26 DGND SA0 10 15 RA
SDATA 12 25 SDA MCLK 11 14 NC
13
14
15
16
17
18
19
20
21
22
23
24
BCLK 12 13 VDDRA
E-TSSOP-24L
ERROR
RESET
PD
MONO
LRCIN
BCLK
N.C.
SCL
N.C.
SA0
SA1
N.C.
Pin Description
E-LQFP E-TSSOP
NAME TYPE DESCRIPTION CHARACTERISTICS
48L 24L
VDDLA 1 24 P Left channel supply A
N.C. 2 NA NC
N.C. 3 NA NC
N.C. 4 NA NC
N.C. 5 NA NC
PLL 6 NA I PLL enable, low active Schmitt trigger TTL input buffer
MCLK 7 11 I Master clock input Schmitt trigger TTL input buffer
CLK_OUT 8 NA O Clock output from PLL TTL output buffer
DGND 9 NA P Digital Ground
DVDD 10 NA P Digital Power
DEF 11 NA I Default volume setting Schmitt trigger TTL input buffer
SDATA 12 3 I Serial audio data input Schmitt trigger TTL input buffer
N.C. 13 NA NC
MONO 14 NA I MONO mode enable, high active Schmitt trigger TTL input buffer
LRCIN 15 4 I Left/Right clock input (Fs) Schmitt trigger TTL input buffer
BCLK 16 12 I Bit clock input (64Fs) Schmitt trigger TTL input buffer
PD 17 1 I Power down, low active Schmitt trigger TTL input buffer
ERROR 18 2 O Error status, low active Open-drain output

Revision: 1.6 2/45
ESMT AD82587D
RESET 19 7 I Reset, low active Schmitt trigger TTL input buffer
2
SA0 20 10 I I C select address 0 Schmitt trigger TTL input buffer
2
SA1 21 NA I I C select address 1 Schmitt trigger TTL input buffer
N.C. 22 NA NC
N.C. 23 NA NC
2
SCL 24 6 I I C serial clock input Schmitt trigger TTL input buffer
2
SDA 25 5 I/O I C bi-directional serial data Schmitt trigger TTL input buffer
DGND 26 8 P Digital Ground
DVDD 27 9 P Digital Power
N.C. 28 NA NC
N.C. 29 NA NC
N.C. 30 NA NC
N.C. 31 NA NC
N.C. 32 NA NC
N.C. 33 NA NC
N.C. 34 NA NC
N.C. 35 NA NC
VDDRA 36 13 P Right channel supply A
RA 37 15 O Right channel output A
N.C. 38 14 NC
GNDR 39 16 P Right channel ground
N.C. 40 NA NC
RB 41 17 O Right channel output B
VDDRB 42 18 P Right channel supply B
VDDLB 43 19 P Left channel supply B
LB 44 20 O Left channel output B
N.C. 45 NA NC
GNDL 46 21 P Left channel ground
N.C. 47 23 NC
LA 48 22 O Left channel output A

Revision: 1.6 3/45
ESMT AD82587D
Functional Block Diagram
Reset
MCLK
SDA
SCL
SA0
SA1
PD
PLL
I2C Control PLL Logic

Interface Interface ERROR
Internal
BCLK System
Input
SDATA Interface Clock
LRCIN
Audio Signal Loudspeaker L
SDM PCM to PWM
Processing Driver R
MONO
Available Package
Package Type Device No. θ ja(℃/W) Ψ jt(℃/W) θ jt(℃/W) Exposed Thermal Pad
E-LQFP-48L 22.9 1.05 34.9

AD82587D Yes (Note1)
E-TSSOP 24L 26.8 0.35 27.1
Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance,
soldering the thermal pad to the PCB’s ground plane is suggested.
Note 1.2: θ ja is measured on a room temperature (TA=25℃), natural convection environment test board, which
is constructed with a thermally efficient, 4-layers PCB (2S2P). The measurement is tested using the
JEDEC51-5 thermal measurement standard.
Note 1.3: θ jt represents the heat resistance for the heat flow between the chip and the package’s top surface.
Note 1.4: Ψ jt represents the heat resistance for the heat flow between the chip and the package’s top surface
center.
Absolute Maximum Ratings

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Symbol Parameter Min Max Units

DVDD Supply for Digital Circuit -0.3 3.6 V
VDDL/R Supply for Driver Stage -0.3 30 V
Vi Input Voltage -0.3 3.6 V
o
Tstg Storage Temperature -65 150 C
o
TJ Junction Operating Temperature 0 150 C

Revision: 1.6 4/45
ESMT AD82587D
Recommended Operating Conditions
Symbol Parameter Typ Units
DVDD Supply for Digital Circuit 3.15~3.45 V
VDDL/R Supply for Driver Stage 10~26 V
o
TJ Junction Operating Temperature 0~125 C
o
TA Ambient Operating Temperature 0~70 C
General Electrical Characteristics

o
Condition: TA=25 C (unless otherwise specified).
Symbol Parameter Condition Min Typ Max Units

IPD(HV) PVDD Supply Current during Power Down PVDD=24V 40 200 uA
IPD(LV) DVDD Supply Current during Power Down DVDD=3.3V 4 20 uA
o
Junction Temperature for Driver Shutdown 160 C
TSENSOR o
Temperature Hysteresis for Recovery from Shutdown 35 C
UVH Under Voltage Disabled (For DVDD) 2.8 V
UVL Under Voltage Enabled (For DVDD) 2.7 V
Static Drain-to-Source On-state Resistor, PMOS PVDD=24V, 260 m
Rds-on Id=500mA
Static Drain-to-Source On-state Resistor, NMOS 175 m
L(R) Channel Over-Current Protection (Note 2) PVDD=24V 5.2 A
ISC
Mono Channel Over-Circuit Protection (Note 2) PVDD=24V 10.4 A
VIH High-Level Input Voltage DVDD=3.3V 2.0 V
VIL Low-Level Input Voltage DVDD=3.3V 0.8 V
VOH High-Level Output Voltage DVDD=3.3V 2.4 V
VOL Low-Level Output Voltage DVDD=3.3V 0.4 V
CI Input Capacitance 6.4 pF
Note 2: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly
connected with external LC filters. Please refer to the application circuit example for recommended
LC filter configuration.
Marking Information
AD82587D ESMT
Line 1 : LOGO
AD82587D ESMT
Tracking Code AD82587D
Line 2 : Product no. Date Code Tracking Code
Line 3 : Tracking Code
PIN1 DOT PIN1 DOT
Line 4 : Date Code
E-LQFP 48L E-TSSOP-24L

Revision: 1.6 5/45
AD82587D
Logic
Publication Date: Jan. 2018

0 1
6/45
470F Pin
-
PD Power Down Normal
+
0.1F 0.1F 0.1F 0.1F DEF Default Mute Default Un-Mute

3.3V
24V MONO Stereo Mono
RB
RA
LA
LB
PLL Enable External
Revision: 1.6
VDDRB
GNDR
VDDLA
VDDRA
RB
GNDL
RA
LA
VDDLB
LB
PLL
MCLK
(Note 5) (Note 6) (Note 3) (Note 4)
CLK_OUT
LA
DGND 470pF BEA D 22H 100nF 1nF 10nF
0.1F ≧3A 3A
220nF
DVDD 10 10
470nF
DEF 10 10
220nF
Speaker
AD82587D BEA D 22H

470pF ≧3A 3A 100nF 1nF 10nF
LB
(Note 3)
SDATA 3.3V
DVDD
0.1F
DGND (Note 5) (Note 6) (Note 3) (Note 4)
Elite Semiconductor Memory Technology Inc.

Application Circuit Example for Stereo
3.3V
RA
ERROR 100nF 1nF 10nF
MONO
22H
LRCIN
470pF BEA D
Reset
BCLK
4.7K 4.7K ≧3A
SCL
3A
SA1
SA0
220nF
PD
SDA 10 10

470nF
3.3V 3.3V 10 10
220nF
Speaker
1M 1M BEA D 22H

470pF ≧3A 3A 100nF 1nF 10nF
1F 1F RB
(Note 3)
Note 3: When concerning about short-circuit protection or performance, it is suggested using
the choke with its IDC larger than 5A.
ESMT
Note 4: These capacitors should be placed as close to speaker jack as possible, and their
values should be determined according to EMI test results.
Note 5: The snubber circuit can be removed while the PVDD <=20V.
Note 6: The bead (option component) can be removed if the system EMI test result is good
enough.
AD82587D

Application Circuit Example for Stereo (Economic type, moderate EMI suppression)
7/45
Logic
470F Pin 0 1
-
PD Power Down Normal
+
0.1F 0.1F 0.1F 0.1F

DEF Default Mute Default Un-Mute
3.3V
24V
MONO Stereo Mono
LB
LA
RA
RB
Revision: 1.6
PLL Enable External
VDDRB
VDDLA
GNDR
VDDRA
RB
GNDL
VDDLB
LA
RA
LB
PLL
MCLK (Note 9) (Note 8)
CLK_OUT (Note 7)
LA
DGND 22H 1nF
470pF
0.1F 3A
DVDD 10
470nF
DEF 10
Speaker
AD82587D 22H

470pF 3A 1nF
LB
(Note 7)
SDATA 3.3V
DVDD
0.1F
(Note 9) (Note 8)

DGND (Note 7)
3.3V RA
ERROR
470pF 22H 1nF
MONO
LRCIN
Reset
BCLK
4.7K 4.7K 3A
SCL
SA0
SA1
PD 10
SDA
470nF
3.3V 3.3V 10
Speaker
1M 1M 22H

470pF 3A 1nF
RB
1F 1F
(Note 7)
ESMT
Note 9: The snubber circuit can be removed while the PVDD <=20V.
AD82587D

8/45
470F
Logic
- Pin 0 1
+
0.1F 0.1F 0.1F 0.1F PD Power Down Normal

3.3V
24V DEF Default Mute Default Un-Mute
Revision: 1.6
LB
LA
RA
RB
MONO Stereo Mono

VDDRB
RB
GNDL
GNDR
VDDLA
VDDRA
VDDLB
RA
LA
LB
PLL PLL Enable External

MCLK
CLK_OUT
DGND
0.1F
DVDD LA
470pF BEAD
≧3A (Note 11)
DEF (Note 10)
10
AD82587D 10H 100nF
1nF 10nF
10
BEAD 6A
470pF ≧3A 220nF
SDATA 3.3V LB 10
DVDD 470nF

0.1F RA
Application Circuit Example for Mono
10
Speaker
DGND 470pF BEAD 220nF

3.3V ≧3A
10 10H
100nF
ERROR
6A 1nF
MONO
10nF
LRCIN
Reset
BCLK
4.7K 4.7K
SCL
SA0
SA1
10
PD SDA BEAD (Note 10)
470pF ≧3A
3.3V 3.3V RB
1M 1M
3.3V
1F 1F
ESMT
ESMT AD82587D
Electrical Characteristics and Specifications for Loudspeaker
 Stereo output with 24V supply voltage
o
Condition: TA=25 C, DVDD=3.3V, VDDL=VDDR=24V, FS=48kHz, Load=8 with passive LC lowpass filter
(L=22μ H with RDC=0.12Ω , C=470nF); Input is 1kHz sinewave. Volume is 0dB unless otherwise specified.
Symbol Parameter Condition Input Level Min Typ Max Units

RMS Output Power (THD+N=0.21%) 20 W
PO
RMS Output Power (THD+N=0.18%) +8dB volume 15 W
(Note 13)
RMS Output Power (THD+N=0.16%) 10 W
THD+N Total Harmonic Distortion + Noise PO=7.5W 0.14 %
SNR Signal to Noise Ratio (Note 12) +8dB volume -9dB 97 dB
DR Dynamic Range (Note 12) +8dB volume -68dB 105 dB
VRIPPLE=1VRMS
PSRR Power Supply Rejection Ratio 77 dB
at 1kHz
Channel Separation (non-shield choke) PO=1W at 1kHz 70 dB
Note 12: Measured with A-weighting filter.
Note 13: Thermal dissipation is limited by package type and PCB design, the external heat-sink or system
cooling method should be adopted for RMS power output.
Total Harmonic Distortion + Noise vs. Output Power (Stereo)

20
10 24V, 8Ω
Stereo
5
2
THD+N (%)
1
0.5
10kHz
0.2
1kHz
0.1
20Hz
0.05
0.02
0.01
1m 2m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100
Output Power (W)

Revision: 1.6 9/45
ESMT AD82587D
Total Harmonic Distortion + Noise vs. Frequency (Stereo)
20
10 24V, 8Ω
5 Stereo
10W
5W
2 2.5W
1W
THD+N (%)
1
0.5W
0.5
0.2
0.1
0.05
0.02
0.01
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Cross-talk (Stereo)
+0
24V, 8Ω
-20 Stereo
PO=1W
Non-shield Choke
-40
Cross-talk (dBr)
-60
-80
-100
-120
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Frequency Response (Stereo)

+1 +1
+0.8 24V, 8Ω +0.8

Stereo
+0.6 PO=1W +0.6
+0.4 +0.4
+0.2 +0.2
dBr
+0 +0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)

Revision: 1.6 10/45
ESMT AD82587D
Efficiency (Stereo)
Efficiency vs. Output Power (Stereo)
100
90
80
12V
70
15V
Efficiency(%)
60
18V
50 24V
40
30
20
10
0
0 10 20 30 40 50 60 70
2CH Output Power(W)
Efficiency (Stereo) for PWM of Power Saving Mode
Efficiency vs. Output Power (Stereo)
100
90
80
70 Power saving mode enable
Efficiency(%)
Quaternary to Ternary
60 W/O power saving mode
switching level: 30
50
40
30
20
24V, 8Ω
10 Stereo
0
0 10 20 30 40 50 60 70
2CH Output Power(W)

Revision: 1.6 11/45
ESMT AD82587D
Electrical Characteristics and Specifications for Loudspeaker
 Mono output with 24V supply voltage
o
Condition: TA=25 C, DVDD=3.3V, VDDL=VDDR=24V, FS=48kHz, Load=4 with passive LC lowpass filter
(L=10μ H with RDC=27mΩ , C=470nF); Input is 1kHz sinewave. Volume is 0dB unless otherwise specified.
Symbol Parameter Condition Input Level Min Typ Max Units

RMS Output Power (THD=0.24%) +8dB volume 40 W
PO
(Note 13)
THD+N Total Harmonic Distortion + Noise Po=15W 0.15 %
SNR Signal to Noise Ratio(Note 12) +8dB volume -9dB 97 dB
DR Dynamic Range(Note 12) +8dB volume -68dB 105 dB
VRIPPLE=1VRMS at
PSRR Power Supply Rejection Ratio 77 dB
1kHz
Note 12: Measured with A-weighting filter.
Note 13: Thermal dissipation is limited by package type and application PCB design, the external heat-sink or
system cooling method should be adopted for maximum power output.
Total Harmonic Distortion + Noise vs. Output Power (Mono)

20
10 24V, 4Ω
5 Mono
2
THD+N (%)
1
0.5
10kHz
0.2
0.1 1kHz
20Hz
0.05
0.02
0.01
1m 2m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100
Output Power (W)

Revision: 1.6 12/45
ESMT AD82587D
Total Harmonic Distortion + Noise vs. Frequency (Mono)
20
10 24V, 4Ω
Mono
5
20W
2 10W
5W
THD+N (%)
1 2W
1W
0.5
0.2
0.1
0.05
0.02
0.01
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Frequency Response (Mono)

+1 +1
+0.8 24V, 4Ω +0.8

Mono
PO=1W
+0.6 +0.6
+0.4 +0.4
+0.2 +0.2
dBr
+0 +0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)

Revision: 1.6 13/45
ESMT AD82587D
Efficiency (Mono)
Efficiency vs. Output Power (Mono)
100
90
80
70 12V
15V
Efficiency(%)
60
18V
50 24V
40
30
20
10
0
0 10 20 30 40 50 60 70
Output Power(W)
Efficiency (Mono) for PWM of Power Saving Mode
Efficiency vs. Output Power (Mono)
100
90
80
70 Power saving mode enable
Quaternary to Ternary
Efficiency(%)
60 switching level: 30 W/O power saving mode

50
40
30
20 24V, 4Ω
10 Mono
0
0 10 20 30 40 50 60
Output Power(W)

Revision: 1.6 14/45
ESMT AD82587D
Interface Configuration
 I2S LRCIN Left Right
BCLK
SDATA MSB LSB MSB LSB
 Left-Alignment LRCIN Left Right
BCLK
 Right-Alignment LRCIN Left Right
BCLK
 System Clock Timing

t PERIOD
t LOW
MCLK t HIGH
t HIGH ≧ 40 . 4 ns , t LOW ≧ 40 . 4 ns , t PERIOD ≧ 80 .8 ns Default setting,when PLL is enable
t HIGH ≧ 10 . 1 ns , t LOW ≧ 10 . 1 ns , t PERIOD ≧ 20 .2 ns When PLL is disable
 Timing Relationship (Using I2S format as an example)
t LR
LRCIN Left Right

t BL t LB tBCH tBCL
BCLK
t BCC
SDATA MSB MSB
tDS tDH

Revision: 1.6 15/45
ESMT AD82587D
Symbol Parameter Min Typ Max Units
tLR LRCIN Period (1/FS) 10.41 31.25 s
tBL BCLK Rising Edge to LRCIN Edge 50 ns
tLB LRCIN Edge to BCLK Rising Edge 50 ns
tBCC BCLK Period (1/64FS) 162.76 488.3 ns
tBCH BCLK Pulse Width High 81.38 244 ns
tBCL BCLK Pulse Width Low 81.38 244 ns
tDS SDATA Set-Up Time 50 ns
tDH SDATA Hold Time 50 ns
 I2C Timing
tf tr tSU;DAT tf tHD;STA tr tBUF

tLOW
tHD;STA tSU;STA tSU;STO

tHD;DAT tHIGH P S
S Sr
Standard Mode Fast Mode

Parameter Symbol Unit
MIN. MAX. MIN. MAX.
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time for repeated START condition tHD,STA 4.0 --- 0.6 --- s
LOW period of the SCL clock tLOW 4.7 --- 1.3 --- s
HIGH period of the SCL clock tHIGH 4.0 --- 0.6 --- s
Setup time for repeated START condition tSU;STA 4.7 --- 0.6 --- s
2
Hold time for I C bus data tHD;DAT 0 3.45 0 0.9 s
Setup time for I2C bus data tSU;DAT 250 --- 100 --- ns
Rise time of both SDA and SDL signals tr --- 1000 20+0.1Cb 300 ns
Fall time of both SDA and SDL signals tf --- 300 20+0.1Cb 300 ns
Setup time for STOP condition tSU;STO 4.0 --- 0.6 --- s
Bus free time between STOP and the next
tBUF 4.7 --- 1.3 --- s
START condition
Capacitive load for each bus line Cb 400 400 pF
Noise margin at the LOW level for each
VnL 0.1VDD --- 0.1VDD --- V
connected device (including hysteresis)
Noise margin at the HIGH level for each
VnH 0.2VDD --- 0.2VDD --- V
connected device (including hysteresis)

Revision: 1.6 16/45
ESMT AD82587D
Operation Description
 Reset
When the RESET pin is lowered, AD82587D will clear the stored data and reset the register table to
th
default values. AD82587D will exit reset state at the 256 MCLK cycle after the RESET pin is raised to
high.
 Power down control

AD82587D has a built-in volume fade-in/fade-out design for PD/Mute function. The relative PD timing
diagrams for loudspeakers are shown below.
Volume Level Volume Level

PD enabled PD disabled PD enabled
+24 dB +24 dB PD disabled
Original level Original level
-103 dB -103 dB
time time
Fade out Mute Fade in Fade out Fade in

time state time time time
t arg et ( dB ) original ( dB )
(10 80
 10 80
) x512x(1/ 96K )
The volume level will be decreased to -∞dB in several LRCIN cycles. Once the fade-out procedure is
finished, AD82587D will turn off the power stages, clock signals (for digital circuits) and current (for analog
circuits). After PD pin is pulled low, AD82587D requires Tfade to finish the forementioned work before
entering power down state. Users can not program AD82587D during power down state. Also, all settings in
the registers will remain intact unless DVDD is removed.
If the PD signal is removed during the fade-out procedure (above, right figure), AD82587D will still execute
the fade-in procedure. In addition, AD82587D will establish the analog circuits’ bias current and send the
clock signals to digital circuits. Afterwards, AD82587D will return to its normal status.

Revision: 1.6 17/45
ESMT AD82587D
 Internal PLL ( PLL )
2
AD82587D has a built-in PLL with multiple MCLK/FS ratio, which is selected by I C control interface. If PLL
pin is pulled low, the built-in PLL is enabled; if PLL pin is pulled high, an external clock source for MCLK
less than 50MHz should be provided. The MCLK/FS ratio will be fixed at 1024x, 512x, or 256x with a sample
frequency of 48kHz, 96kHz, or 192kHz respectively.
2
When using AD82587D without I C control interface, the operation is as follows.
PLL pin is set to high:

Internal PLL is bypassed (Disable). The following master clock frequency is inputted into a MCLK pin by
the sampling frequency. When the following master clock frequency cannot be inputted, PLL pin is set
low. A career clock frequency is the frequency divided by 128 of master clock.
Fs MCLK frequency PWM career frequency

48kHz 49.152MHz 384kHz
44.1kHz 45.158MHz 352.8kHz
32kHz 32.768MHz 256kHz
PLL pin is set to low:

Internal PLL is enabled. The master clock inputted into the MCLK pin becomes the frequency of quad
edge evaluation. A career clock frequency is the frequency divided by 32 of master clock.
Multiple edge
MCLK/FS Setting PWM Career
Fs MCLK Frequency evaluation for
Ratio for PLL Frequency
master clock
48kHz 256x 12.288MHz 4x 384kHz
44.1kHz 256x 11.289MHz 4x 352.8kHz
32kHz 256x 8.192MHz 4x 256kHz
 Anti-pop design
AD82587D will generate appropriate control signals to suppress pop sounds during initial power on/off,
power down/up, mute, and volume level changes.
 Default volume (DEF)

The volume of AD82587D is +1.625dB when DEF pin is high, and the volume is muted when DEF pin low.
When using AD82587D without I2C control interface, user should set the pin high. The user can change the
values of the register table setting for volume control. For detailed information, refer to the register table
section.

Revision: 1.6 18/45
ESMT AD82587D
 Self-protection circuits
AD82587D has built-in protection circuits including thermal, short-circuit and under-voltage detection circuits.
(i) When the internal junction temperature is higher than 160℃, power stages will be turned off and
AD82587D will return to normal operation once the temperature drops to 125℃. The temperature values
may vary around 10%.
(ii) The short-circuit protection circuit protects the output stage when the wires connected to loudspeakers
are shorted to each other or GND/VDD. For normal 24V operations, the current flowing through the
power stage will be less than 5Afor stereo configuration or less than 10A for mono configuration.
Otherwise, the short-circuit detectors may pull the ERROR pin to DGND, disabling the output stages.
When the over-temperature or short-circuit condition occurs, the open-drain ERROR pin will be pulled
low and latched into ERROR state. Once the over-temperature or short-circuit condition is removed,
AD82587D will exit ERROR state when one of the following conditions is met: (1) RESET pin is pulled
2
low, (2) PD pin is pulled low, (3) Master mute is enabled through the I C interface.
(iii) Once the DVDD voltage is lower than 2.7V, AD82587D will turn off its loudspeaker power stages and
cease the operation of digital processing circuits. When DVDD becomes larger than 2.8V, AD82587D
will return to normal operation.
(iv) If the master clock inputted into MCLK pin stops during the period for 500 ns or more, AD82587D detect
the stop of MCK. In this state, amplifier outputs are forced to Weak Low. If master clock is inputted
normally again, ERROR pin is set to low. AD82587D won’t leave ERROR state until one of the
following conditions: (1) Reset pin is pulled low, (2) PD pin is pulled low, (3) Programming master mute
2
via I C interface.
PD pin is set to low, when stop the clock inputted into MCLK, BCLK, and LRCIN during operation.
(v) If it will be in the state where PVDD power supply is OFF and DVDD power supply is ON, ERROR pin
is set to Low.

Revision: 1.6 19/45
ESMT AD82587D
 Power on sequence
Hereunder is AD82587D’s power on sequence. Please note that we suggested users set DEF pin at low
2
state initially, and than give a de-mute command via I C when the whole system is stable.
Normal Normal
Power - On PD = L
Operation Operation
PVDD
t1 t8
DVDD
t2 t3 t12 t3
MCLK
BCLK
LRCIN
t4 t5 t13 t5
RESET
t6 t7
PD
t9 t10
I2C active
I2 C De-Mute
t 11 t 14 t 15
LA , LB ,
RA , RB
Symbol Condition Min Max Units

t1 0 - msec
t2 0 - msec
t3 10 - msec
t4 0 - msec
t5 10 - msec
t6 10 - msec
t7 0 - msec
t8 200 - msec
t9 20 - msec
t10 DEF=L - 1 msec
t11 DEF=H - 1 msec
t12 25 - msec
t13 25 - msec
t14 - 22 msec
t15 DEF= L or H - 1 msec

Revision: 1.6 20/45
ESMT AD82587D
 Power off sequence
Hereunder is AD82587D’s power off sequence.
PVDD
DVDD
t4 t5
MCLK
BCLK, t3
LRCIN
t2
/RESET
t1
/PD
Don’t care
I2C
LA, LB,
RA, RB
Symbol Condition Min Max Units

t1 35 - msec
t2 0.1 - msec
t3 0 - msec
t4 1 - msec
t5 1 - msec

Revision: 1.6 21/45
ESMT AD82587D
I2C-Bus Transfer Protocol
 Introduction
2
AD82587D employs I C-bus transfer protocol. Two wires, serial data and serial clock carry information
between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can
operate as either a transmitter or a receiver. The master device initiates a data transfer and provides the
2
serial clock on the bus. AD82587D is always an I C slave device.
 Protocol
 START and STOP condition
START is identified by a high to low transition of the SDA signal.. A START condition must precede
any command for data transfer. A STOP is identified by a low to high transition of the SDA signal. A
STOP condition terminates communication between AD82587D and the master device on the bus. In
both START and STOP, the SCL is stable in the high state.
 Data validity
The SDA signal must be stable during the high period of the clock. The high or low change of SDA only
occurs when SCL signal is low. AD82587D samples the SDA signal at the rising edge of SCL signal.
 Device addressing
The master generates 7-bit address to recognize slave devices. When AD82587D receives 7-bit
address matched with 0110x0y for E-LQFP 48L package (where x and y can be selected by external
SA0 and SA1 pins, respectively) and address matched with 0110x00 for E-TSSOP 24L package
th th
(where x can be selected by external SA0 pin), AD82587D will acknowledge at the 9 bit (the 8 bit is
for R/W bit). The bytes following the device identification address are for AD82587D internal
sub-addresses.
 Data transferring
Each byte of SDA signaling must consist of 8 consecutive bits, and the byte is followed by an
acknowledge bit. Data is transferred with MSB first, as shown in the figure below. In both write and
read operations, AD82587D supports both single-byte and multi-byte transfers. Refer to the figure
below for detailed data-transferring protocol.
START ACK ACK ACK STOP
Byte DEV_ADDR SUB_ADDR DATAIN
Write
R/W
START ACK ACK ACK ACK STOP
Multi-Byte DEV_ADDR SUB_ADDR DATAIN DATAIN
Write
R/W
NO
Random START ACK ACK ACK ACK STOP
Address DEV_ADDR SUB_ADDR DEV_ADDR DATAIN
Read
R/W START R/W
NO
Sequential START ACK ACK ACK ACK ACK ACK STOP
Random DEV_ADDR SUB_ADDR DEV_ADDR DATAIN DATAIN
Read
R/W START R/W

Revision: 1.6 22/45
ESMT AD82587D
Register Table
The audio signal processing data flow is shown as the following figure. Users can control these function by
programming appropriate setting to register table. In this section, the register table is summarized first. The
definition of each register follows in the next section.
DTC
control
L
Volume Power Power Interpolation
ASRC HPF SDM PWM
BCLK control Limt Clipping filter
LRCIN
L/R Ex- Power
SDATA DAII Stage
change Mixing
R
Volume Power Power Interpolation
ASRC HPF SDM PWM
control Limt Clipping filter
Audio Signal Processing
DTC
control
Address Register B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
0X00 SCTL1 IF[2] IF[1] IF[0] LREXC PWML_X PWMRX PwmMode NGE
0X01 SCTL 2 Reserved FS[1] FS[0] PMF[3] PMF[2] PMF[1] PMF[0]
0X02 SCTL 3 EN_CLKO HPB LV_UVSEL SW_RSTB MUTE CM1 CM2 CompSDMEn
0X03 MVOL MV[7] MV[6] MV[5] MV[4] MV[3] MV[2] MV[1] MV[0]
0X04 C1VOL C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0]
0X05 C2VOL C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0]
0X06 HVUV DIS_HVUV Reserved HVUVSEL[3] HVUVSEL[2] HVUVSEL[1] HVUVSEL[0]
0X07 SCTL 4 C1MX_EN C2MX_EN PC_EN DRC_EN MONO_EN Reserved
0X08 LAR LA[3] LA[2] LA[1] LA[0] LR[3] LR[2] LR[1] LR[0]
0X09 QT_SW_LEVEL Reserved QTS[4] QTS[3] QTS[2] QTS[1] QTS[0]
0X0A Reserved
0X0B OC SET Reserved
0X0C STATUS Reserved
0X0D ACFG Reserved
0X0E TM_CTRL Reserved
0X0F PWM_CTRL Reserved
0X10 ATT Reserved ATT[4] ATT[3] ATT[2] ATT[1] ATT[0]
0X11 ATM ATM[7] ATM[6] ATM[5] ATM[4] ATM[3] ATM[2] ATM[1] ATM[0]
0X12 ATB ATB[7] ATB[6] ATB[5] ATB [4] ATB [3] ATB [2] ATB [1] ATB [0]

Revision: 1.6 23/45
ESMT AD82587D
0X13 PCT Reserved PCT[4] PCT[3] PCT[2] PCT[1] PCT[0]
0X14 PCM PCM[7] PCM[6] PCM[5] PCM[4] PCM[3] PCM[2] PCM[1] PCM[0]
0X15 PCB PCB[7] PCB[6] PCB[5] PCB [4] PCB [3] PCB [2] PCB [1] PCB [0]
DIS_ZD
0X16 NGG Reserved Reserved NG_GAIN[1] NG_GAIN[0]
_FADE
0X17 VFT MV_FT[1] MV_FT[0] C1V_FT[1] C1V_FT[0] C2V_FT[1] C2V_FT[0] Reserved
0X18 DTC DTC_EN DTC_TH[1] DTC_TH[0] DTC_RATE[1] DTC_RATE[0] Reserved
0X19 Reserved
0X1A NGALT NGALT[7] NGALT[6] NGALT[5] NGALT[4] NGALT[3] NGALT[2] NGALT[1] NGALT[0]
0X1B NGALM NGALM[7] NGALM[6] NGALM[5] NGALM[4] NGALM[3] NGALM[2] NGALM[1] NGALM[0]
0X1C NGALB NGALB[7] NGALB [6] NGALB [5] NGALB [4] NGALB [3] NGALB [2] NGALB [1] NGALB [0]
0X1D NGRLT NGRLT[7] NGRLT[6] NGRLT[5] NGRLT[4] NGRLT[3] NGRLT[2] NGRLT[1] NGRLT[0]
0X1E NGRLM NGRLM[7] NGRLM[6] NGRLM[5] NGRLM[4] NGRLM[3] NGRLM[2] NGRLM[1] NGRLM[0]
0X1F NGRLB NGRLB[7] NGRLB [6] NGRLB[5] NGRLB[4] NGRLB [3] NGRLB [2] NGRLB [1] NGRLB [0]
0X20 DRC_ECT DRC_ECT[7] DRC_ECT[6] DRC_ECT[5] DRC_ECT[4] DRC_ECT[3] DRC_ECT[2] DRC_ECT[1] DRC_ECT[0]
0X21 DRC_ECB DRC_ECB[7] DRC_ECB[6] DRC_ECB[5] DRC_ECB[4] DRC_ECB[3] DRC_ECB[2] DRC_ECB[1] DRC_ECB[0]
0X22 RTT Reserved RTT[4] RTT[3] RTT[2] RTT[1] RTT[0]
0X23 RTM RTM[7] RTM[6] RTM[5] RTM[4] RTM[3] RTM[2] RTM[1] RTM[0]
0X24 RTB RTB[7] RTB[6] RTB[5] RTB [4] RTB [3] RTB [2] RTB [1] RTB [0]

Revision: 1.6 24/45
ESMT AD82587D
Detail Description for Register
In this section, please note that the highlighted columns are the default value of these tables. If no highlighted, it
is because the default setting of this bit is determined by external pin.
 Address 0X00 : State control 1

2
AD82587D support multiple serial data input formats including I S, Left-alignment and Right-alignment.
These formats is chosen by user via bit7~bit5 of address 0.
BIT NAME DESCRIPTION VALUE FUNCTION

2
000 I S 16-24 bits
001 Left-alignment 16-24 bits
010 Right-alignment 16 bits
B[7:5] IF[2:0] Input Format 011 Right-alignment 18 bits
other Reversed
Left/Right (L/R) 0 No exchanged
B[4] LREXC
Channel Exchanged 1 L/R exchanged
0 No exchange
B[3] PWML_X LA/LB Exchange
1 Exchange
0 No exchange
B[2] PWMR_X RA/RB Exchange
1 Exchange
0 Quarternary+Ternary
B[1] PwmMode PWM Mmode
1 Quarternary
0 Disable
B[0] NGE Noise Gate Enable
1 Enable

Revision: 1.6 25/45
ESMT AD82587D
AD82587D has built-in PLL which can be bypassed by pull high the PLL pin. When PLL is enabled, multiple
MCLK/FS ratio is supported. Detail setting is shown as the above table.

B[7:6] X Reserved
00 32/44.1/48kHz
01 32/44.1/48kHz
B[5:4] FS Sampling Frequency
10 64/88.2/96kHz
11 128/176.4/192kHz
Multiple MCLK/FS ratio setting table
BIT NAME DESCRIPTION VALUE B[5:4]=00/01 B[5:4]=10 B[5:4]=11

Reset Reset Reset
0001 Default Default Default
Multiple
(256x) (128x) (64x)
B[3:0] PMF[3:0] MCLK/FS
0010 512x 256x 128x
Ratio Setting
0011 768x 384x 192x
0100 1024x 512x 256x

Revision: 1.6 26/45
ESMT AD82587D
To prevent the DC current from damaging the speaker, a high pass filter (3dB frequency = 5Hz ) is built into
the AD82587D. It can be enabled or disabled by bit 6 of address 2.
AD82587D has a mute function which includes master mute and individual channel mute modes. When the
master mute mode is enabled, both left and right processing channels are muted. On the other hand, either
channel can be muted by using the channel mute mode. When the mute function is enabled or disabled, the
fade-out or fade-in process will be initiated.
The default settings of B[3:1] are determined by DEF pin. When DEF pin is pulled low or high, the default
setting is muted or unmated.

EN_CLK_ 0 Disabled
B[7] PLL Clock Output
OUT 1 Enabled
DC Blocking HPF 0 Enable
B[6] HPB
Bypass 1 Disabled
LV Under Voltage 0 2.7V
B[5] LV_UVSEL
Selection 1 3.0V
0 Reset
B[4] SW_RSTB Software reset
1 Normal operating
0 Un-Mute (DEF=1)
B[3] MUTE Master Mute
1 Mute (DEF=0)
0 Un-Mute (DEF=1)
B[2] CM1 Channel 1 Mute
1 Mute (DEF=0)
0 Un-Mute (DEF=1)
B[1] CM2 Channel 2 Mute
1 Mute (DEF=0)
Compensate SDM 0 Disable
B[0] CompSDMEn
Frequency Response 1 Enable

Revision: 1.6 27/45
ESMT AD82587D
 Address 0X03 : Master volume
AD82587D supports both master-volume and channel-volume control for the stereo processing channels.
Both master volume control (Address 0X03) and channel volume (Address 0X04 and 0X05 ) settings range
from +12dB ~ -102dB. Given master volume level, say, Level A (in dB unit) and channel volume level, say
Level B (in dB unit), the total volume equals to Level A plus with Level B and its range is from +24dB ~
-102dB, i.e., -103dB ≦ Total Volume ( Level A + Level B ) ≦ +24dB.

00000000 +12dB
00000001 +11.5dB
00000010 +11dB
︰︰
00010111 0.5dB
00011000 0dB
B[7:0] MV[7:0] Master Volume
00011001 -0.5dB
︰︰
11100110 -103dB
11100101 -∞dB
︰︰
1111111 -∞dB
 Address 0X04 : Channel1 volume

00000000 +12dB
00000001 +11.5dB
︰︰
00010100 2dB
︰︰
00011000 0dB
B[7:0] C1V[7:0] Channel 1 Volume
00011001 -0.5dB
︰︰
11100110 -103dB
11100101 -∞dB
︰︰
1111111 -∞dB

Revision: 1.6 28/45
ESMT AD82587D
 Address 0X05 : Channel2 volume

00000000 +12dB
00000001 +11.5dB
︰︰
00010100 2dB
︰︰
00011000 0dB
B[7:0] C2V[7:0] Channel 2 Volume
00011001 -0.5dB
︰︰
11100110 -103dB
11100101 -∞dB
︰︰
1111111 -∞dB
 Address 0X06 : Under voltage selection for high voltage supply

AD82587D provides HV under voltage detection which can be enable or disable via bit 7. The under-voltage
detection level is programmable via bit3~ bit0. Once the output stage voltage drops below the preset value
(see table), AD82587D will fade out audio signals to turn off the speaker.

Disable HV Under 0 Enable
B[7] Dis_HVUV
Voltage Circuit 1 Disable
B[6:4] X Reserved
Other 9.7V
1100 19.5V
HV Under Voltage 0100 15.5V
B[3:0] HVUVSEL[3:0]
Selection (Active) 0011 13.2V
0001 9.7V
0000 8.2V
Note: under voltage range has +/- 10% max variation due to process window.

Revision: 1.6 29/45
ESMT AD82587D
AD82587D provides channel mix, power clipping, and dynamic range control (DRC) function. These
functions can be enable or not as the following table.

Channel1 Mixing 0 Disable(MONO=0)
B[7] C1MX_EN
Enable 1 Enable (MONO=1)
Channel2 Mixing 0 Disable(MONO=0)
B[6] C2MX_EN
Enable 1 Enable(MONO=1)
Power Clipping 0 Disable
B[5] PC_EN
Enable 1 Enable
0 Disable
B[4] DRC_EN DRC Enable
1 Enable
MONO or Stereo 0 Stereo
B[3] MONO_EN
Configure 1 MONO
B[2:0] X Reserved
AD82587D also provides MONO configuration via register bit 3 of address 0X07. The output configuration
(please refer to the page 8, Mono application circuit) shall be right connected before Mono configuration
enable. That’s possible to damage chips due to channel shoot-through if the wrong output configuration is
connected.
Normal Normal
Power - On PD = L
Operation Operation
PVDD
DVDD
MCLK
BCLK
LRCIN
RESET
PD
I2C active I2C active

I2 C Mono Configuration De-Mute
LA , LB ,
RA , RB

Revision: 1.6 30/45
ESMT AD82587D
 Address 0X08 : Attack rate and Release rate for Dynamic Range Control (DRC)
The attack/release rates of AD82587D are defined as following table,

0000 3 dB/ms
0001 2.667 dB/ms
0010 2.182 dB/ms
0011 1.846 dB/ms
0100 1.333 dB/ms
0101 0.889 dB/ms
0110 0.4528 dB/ms
0111 0.2264 dB/ms
B[7:5] LA[3:0] DRC Attack Rate
1000 0.15 dB/ms
1001 0.1121 dB/ms
1010 0.0902 dB/ms
1011 0.0752 dB/ms
1100 0.0645 dB/ms
1101 0.0563 dB/ms
1110 0.0501 dB/ms
1111 0.0451 dB/ms
0000 0.5106 dB/ms
0001 0.1371 dB/ms
0010 0.0743 dB/ms
0011 0.0499 dB/ms
0100 0.0360 dB/ms
0101 0.0299 dB/ms
0110 0.0264 dB/ms
0111 0.0208 dB/ms
B[3:0] LR[3:0] DRC Release Rate
1000 0.0198 dB/ms
1001 0.0172 dB/ms
1010 0.0147 dB/ms
1011 0.0137 dB/ms
1100 0.0134 dB/ms
1101 0.0117 dB/ms
1110 0.0112 dB/ms
1111 0.0104 dB/ms

Revision: 1.6 31/45
ESMT AD82587D
 Address 0X09 : Power saving mode switching level
If the PWM exceeds the programmed switching power level (default 30*40ns), the modulation algorithm will
change from quaternary to ternary modulation. Ternary modulation has less switching loss, resulting in
higher power efficiency during larger power output operations. If the PWM drops below the programmed
switching power level, the modulation algorithm will change back to quaternary modulation.

B[7:5] X Reserved
11111 62
11110 60
︰︰
︰︰
Quaternary and 10000 32
B[4:0] QTS[4:0] Ternary Switching 01111 30
Level 01110 28
01101 26
︰︰
00001 4
00000 4
Total Harmonic Distortion + Noise v.s. Output Power

2
Quaternary 24V, 8Ω
Q+T level 20
1
Q+T level 30
0.7 Q+T level 40
0.5 Q+T level 46
% 0.3
0.2
0.08
0.06
0.04
2 3 4 5 6 7 8 9 10 20
W
Sweep Trace Color Line Style Thick Data Axis Comment
1 1 Red Solid 2 Anlr.THD+N Ratio Left Q

2 1 Blue Solid 3 Anlr.THD+N Ratio Left Q+T level 30
3 1 Magenta Solid 3 Anlr.THD+N Ratio Left Q+T level 40
4 1 Green Solid 3 Anlr.THD+N Ratio Left Q+T level 20
5 1 Cyan Solid 3 Anlr.THD+N Ratio Left Q+T level 46

Revision: 1.6 32/45
ESMT AD82587D
 Address 0X10 : Top 5 bits of attack threshold for Dynamic Range Control (DRC)
The AD82587D provides dynamic range control function. When the input RMS exceeds the programmable
attack threshold value, the output power will be limited by this threshold power level via gradual gain
reduction. Attack threshold is defined by 21-bit representation composed of registers controlled by I2C. The
device addresses of DRC attack threshold are 0X10, 0X11, and 0X12.

B[7:5] X Reserved
Top 5 Bits of Attack X User programmed
B[4:0] ATT[4:0]
Threshold 01000 0dB
 Address 0X11 : Middle 8 bits of attack threshold

Middle 8 Bits of Attack X User programmed
B[7:0] ATM[7:0]
Threshold 00000000 0dB
 Address 0X12 : Bottom 8 bits of attack threshold

Bottom 8 bits of attack X User programmed
B[7:0] ATB[7:0]
threshold 00000000 0dB

Revision: 1.6 33/45
ESMT AD82587D
 Address 0X13 : Top 8 bits of power clipping
The AD82587D provides power clipping function to avoid excessive signal that may destroy loud speaker.
The power clipping level is defined by 21-bit representation composed of registers controlled by I2C. The
device addresses of power clipping threshold are 0X13, 0X14, and 0X15.

B[7:5] X Reserved
Top 5 Bits of Power X User programmed
B[4:0] PCT[4:0]
Clipping Level 01000 0dB
 Address 0X14 : Middle 8 bits of power clipping

Middle 8 Bits of Power X User programmed
B[7:0] PCM[7:0]
 Address 0X15 : Bottom 8 bits of power clipping level

Bottom 8 Bits of Power X User programmed
B[7:0] PCB[7:0]
The following table shows the power clipping level’s numerical representation.
Sample calculation for power clipping

Max Hex
dB Linear Decimal
amplitude (2.19 format)
PVDD 0 1 524288 80000
PVDD*0.707 -3 0.707 370727 5A827
PVDD*0.5 -6 0.5 262144 40000
(x/20)
PVDD*L x L=10 D=524288xL H=dec2hex(D)

Revision: 1.6 34/45
ESMT AD82587D
 Address 0X16 : Noise gate gain control
AD82587D provide noise gate function if receiving 2048 signal sample points less than noise gate attack
level. User can change noise gate gain via bit1~ bit0. When noise gate function occurs, input signal will
multiply noise gate gain (x1/8, x1/4 x1/2, x0). User can select fade out or not via bit 4.

B[7:5] X Reserved
Disable Noise Gate 0 Fade
B[4] DIS_NG_FADE
Fade 1 No fade
B[3:2] X Reserved
00 x1/8
Noise Gate 01 x1/4
B[1:0] NG_GAIN
Detection Gain 10 x1/2
11 Mute
 Address 0X17 : Volume fine tune

AD82587D supports both master-volume fine tune and channel-volume control fine tune modes. Both
volume control settings range from 0dB ~ -0.375dB and 0.125dB per step. Note that the master volume fine
tune is added to the individual channel volume fine tune as the total volume fine tune.

00 0dB
Master Volume Fine 01 -0.125dB
B[7:6] MV_FT
Tune 10 -0.25dB
11 -0.375dB
00 0dB
Channel 1 Volume Fine 01 -0.125dB
B[5:4] C1V_FT
Tune 10 -0.25dB
11 -0.375dB
00 0dB
Channel 2 Volume Fine 01 -0.125dB
B[3:2] C2V_FT
Tune 10 -0.25dB
11 -0.375dB
B[1:0] X Reserved

Revision: 1.6 35/45
ESMT AD82587D
 Address 0X18 : Dynamic Temperature Control (DTC)
AD82587D supports dynamic temperature control. The table describes the setting of DTC.

0 Disable
B[7] DTC_EN DTC Enable
1 Enable
o
00 110 C
o
01 120 C
B[6:5] DTC_TH DTC Threshold o
10 130 C
o
11 140 C
00 1dB/sec
DTC Attack and 01 0.5dB/sec
B[4:3] DTC_RATE
Release Rate 10 0.33dB/sec
11 0.25dB/sec
B[2:0] X Reserved
o
Release threshold is always 10 C smaller than attack threshold.
For example:
o o
DTC threshold (attack threshold) =130 C, the release threshold = 120 C.
o o
DTC threshold (attack threshold) =120 C, the release threshold = 110 C.
o
If junction temperature (Tj) exceeds 130 C, amplifier gain will be lowered to timing of 1dB/sec. If amplifier
o o
gain falls and junction temperature (Tj) turns into less than 130 C and larger than 120 C, the gain will not
o
increase or decrease. If amplifier gain falls and junction temperature (Tj) turns into less than 120 C,
amplifier gain will be raised to timing of 1dB/sec.

Revision: 1.6 36/45
ESMT AD82587D
 Address 0X1A : Top 8 bits of noise gate attack level
When both left and right signals have 2048 consecutive sample points less than the programmable noise
gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8, x1/4, x1/2, or zero if
the noise gate function is enabled. Noise gate attack level is defined by 24-bit representation composed of
registers controlled by I2C. The device addresses of noise gate attack level are 0X1A, 0X1B, and 0X1C
Top 8 Bits of Noise X User programmed

B[7:0] NGALT[7:0]
Gate Attack Level 00000000 -110dB
 Address 0X1B : Middle 8 bits of noise gate attack level

Middle 8 Bits of Noise X User programmed
B[7:0] NGALM[7:0]
 Address 0X1C : Bottom 8 bits of noise gate attack level

Bottom 8 Bits of Noise X User programmed
B[7:0] NGALB[7:0]

Revision: 1.6 37/45
ESMT AD82587D
 Address 0X1D : Top 8 bits of noise gate release level
After entering the noise gating status, the noise gain will be removed whenever AD82587D receives any
input signal that is more than the noise gate release level. Noise gate release level is defined by 24-bit
representation composed of registers controlled by I2C. The device addresses of noise gate release level
are 0X1D, 0X1E, and 0X1F.

Top 8 Bits of Noise X User programmed
B[7:0] NGRLT[7:0]
Gate Release Level 00000000 -100dB
 Address 0X1E : Middle 8 bits of noise gate release level

Middle 8 Bits of Noise X User programmed
B[7:0] NGRLM[7:0]
 Address 0X1F : Bottom 8 bits of noise gate release level

Bottom 8 Bits of Noise X User programmed
B[7:0] NGRLB[7:0]
The following table shows the noise gate attack and release threshold level’s numerical representation.
Sample calculation for noise gate attack and release level

Input amplitude Hex
Linear Decimal
(dB) (1.23 format)
0 1 8388607 7FFFFF
-5
-100 10 83 53
-5.5
-110 10 26 1A
(x/20)
X L=10 D=8388607xL H=dec2hex(D)

Revision: 1.6 38/45
ESMT AD82587D
 Address 0X20 : Top 8 bits of DRC energy coefficient

Top 8 Bits of DRC X User programmed
B[7:0] DRC_ECT [7:0]
Energy Coefficient 00000000 1/256
 Address 0X21 : Bottom 8 bits of DRC energy coefficient

DRC_ECB Bottom 8 Bits of DRC X User programmed
B[7:0]
[7:0] Energy Coefficient 00010000 1/256
DRC_EC
x2 [n] xrms[n]
Z-1
1-DRC_EC
The above figure illustrates the digital processing of calculating RMS signal power. In this processing, a DRC
energy coefficient is required, which can be programmed for different frequency range. Energy coefficient is
defined by 16-bit representation composed of registers controlled by I2C. The device addresses of DRC energy
coefficient are 0X20, and 0X21. The following table shows the DRC energy coefficient numerical representation.
Sample calculation for DRC energy coefficient

DRC energy Hex
dB Linear Decimal
coefficient (1.12 format)
1 0 1 4095 FFF
1/256 -48.2 1/256 16 10
1/1024 -60.2 1/1024 4 4
(x/20)
L x L=10 D=4095xL H=dec2hex(D)

Revision: 1.6 39/45
ESMT AD82587D
 Address 0X22 : Top 8 bits of release threshold for Dynamic Range Control (DRC)
After AD82587D has reached the attack threshold, its output power will be limited to that level. The output
power level will be gradually adjusted to the programmable release threshold level. Release threshold is
defined by 21-bit representation composed of registers controlled by I2C. The device addresses of release
threshold are 0X22, 0X23, and 0X24.

B[7:5] X Reserved
Top 5 Bits of X User programmed
B[4:0] RTT[4:0]
Release Threshold 00000010 -6dB
 Address 0X23 : Middle 8 bits of release threshold

Middle 8 Bits of X User programmed
B[7:0] RTM[7:0]
 Address 0X24 : Bottom 8 bits of release threshold

Bottom 8 Bits of X User programmed
B[7:0] RTB[7:0]
The following table shows the attack and release threshold’s numerical representation.
Sample calculation for attack and release threshold

Hex
Power dB Linear Decimal
(2.19 format)
(PVDD^2)/R 0 1 524288 80000
(PVDD^2)/2R -3 0.5 262144 40000
(PVDD^2)/4R -6 0.25 131072 20000
(x/10)
((PVDD^2)/R)*L x L=10 D=524288xL H=dec2hex(D)

Revision: 1.6 40/45
ESMT AD82587D
To best illustrate the dynamic range control function, please refer to the following figure.
Attack threshold
Release threshold
INPUT
Release threshold
Attack threshold
Δ gain2
GAIN
Δ gain1
Attack rate=Δ gain1/Δt1
Δ t1 Δ t2 Release rate=Δ
gain2/Δt2
Touch attack
threshold Under release
threshold
Attack threshold
Release threshold
OUTPUT
Release threshold
Attack threshold

Revision: 1.6 41/45
ESMT AD82587D
Package Dimensions
 E-LQFP 48L (7x7mm)
D1
D
48 37 37 48
1 36 36 D2 1
E2 DETAIL A
E E1
12 25 25 12
13 24 24 13
c
TOP VIEW BOTTOM VIEW
A1
b e L
SIDE VIEW DETAIL A
Dimension in mm Exposed pad

Symbol
Min Max Dimension in mm
A -- 1.60 Min Max
A1 0.05 0.15 D2 4.31 5.21
b 0.17 0.27 E2 4.31 5.21
c 0.09 0.20
D 6.90 7.10
D1 8.90 9.10
E 6.90 7.10
E1 8.90 9.10
e 0.50 BSC
L 0.45 0.75

Revision: 1.6 42/45
ESMT AD82587D
Package Dimensions
 E-TSSOP 24L
24 13
D2
E2 E E1 DETAIL A
PIN#1
MARK 1 12
c
TOP VIEW
D
A
A1
b e
L
SIDE VIEW
Dimension in mm Exposed pad

Symbol
Min Max Dimension in mm
A 1.00 1.20 D2 3.70 4.62
A1 0.00 0.15 E2 2.20 2.85
b 0.19 0.30
c 0.09 0.20
D 7.70 7.90
E 4.30 4.50
E1 6.30 6.50
e 0.65 BSC
L 0.45 0.75

Revision: 1.6 43/45
ESMT AD82587D
Revision History
Revision Date Description

0.1 2012.08.27 Original.
1) Update address 0X02, register table B[4] content.
2) Improved OC protection level on this version.
0.2 2013.01.07
3) Updated package thermal data2.
4) Added Power-OFF sequence into this datasheet.
1) Fade-out and fade-in time formula revised.
0.3 2013.02.08 2) Added DTC explanation at address 0X18.
3) Showed Ψ jt values to replace of Ψ jb.
1) Modified the typical value of ISC in General Electrical

0.4 2013.04.26 Characteristics.
2) Modified color for curve and legend.
1) Removed the letters of “Preliminary”
1.0 2014.05.26 2) Added note6 to Application Circuit Example for Stereo.
3) Modified the description of Device addressing.
Updated MONO configuration description via register bit of
1.1 2014.12.17
address 0X07.
1.2 2015.02.03 Add E-TSSOP 24L reel information
1.3 2016.03.08 Added Class-D HVUV range information into.
1.4 2016.06.30 Modify order information
1.5 2017.09.21 Modify timing of power on sequence.
1.6 2018.01.26 Modify PLL table.

Revision: 1.6 44/45
ESMT AD82587D
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by

any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the

time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples

for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express, implied
or otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.

Revision: 1.6 45/45

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ESMT AD82587D

2X20W Stereo / 1X40W Mono Digital Audio Amplifier

Product ID Package Packing code Packing / MPQ Comments

2.5K Units / Small Box

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

I2C Control PLL Logic

E-LQFP-48L 22.9 1.05 34.9

Absolute Maximum Ratings

Symbol Parameter Min Max Units

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

General Electrical Characteristics

Symbol Parameter Condition Min Typ Max Units

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Publication Date: Jan. 2018

0.1F 0.1F 0.1F 0.1F DEF Default Mute Default Un-Mute

PLL Enable External

Elite Semiconductor Memory Technology Inc.

4.7K 4.7K ≧3A

SDA 10 10

Publication Date: Jan. 2018

0.1F 0.1F 0.1F 0.1F

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2018

0.1F 0.1F 0.1F 0.1F PD Power Down Normal

MONO Stereo Mono

PLL PLL Enable External

Elite Semiconductor Memory Technology Inc.

Symbol Parameter Condition Input Level Min Typ Max Units

Total Harmonic Distortion + Noise vs. Output Power (Stereo)

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Frequency Response (Stereo)

+0.8 24V, 8Ω +0.8

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Efficiency vs. Output Power (Stereo)

Efficiency (Stereo) for PWM of Power Saving Mode

Efficiency vs. Output Power (Stereo)

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Symbol Parameter Condition Input Level Min Typ Max Units

Total Harmonic Distortion + Noise vs. Output Power (Mono)

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Frequency Response (Mono)

+0.8 24V, 4Ω +0.8

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

Efficiency vs. Output Power (Mono)

Efficiency (Mono) for PWM of Power Saving Mode

Efficiency vs. Output Power (Mono)

60 switching level: 30 W/O power saving mode

Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2018

 I2S LRCIN Left Right

SDATA MSB LSB MSB LSB

 Left-Alignment LRCIN Left Right

SDATA MSB LSB MSB LSB

 Right-Alignment LRCIN Left Right

SDATA MSB LSB MSB LSB

 System Clock Timing

t HIGH ≧ 40 . 4 ns , t LOW ≧ 40 . 4 ns , t PERIOD ≧ 80 .8 ns Default setting,when PLL is enable

t HIGH ≧ 10 . 1 ns , t LOW ≧ 10 . 1 ns , t PERIOD ≧ 20 .2 ns When PLL is disable