EUSART

PIC16(L)F1946/47
25.0 ENHANCED UNIVERSAL These devices typically do not have internal clocks for
baud rate generation and require the external clock
SYNCHRONOUS
signal provided by a master synchronous device.
ASYNCHRONOUS RECEIVER
The EUSART module includes the following capabilities:
TRANSMITTER (EUSART)
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
Note: The PIC16(L)F1946/47 devices have two • One-character output buffer
EUSARTs. Therefore, all information in • Programmable 8-bit or 9-bit character length
this section refers to both EUSART 1 and • Address detection in 9-bit mode
EUSART 2.
• Input buffer overrun error detection
The Enhanced Universal Synchronous Asynchronous • Received character framing error detection
Receiver Transmitter (EUSART) module is a serial I/O • Half-duplex synchronous master
communications peripheral. It contains all the clock
• Half-duplex synchronous slave
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer • Programmable clock polarity in synchronous
independent of device program execution. The modes
EUSART, also known as a Serial Communications • Sleep operation
Interface (SCI), can be configured as a full-duplex The EUSART module implements the following
asynchronous system or half-duplex synchronous additional features, making it ideally suited for use in
system. Full-Duplex mode is useful for Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
• Automatic detection and calibration of the baud rate
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications • Wake-up on Break reception
with peripheral devices, such as A/D or D/A integrated • 13-bit Break character transmit
circuits, serial EEPROMs or other microcontrollers. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 25-1 and Figure 25-2.
FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXxIE
Interrupt
TXxREG Register TXxIF
8
MSb LSb TXx/CKx pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)
TXEN
TRMT
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
 2010-2012 Microchip Technology Inc. DS41414D-page 297

PIC16(L)F1946/47
FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM
CREN OERR RCIDL
RXx/DTx pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 START
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH X 1 1 0 0 FIFO
FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCxIF Interrupt
RCxIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 25-1,
Register 25-2 and Register 25-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RXx/DTx and TXx/CKx pins
should be set to ‘1’. The EUSART control will
automatically reconfigure the pin from input to output, as
needed.
When the receiver or transmitter section is not enabled
then the corresponding RXx/DTx or TXx/CKx pin may be
used for general purpose input and output.
DS41414D-page 298  2010-2012 Microchip Technology Inc.

PIC16(L)F1946/47
25.1 EUSART Asynchronous Mode 25.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXxREG register. If this is the first character, or the
implemented with two levels: a VOH mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXxREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXxREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the mark state. Each character character in the TXxREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is 8 bits. Each transmitted bit persists for a period TXxREG.
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate 25.1.1.3 Transmit Data Polarity
frequencies from the system oscillator. See Table 25-5 The polarity of the transmit data can be controlled with
for examples of baud rate configurations. the CKTXP bit of the BAUDxCON register. The default
The EUSART transmits and receives the LSb first. The state of this bit is ‘0’ which selects high true transmit
EUSART’s transmitter and receiver are functionally idle and data bits. Setting the CKTXP bit to ‘1’ will invert
independent, but share the same data format and baud the transmit data resulting in low true idle and data bits.
rate. Parity is not supported by the hardware, but can The CKTXP bit controls transmit data polarity only in
be implemented in software and stored as the ninth Asynchronous mode. In Synchronous mode the
data bit. CKTXP bit has a different function. See
Section 25.5.1.2 “Clock Polarity”.
25.1.1 EUSART ASYNCHRONOUS
TRANSMITTER 25.1.1.4 Transmit Interrupt Flag
The TXxIF interrupt flag bit of the PIR1/PIR3 register is
The EUSART transmitter block diagram is shown in
set whenever the EUSART transmitter is enabled and
Figure 25-1. The heart of the transmitter is the serial
no character is being held for transmission in the
Transmit Shift Register (TSR), which is not directly
TXxREG. In other words, the TXxIF bit is only clear
accessible by software. The TSR obtains its data from
when the TSR is busy with a character and a new
the transmit buffer, which is the TXxREG register.
character has been queued for transmission in the
25.1.1.1 Enabling the Transmitter TXxREG. The TXxIF flag bit is not cleared immediately
upon writing TXxREG. TXxIF becomes valid in the
The EUSART transmitter is enabled for asynchronous second instruction cycle following the write execution.
operations by configuring the following three control Polling TXxIF immediately following the TXxREG write
bits: will return invalid results. The TXxIF bit is read-only, it
• TXEN = 1 cannot be set or cleared by software.
• SYNC = 0 The TXxIF interrupt can be enabled by setting the
• SPEN = 1 TXxIE interrupt enable bit of the PIE1/PIE4 register.
However, the TXxIF flag bit will be set whenever the
All other EUSART control bits are assumed to be in
TXxREG is empty, regardless of the state of TXxIE
their default state.
enable bit.
Setting the TXEN bit of the TXxSTA register enables the
To use interrupts when transmitting data, set the TXxIE
transmitter circuitry of the EUSART. Clearing the SYNC
bit only when there is more data to send. Clear the
bit of the TXxSTA register configures the EUSART for
TXxIE interrupt enable bit upon writing the last
asynchronous operation. Setting the SPEN bit of the
character of the transmission to the TXxREG.
RCxSTA register enables the EUSART. The program-
mer must set the corresponding TRIS bit to configure the
TXx/CKx I/O pin as an output. If the TXx/CKx pin is
shared with an analog peripheral, the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
Note: The TXxIF transmitter interrupt flag is set
when the TXEN enable bit is set.

PIC16(L)F1946/47
25.1.1.5 TSR Status 25.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXxSTA register indicates the 1. Initialize the SPxBRGH:SPxBRGL register pair
status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the
TRMT bit is set when the TSR register is empty and is desired baud rate (see Section 25.4 “EUSART
cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”).
register from the TXxREG. The TRMT bit remains clear 2. Set the RXx/DTx and TXx/CKx TRIS controls to
until all bits have been shifted out of the TSR register. ‘1’.
No interrupt logic is tied to this bit, so the user needs to 3. Enable the asynchronous serial port by clearing
poll this bit to determine the TSR status. the SYNC bit and setting the SPEN bit.
Note: The TSR register is not mapped in data 4. If 9-bit transmission is desired, set the TX9
memory, so it is not available to the user. control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
25.1.1.6 Transmitting 9-Bit Characters when the receiver is set for address detection.
The EUSART supports 9-bit character transmissions. 5. Set the CKTXP control bit if inverted transmit
When the TX9 bit of the TXxSTA register is set the data polarity is desired.
EUSART will shift 9 bits out for each character transmit- 6. Enable the transmission by setting the TXEN
ted. The TX9D bit of the TXxSTA register is the ninth, control bit. This will cause the TXxIF interrupt bit
and Most Significant, data bit. When transmitting 9-bit to be set.
data, the TX9D data bit must be written before writing 7. If interrupts are desired, set the TXxIE interrupt
the 8 Least Significant bits into the TXxREG. All nine enable bit. An interrupt will occur immediately
bits of data will be transferred to the TSR shift register provided that the GIE and PEIE bits of the
immediately after the TXxREG is written. INTCON register are also set.
A special 9-bit Address mode is available for use with 8. If 9-bit transmission is selected, the ninth bit
multiple receivers. See Section 25.1.2.8 “Address should be loaded into the TX9D data bit.
Detection” for more information on the Address mode. 9. Load 8-bit data into the TXxREG register. This
will start the transmission.
FIGURE 25-3: ASYNCHRONOUS TRANSMISSION
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
TRMT bit Word 1

Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)

PIC16(L)F1946/47
FIGURE 25-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TXx/CKx pin Start bit Start bit
bit 0 bit 1 bit 7/8 Stop bit bit 0
TXxIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg
Reg. Empty Flag) Transmit Shift Reg
Note: This timing diagram shows two consecutive transmissions.
TABLE 25-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92
PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 93
PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE 96
PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 97
PIR4 — — RC2IF TX2IF — — BCL2IF SSP2IF 100
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 308
SP1BRGL EUSART1 Baud Rate Generator, Low Byte 310*
SP1BRGH EUSART1 Baud Rate Generator, High Byte 310*
TX1REG EUSART1 Transmit Register 302*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 307
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.
* Page provides register information.

PIC16(L)F1946/47
25.1.2 EUSART ASYNCHRONOUS 25.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit,
RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data
in Figure 25-2. The data is received on the RXx/DTx recovery circuit counts one-half bit time to the center of
pin and drives the data recovery block. The data the Start bit and verifies that the bit is still a zero. If it is
recovery block is actually a high-speed shifter not a zero then the data recovery circuit aborts
operating at 16 times the baud rate, whereas the serial character reception, without generating an error, and
Receive Shift Register (RSR) operates at the bit rate. resumes looking for the falling edge of the Start bit. If
When all 8 or 9 bits of the character have been shifted the Start bit zero verification succeeds then the data
in, they are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCxREG a ‘1’. If the data recovery circuit samples a ‘0’ in the
register. Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
25.1.2.1 Enabling the Receiver character. See Section 25.1.2.5 “Receive Framing
The EUSART receiver is enabled for asynchronous Error” for more information on framing errors.
operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have
• CREN = 1 been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCxIF interrupt
• SYNC = 0
flag bit of the PIR1/PIR3 register is set. The top charac-
• SPEN = 1 ter in the FIFO is transferred out of the FIFO by reading
All other EUSART control bits are assumed to be in the RCxREG register.
their default state.
Note: If the receive FIFO is overrun, no additional
Setting the CREN bit of the RCxSTA register enables characters will be received until the overrun
the receiver circuitry of the EUSART. Clearing the SYNC condition is cleared. See Section 25.1.2.6
bit of the TXxSTA register configures the EUSART for “Receive Overrun Error” for more
asynchronous operation. Setting the SPEN bit of the information on overrun errors.
RCxSTA register enables the EUSART. The
programmer must set the corresponding TRIS bit to 25.1.2.3 Receive Data Polarity
configure the RXx/DTx I/O pin as an input. The polarity of the receive data can be controlled with
Note 1: If the RX/DT function is on an analog pin, the DTRXP bit of the BAUDxCON register. The default
the corresponding ANSEL bit must be state of this bit is ‘0’ which selects high true receive idle
cleared for the receiver to function. and data bits. Setting the DTRXP bit to ‘1’ will invert the
receive data resulting in low true idle and data bits. The
If the RXx/DTx pin is shared with an analog peripheral
DTRXP bit controls receive data polarity only in
the analog I/O function must be disabled by clearing the
Asynchronous mode. In synchronous mode the
corresponding ANSEL bit.
DTRXP bit has a different function.

PIC16(L)F1946/47
25.1.2.4 Receive Interrupts 25.1.2.7 Receiving 9-bit Characters
The RCxIF interrupt flag bit of the PIR1/PIR3 register is The EUSART supports 9-bit character reception. When
set whenever the EUSART receiver is enabled and the RX9 bit of the RCxSTA register is set, the EUSART
there is an unread character in the receive FIFO. The will shift 9 bits into the RSR for each character
RCxIF interrupt flag bit is read-only, it cannot be set or received. The RX9D bit of the RCxSTA register is the
cleared by software. ninth and Most Significant data bit of the top unread
RCxIF interrupts are enabled by setting the following character in the receive FIFO. When reading 9-bit data
bits: from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
• RCxIE interrupt enable bit of the PIE1/PIE4 the RCxREG.
register
• PEIE peripheral interrupt enable bit of the INTCON 25.1.2.8 Address Detection
register A special Address Detection mode is available for use
• GIE global interrupt enable bit of the INTCON when multiple receivers share the same transmission
register line, such as in RS-485 systems. Address detection is
The RCxIF interrupt flag bit will be set when there is an enabled by setting the ADDEN bit of the RCxSTA
unread character in the FIFO, regardless of the state of register.
interrupt enable bits. Address detection requires 9-bit character reception.
When address detection is enabled, only characters
25.1.2.5 Receive Framing Error with the ninth data bit set will be transferred to the
Each character in the receive FIFO buffer has a receive FIFO buffer, thereby setting the RCxIF interrupt
corresponding framing error Status bit. A framing error bit. All other characters will be ignored.
indicates that a Stop bit was not seen at the expected Upon receiving an address character, user software
time. The framing error status is accessed via the determines if the address matches its own. Upon
FERR bit of the RCxSTA register. The FERR bit address match, user software must disable address
represents the status of the top unread character in the detection by clearing the ADDEN bit before the next
receive FIFO. Therefore, the FERR bit must be read Stop bit occurs. When user software detects the end of
before reading the RCxREG. the message, determined by the message protocol
The FERR bit is read-only and only applies to the top used, software places the receiver back into the
unread character in the receive FIFO. A framing error Address Detection mode by setting the ADDEN bit.
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR
bit.
25.1.2.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.

PIC16(L)F1946/47
25.1.2.9 Asynchronous Reception Set-up: 25.1.2.10 9-bit Address Detection Mode Set-up
1. Initialize the SPxBRGH:SPxBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 25.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPxBRGH, SPxBRGL register pair
2. Set the RXx/DTx and TXx/CKx TRIS controls to and the BRGH and BRG16 bits to achieve the
‘1’. desired baud rate (see Section 25.4 “EUSART
3. Enable the serial port by setting the SPEN bit Baud Rate Generator (BRG)”).
and the RXx/DTx pin TRIS bit. The SYNC bit 2. Set the RXx/DTx and TXx/CKx TRIS controls to
must be clear for asynchronous operation. ‘1’.
4. If interrupts are desired, set the RCxIE interrupt 3. Enable the serial port by setting the SPEN bit.
enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCxIE interrupt
6. Set the DTRXP if inverted receive polarity is enable bit and set the GIE and PEIE bits of the
desired. INTCON register.
7. Enable reception by setting the CREN bit. 5. Enable 9-bit reception by setting the RX9 bit.
8. The RCxIF interrupt flag bit will be set when a 6. Enable address detection by setting the ADDEN
character is transferred from the RSR to the bit.
receive buffer. An interrupt will be generated if 7. Set the DTRXP if inverted receive polarity is
the RCxIE interrupt enable bit was also set. desired.
9. Read the RCxSTA register to get the error flags 8. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 9. The RCxIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
10. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCxREG will be generated if the RCxIE interrupt enable
register. bit was also set.
11. If an overrun occurred, clear the OERR flag by 10. Read the RCxSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
11. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
12. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
13. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.

PIC16(L)F1946/47
FIGURE 25-5: ASYNCHRONOUS RECEPTION
Start Start Start
RXx/DTx pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg
Word 1 Word 2
RCxREG RCxREG
RCIDL
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 25-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register
on Page
RC1REG EUSART1 Receive Register 302*
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.

PIC16(L)F1946/47
25.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (HFINTOSC). However, the HFINTOSC
frequency may drift as VDD or temperature changes,
and this directly affects the asynchronous baud rate.
Two methods may be used to adjust the baud rate
clock, but both require a reference clock source of
some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 5.2
“Clock Source Types” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 25.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

PIC16(L)F1946/47
25.3 Register Definitions: EUSART Control
REGISTER 25-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16(L)F1946/47
REGISTER 25-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16(L)F1946/47
REGISTER 25-3: BAUDxCON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TXx/CKx pin
0 = Transmit non-inverted data to the TXx/CKx pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16(L)F1946/47
25.4 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 25-1: CALCULATING BAUD
BRG16 bit of the BAUDxCON register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPxBRGH:SPxBRGL register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
F OS C
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = --------------------------------------------------------------------------
64  [SPxBRGH:SPxBRG] + 1 
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON Solving for SPxBRGH:SPxBRGL:
register. In Synchronous mode, the BRGH bit is ignored.
F OS C
---------------------------------------------
Example 25-1 provides a sample calculation for deter- Desired Baud Rate
SPxBRGH: SPxBRGL = --------------------------------------------- – 1
mining the desired baud rate, actual baud rate, and 64
baud rate % error. 16000000
------------------------
Typical baud rates and error values for various 9600
= ------------------------ – 1
asynchronous modes have been computed for your 64
convenience and are shown in Table 25-5. It may be =  25.042  = 25
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 16000000
ActualBaudRate = ---------------------------
64  25 + 1 
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies. = 9615
Writing a new value to the SPxBRGH, SPxBRGL
Calc. Baud Rate – Desired Baud Rate
register pair causes the BRG timer to be reset (or Baud Rate % Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.  9615 – 9600 
= ---------------------------------- = 0.16%
9600
TABLE 25-3: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair

PIC16(L)F1946/47
TABLE 25-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
page
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG.
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
BAUD
RATE SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 2404 0.16 207 2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9615 0.16 51 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 47 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.23k 0.16 25 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k 55.55k -3.55 3 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —

PIC16(L)F1946/47
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 191 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 103 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.14k -0.79 34 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 117.64k 2.12 16 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
RATE SPxBRGH: SPxBRGH: SPxBRGH: SPxBRGH:
SPxBRGL SPxBRGL SPxBRGL SPxBRGL
300 300.0 0.00 6666 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200.1 0.02 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2401 -0.04 832 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 207 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 191 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 103 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.14k -0.79 34 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 117.6k 2.12 16 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5

PIC16(L)F1946/47
TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300 0.00 26666 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 0.00 6666 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.01 3332 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9604 0.04 832 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 767 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.18k -0.08 416 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 115.9 0.64 68 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

PIC16(L)F1946/47
25.4.1 AUTO-BAUD DETECT 1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
The EUSART module supports automatic detection
speed.
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the Note 1: If the WUE bit is set with the ABDEN bit,
BRG is reversed. Rather than the BRG clocking the auto-baud detection will occur on the byte
incoming RXx signal, the RXx signal is timing the BRG. following the Break character (see
The Baud Rate Generator is used to time the period of Section 25.4.3 “Auto-Wake-up on
a received 55h (ASCII “U”) which is the Sync character Break”).
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
Setting the ABDEN bit of the BAUDxCON register range of the selected BRG clock source.
starts the auto-baud calibration sequence Some combinations of oscillator frequency
(Figure 25.4.2). While the ABD sequence takes place, and EUSART baud rates are not possible.
the EUSART state machine is held in Idle. On the first 3: During the auto-baud process, the
rising edge of the receive line, after the Start bit, the auto-baud counter starts counting at 1.
SPxBRGL begins counting up using the BRG counter Upon completion of the auto-baud
clock as shown in Table 25-6. The fifth rising edge will sequence, to achieve maximum accu-
occur on the RXx/DTx pin at the end of the eighth bit racy, subtract 1 from the SPxBRGH:SPx-
period. At that time, an accumulated value totaling the BRGL register pair.
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on TABLE 25-6: BRG COUNTER CLOCK
the RCxREG needs to be performed to clear the RCxIF RATES
interrupt. RCxREG content should be discarded. When BRG Base BRG ABD
calibrating for modes that do not use the SPxBRGH BRG16 BRGH
Clock Clock
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH 0 0 FOSC/64 FOSC/512
register. 0 1 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16
1 0 FOSC/16 FOSC/128
and BRGH bits as shown in Table 25-6. During ABD,
both the SPxBRGH and SPxBRGL registers are used 1 1 FOSC/4 FOSC/32
as a 16-bit counter, independent of the BRG16 bit set- Note: During the ABD sequence, SPxBRGL and
ting. While calibrating the baud rate period, the SPxBRGH registers are both used as a
SPxBRGH and SPxBRGL registers are clocked at 16-bit counter, independent of BRG16
setting.
FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION
BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
RXx/DTx pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
SPxBRGL XXh 1Ch
SPxBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16(L)F1946/47
25.4.2 AUTO-BAUD OVERFLOW 25.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDxCON register will be set if the To avoid character errors or character fragments during
baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all
is detected on the RX pin. The ABDOVF bit indicates zeros.
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPxBRGH:SPxBRGL When the wake-up is enabled the function works
register pair. After the ABDOVF bit has been set, the independent of the low time on the data stream. If the
counter continues to count until the fifth rising edge is WUE bit is set and a valid non-zero character is
detected on the RXx/DTx pin. Upon detecting the fifth received, the low time from the Start bit to the first rising
RXx/DTx edge, the hardware will set the RCxIF inter- edge will be interpreted as the wake-up event. The
rupt flag and clear the ABDEN bit of the BAUDxCON remaining bits in the character will be received as a
register. The RCxIF flag can be subsequently cleared fragmented character and subsequent characters can
by reading the RCxREG. The ABDOVF flag can be result in framing or overrun errors.
cleared by software directly. Therefore, the initial character in the transmission must
To terminate the auto-baud process before the RCxIF be all ‘0’s. This must be 10 or more bit times, 13-bit
flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit
bit. The ABDOVF bit will remain set if the ABDEN bit is times for standard RS-232 devices.
not cleared first. Oscillator Startup Time
Oscillator start-up time must be considered, especially
25.4.3 AUTO-WAKE-UP ON BREAK
in applications using oscillators with longer start-up
During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync
suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of
is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient
performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator
controller to wake-up due to activity on the RXx/DTx to start and provide proper initialization of the EUSART.
line. This feature is available only in Asynchronous
WUE Bit
mode.
The wake-up event causes a receive interrupt by
The Auto-Wake-up feature is enabled by setting the
setting the RCxIF bit. The WUE bit is cleared by
WUE bit of the BAUDxCON register. Once set, the
hardware by a rising edge on RXx/DTx. The interrupt
normal receive sequence on RXx/DTx is disabled, and
condition is then cleared by software by reading the
the EUSART remains in an Idle state, monitoring for a
RCxREG register and discarding its contents.
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the To ensure that no actual data is lost, check the RCIDL
RXx/DTx line. (This coincides with the start of a Sync bit to verify that a receive operation is not in process
Break or a wake-up signal character for the LIN before setting the WUE bit. If a receive operation is not
protocol.) occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCxIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 25-7), and asynchronously if
the device is in Sleep mode (Figure 25-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RXx line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

PIC16(L)F1946/47
FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RXx/DTx Line
RCxIF
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RXx/DTx Line Note 1

RCxIF
Cleared due to User Read of RCxREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC16(L)F1946/47
25.4.4 BREAK CHARACTER SEQUENCE When the TXxREG becomes empty, as indicated by
the TXxIF, the next data byte can be written to TXxREG.
The EUSART module has the capability of sending the
special Break character sequences that are required by
25.4.5 RECEIVING A BREAK CHARACTER
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit. The Enhanced EUSART module can receive a Break
character in two ways.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character trans- The first method to detect a Break character uses the
mission is then initiated by a write to the TXxREG. The FERR bit of the RCxSTA register and the Received
value of data written to TXxREG will be ignored and all data as indicated by RCxREG. The Baud Rate
‘0’s will be transmitted. Generator is assumed to have been initialized to the
expected baud rate.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user A Break character has been received when;
to preload the transmit FIFO with the next transmit byte • RCxIF bit is set
following the Break character (typically, the Sync • FERR bit is set
character in the LIN specification).
• RCxREG = 00h
The TRMT bit of the TXxSTA register indicates when the
The second method uses the Auto-Wake-up feature
transmit operation is active or Idle, just as it does during
described in Section 25.4.3 “Auto-Wake-up on
normal transmission. See Figure 25-9 for the timing of
Break”. By enabling this feature, the EUSART will
the Break character sequence.
sample the next two transitions on RXx/DTx, cause an
25.4.4.1 Break and Sync Transmit Sequence RCxIF interrupt, and receive the next data byte
followed by another interrupt.
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud Note that following a Break character, the user will
Sync byte. This sequence is typical of a LIN bus typically want to enable the Auto-Baud Detect feature.
master. For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
1. Configure the EUSART for the desired mode. Sleep mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync charac-
ter into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
FIGURE 25-9: SEND BREAK CHARACTER SEQUENCE
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXxIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16(L)F1946/47
25.5 EUSART Synchronous Mode 25.5.1.2 Clock Polarity
Synchronous serial communications are typically used A clock polarity option is provided for Microwire
in systems with a single master and one or more compatibility. Clock polarity is selected with the CKTXP
slaves. The master device contains the necessary bit of the BAUDxCON register. Setting the CKTXP bit
circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the CKTXP bit
for all devices in the system. Slave devices can take is set, the data changes on the falling edge of each
advantage of the master clock by eliminating the clock and is sampled on the rising edge of each clock.
internal clock generation circuitry. Clearing the CKTXP bit sets the Idle state as low. When
the CKTXP bit is cleared, the data changes on the
There are two signal lines in Synchronous mode: a rising edge of each clock and is sampled on the falling
bidirectional data line and a clock line. Slaves use the edge of each clock.
external clock supplied by the master to shift the serial
data into and out of their respective receive and 25.5.1.3 Synchronous Master Transmission
transmit shift registers. Since the data line is
Data is transferred out of the device on the RXx/DTx
bidirectional, synchronous operation is half-duplex
pin. The RXx/DTx and TXx/CKx pin output drivers are
only. Half-duplex refers to the fact that master and
automatically enabled when the EUSART is configured
slave devices can receive and transmit data but not
for synchronous master transmit operation.
both simultaneously. The EUSART can operate as
either a master or slave device. A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
Start and Stop bits are not used in synchronous
a previous character the new character data is held in
transmissions.
the TXxREG until the last bit of the previous character
25.5.1 SYNCHRONOUS MASTER MODE has been transmitted. If this is the first character, or the
previous character has been completely flushed from
The following bits are used to configure the EUSART the TSR, the data in the TXxREG is immediately trans-
for Synchronous Master operation: ferred to the TSR. The transmission of the character
• SYNC = 1 commences immediately following the transfer of the
• CSRC = 1 data to the TSR from the TXxREG.
• SREN = 0 (for transmit); SREN = 1 (for receive) Each data bit changes on the leading edge of the
• CREN = 0 (for transmit); CREN = 1 (for receive) master clock and remains valid until the subsequent
leading clock edge.
• SPEN = 1
Setting the SYNC bit of the TXxSTA register configures Note: The TSR register is not mapped in data
the device for synchronous operation. Setting the CSRC memory, so it is not available to the user.
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the 25.5.1.4 Data Polarity
RCxSTA register ensures that the device is in the The polarity of the transmit and receive data can be
Transmit mode, otherwise the device will be configured controlled with the DTRXP bit of the BAUDxCON
to receive. Setting the SPEN bit of the RCxSTA register register. The default state of this bit is ‘0’ which selects
enables the EUSART. If the RXx/DTx or TXx/CKx pins high true transmit and receive data. Setting the DTRXP
are shared with an analog peripheral the analog I/O bit to ‘1’ will invert the data resulting in low true transmit
functions must be disabled by clearing the corresponding and receive data.
ANSEL bits.
The TRIS bits corresponding to the RXx/DTx and
TXx/CKx pins should be set.
25.5.1.1 Master Clock

Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TXx/CKx line. The
TXx/CKx pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.

PIC16(L)F1946/47
25.5.1.5 Synchronous Master Transmission 4. Disable Receive mode by clearing bits SREN
Set-up: and CREN.
1. Initialize the SPxBRGH, SPxBRGL register pair 5. Enable Transmit mode by setting the TXEN bit.
and the BRGH and BRG16 bits to achieve the 6. If 9-bit transmission is desired, set the TX9 bit.
desired baud rate (see Section 25.4 “EUSART 7. If interrupts are desired, set the TXxIE, GIE and
Baud Rate Generator (BRG)”). PEIE interrupt enable bits.
2. Set the RXx/DTx and TXx/CKx TRIS controls to 8. If 9-bit transmission is selected, the ninth bit
‘1’. should be loaded in the TX9D bit.
3. Enable the synchronous master serial port by 9. Start transmission by loading data to the
setting bits SYNC, SPEN and CSRC. Set the TXxREG register.
TRIS bits corresponding to the RXx/DTx and
TXx/CKx I/O pins.
FIGURE 25-10: SYNCHRONOUS TRANSMISSION

RXx/DTx
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7
TXx/CKx pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit

PIC16(L)F1946/47
TABLE 25-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.

PIC16(L)F1946/47
25.5.1.6 Synchronous Master Reception If the overrun occurred when the CREN bit is set then
the error condition is cleared by either clearing the
Data is received at the RXx/DTx pin. The RXx/DTx pin
CREN bit of the RCxSTA register or by clearing the
output driver must be disabled by setting the
SPEN bit which resets the EUSART.
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
25.5.1.9 Receiving 9-bit Characters
In Synchronous mode, reception is enabled by setting
The EUSART supports 9-bit character reception. When
either the Single Receive Enable bit (SREN of the
the RX9 bit of the RCxSTA register is set the EUSART
RCxSTA register) or the Continuous Receive Enable
will shift 9-bits into the RSR for each character
bit (CREN of the RCxSTA register).
received. The RX9D bit of the RCxSTA register is the
When SREN is set and CREN is clear, only as many ninth, and Most Significant, data bit of the top unread
clock cycles are generated as there are data bits in a character in the receive FIFO. When reading 9-bit data
single character. The SREN bit is automatically cleared from the receive FIFO buffer, the RX9D data bit must
at the completion of one character. When CREN is set, be read before reading the 8 Least Significant bits from
clocks are continuously generated until CREN is the RCxREG.
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac- 25.5.1.10 Synchronous Master Reception
ter is discarded. If SREN and CREN are both set, then Set-up:
SREN is cleared at the completion of the first character
1. Initialize the SPxBRGH, SPxBRGL register pair
and CREN takes precedence.
for the appropriate baud rate. Set or clear the
To initiate reception, set either SREN or CREN. Data is BRGH and BRG16 bits, as required, to achieve
sampled at the RXx/DTx pin on the trailing edge of the the desired baud rate.
TXx/CKx clock pin and is shifted into the Receive Shift 2. Set the RXx/DTx and TXx/CKx TRIS controls to
Register (RSR). When a complete character is ‘1’.
received into the RSR, the RCxIF bit is set and the
3. Enable the synchronous master serial port by
character is automatically transferred to the two
setting bits SYNC, SPEN and CSRC. Disable
character receive FIFO. The Least Significant eight bits
RXx/DTx and TXx/CKx output drivers by setting
of the top character in the receive FIFO are available in
the corresponding TRIS bits.
RCxREG. The RCxIF bit remains set as long as there
are un-read characters in the receive FIFO. 4. Ensure bits CREN and SREN are clear.
5. If using interrupts, set the GIE and PEIE bits of
25.5.1.7 Slave Clock the INTCON register and set RCxIE.
Synchronous data transfers use a separate clock line, 6. If 9-bit reception is desired, set bit RX9.
which is synchronous with the data. A device configured 7. Start reception by setting the SREN bit or for
as a slave receives the clock on the TXx/CKx line. The continuous reception, set the CREN bit.
TXx/CKx pin output driver must be disabled by setting 8. Interrupt flag bit RCxIF will be set when recep-
the associated TRIS bit when the device is configured tion of a character is complete. An interrupt will
for synchronous slave transmit or receive operation. be generated if the enable bit RCxIE was set.
Serial data bits change on the leading edge to ensure 9. Read the RCxSTA register to get the ninth bit (if
they are valid at the trailing edge of each clock. One data enabled) and determine if any error occurred
bit is transferred for each clock cycle. Only as many during reception.
clock cycles should be received as there are data bits.
10. Read the 8-bit received data by reading the
RCxREG register.
25.5.1.8 Receive Overrun Error
11. If an overrun error occurs, clear the error by
The receive FIFO buffer can hold two characters. An either clearing the CREN bit of the RCxSTA
overrun error will be generated if a third character, in its register or by clearing the SPEN bit which resets
entirety, is received before RCxREG is read to access the EUSART.
the FIFO. When this happens the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCxREG.

PIC16(L)F1946/47
FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCxIF bit
(Interrupt)
Read
RCxREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 25-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.

PIC16(L)F1946/47
25.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for Synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXxREG
• CSRC = 0
register.
• SREN = 0 (for transmit); SREN = 1 (for receive)
3. The TXxIF bit will not be set.
• CREN = 0 (for transmit); CREN = 1 (for receive)
4. After the first character has been shifted out of
• SPEN = 1 TSR, the TXxREG register will transfer the
Setting the SYNC bit of the TXxSTA register configures second character to the TSR and the TXxIF bit
the device for synchronous operation. Clearing the will now be set.
CSRC bit of the TXxSTA register configures the device as 5. If the PEIE and TXxIE bits are set, the interrupt
a slave. Clearing the SREN and CREN bits of the will wake the device from Sleep and execute the
RCxSTA register ensures that the device is in the next instruction. If the GIE bit is also set, the
Transmit mode, otherwise the device will be configured to program will call the Interrupt Service Routine.
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins 25.5.2.2 Synchronous Slave Transmission
are shared with an analog peripheral the analog I/O Set-up:
functions must be disabled by clearing the corresponding
1. Set the SYNC and SPEN bits and clear the
ANSEL bits.
CSRC bit.
RXx/DTx and TXx/CKx pin output drivers must be 2. Set the RXx/DTx and TXx/CKx TRIS controls to
disabled by setting the corresponding TRIS bits. ‘1’.
25.5.2.1 EUSART Synchronous Slave 3. Clear the CREN and SREN bits.
Transmit 4. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
The operation of the Synchronous Master and Slave TXxIE bit.
modes are identical (see Section 25.5.1.3
5. If 9-bit transmission is desired, set the TX9 bit.
“Synchronous Master Transmission”), except in the
case of the Sleep mode. 6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXxREG register.

PIC16(L)F1946/47
TABLE 25-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.

PIC16(L)F1946/47
25.5.2.3 EUSART Synchronous Slave 25.5.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 25.5.1.6 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Set the RXx/DTx and TXx/CKx TRIS controls to
• Sleep ‘1’.
• CREN bit is always set, therefore the receiver is 3. If using interrupts, ensure that the GIE and PEIE
never Idle bits of the INTCON register are set and set the
• SREN bit, which is a “don’t care” in Slave mode RCxIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCxIF bit will be set when reception is
to the RCxREG register. If the RCxIE enable bit is set, complete. An interrupt will be generated if the
the interrupt generated will wake the device from Sleep RCxIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 25-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.

PIC16(L)F1946/47
NOTES:

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PIC16(L)F1946/47

FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM

 2010-2012 Microchip Technology Inc. DS41414D-page 297

CREN OERR RCIDL

RXx/DTx pin MSb RSR Register LSb

Baud Rate Generator FOSC RX9

The operation of the EUSART module is controlled

DS41414D-page 298  2010-2012 Microchip Technology Inc.

 2010-2012 Microchip Technology Inc. DS41414D-page 299

FIGURE 25-3: ASYNCHRONOUS TRANSMISSION

TRMT bit Word 1

DS41414D-page 300  2010-2012 Microchip Technology Inc.

Note: This timing diagram shows two consecutive transmissions.

TABLE 25-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

 2010-2012 Microchip Technology Inc. DS41414D-page 301

DS41414D-page 302  2010-2012 Microchip Technology Inc.

25.1.2.6 Receive Overrun Error

 2010-2012 Microchip Technology Inc. DS41414D-page 303

DS41414D-page 304  2010-2012 Microchip Technology Inc.

TABLE 25-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

 2010-2012 Microchip Technology Inc. DS41414D-page 305

DS41414D-page 306  2010-2012 Microchip Technology Inc.

REGISTER 25-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER

bit 7 CSRC: Clock Source Select bit

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2010-2012 Microchip Technology Inc. DS41414D-page 307

REGISTER 25-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER

bit 7 SPEN: Serial Port Enable bit

DS41414D-page 308  2010-2012 Microchip Technology Inc.

REGISTER 25-3: BAUDxCON: BAUD RATE CONTROL REGISTER

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

 2010-2012 Microchip Technology Inc. DS41414D-page 309

TABLE 25-3: BAUD RATE FORMULAS

0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

DS41414D-page 310  2010-2012 Microchip Technology Inc.

TABLE 25-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

 2010-2012 Microchip Technology Inc. DS41414D-page 311

SYNC = 0, BRGH = 1, BRG16 = 0

SYNC = 0, BRGH = 0, BRG16 = 1

DS41414D-page 312  2010-2012 Microchip Technology Inc.

SYNC = 0, BRGH = 0, BRG16 = 1

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

 2010-2012 Microchip Technology Inc. DS41414D-page 313

FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION

BRG Value XXXXh 0000h 001Ch

Set by User Auto Cleared

SPxBRGL XXh 1Ch

SPxBRGH XXh 00h

DS41414D-page 314  2010-2012 Microchip Technology Inc.

 2010-2012 Microchip Technology Inc. DS41414D-page 315

FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

RXx/DTx Line Note 1

DS41414D-page 316  2010-2012 Microchip Technology Inc.

FIGURE 25-9: SEND BREAK CHARACTER SEQUENCE

TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit

 2010-2012 Microchip Technology Inc. DS41414D-page 317