Power Supply Design Seminar

Common Mistakes in DC/DC Converters

and How to Fix Them

Reproduced from
2018 Texas Instruments Power Supply Design Seminar
SEM2300,
Topic 5
TI Literature Number: SLUP384

© 2018 Texas Instruments Incorporated

Power Supply Design Seminar resources

are available at:
www.ti.com/psds
 Common Mistakes in DC/DC Converters
and How to Fix Them
Pradeep Shenoy and Anthony Fagnani

AbstrAct

If you want to learn from the mistakes of others, this session is for you. This practical presentation goes
through a number of common mistakes in point-of-load DC/DC converter design and testing. With an
engaging, interactive format, this session covers issues found in converter capabilities, component
selection, control design, board layout and measurement techniques. The causes of the design mistakes
and how to avoid them in future designs are explained.

I. Introduction node voltage (VSW) and inductor current waveform

No one likes to make mistakes. While we are are shown in Figure 2. While other converter
bound to make them in our engineering journey, it topologies, like the boost converter, buck-boost
is better if we can learn from the mistakes of converter, series capacitor buck converter [1][2]
others. This paper aims to highlight common and many others may also be used, this discussion
mistakes in DC/DC converters. To remain simple focuses on the buck converter for simplicity.
and succinct, this paper overviews the most
Switching Period
frequently seen errors and how to avoid them.
VSW(V) Q1(ON) Q2(ON)
References are provided for more detailed learning
VIN
and information when possible. Let’s begin with a
brief review of the buck converter.
0
The buck converter is the most widely used t
DC/DC converter topology in point-of-load (POL) IL(A)

Topic 5
switching regulators. It is a simple and effective ΔIL = VL• Δt/L
mechanism to step down the input voltage to a
0
lower voltage level and to regulate the output t
voltage efficiently. Diagrams of the two buck
converter switching states in continuous conduction Figure 2 – Buck converter switching
mode are shown in Figure 1. A simplified switch waveforms depicting the switch node voltage
and the inductor current.

LOUT LOUT

COUT VOUT COUT VOUT

(a) (b)
Figure 1 – Buck converter switching states with (a) high-side switch on and (b) low-side switch on.

5-1
 II. Minimum On-Time Violation converter for simplicity. When there is no load, the
losses are low so this equation is an accurate
When designing a buck converter, selecting the
estimation for no load. When the output is loaded
switching frequency (fSW) is typically one of the
and there are more losses in the converter, the
first design choices to be made. The fSW is selected
on-time increases. The calculated on-time required
based on the input voltage, output voltage and other
for VIN = 12 V, VOUT = 1.2 V and fSW = 1.2 MHz is
specifications of the buck converter IC. Figure 3
83 ns. The estimated on-time is below the typical
shows an example VSW and VOUT ripple for a buck
90 ns minimum on-time for the converter [3].
converter in normal operation. The converter is
operating with the following conditions: VIN = 1 VOUT
tON = ⋅ (1)
11 V, VOUT = 1.2 V, IOUT = 0 A, fSW = 1.2 MHz and f SW VIN
forced continuous conduction mode (FCCM). In tON = 83 ns
Figure 4, VIN is increased to 12 V and the VOUT
The converter used in this example is a fixed
ripple increases. Why does the VOUT ripple
frequency converter. When the on-time required is
increase?
less than the minimum on-time, the converter
skips switching pulses to keep VOUT regulated.
SW (5 V/div) The converter outputs a series of 90 ns minimum
on-time pulses that charge VOUT above the target
regulated voltage. The control loop responds to
the overcharged VOUT with a skipped pulse to
VOUT (20 mV/div) regulate VOUT to the correct DC voltage. Other
converters may respond differently when the
minimum on-time is violated. For example, the
fSW may begin to decrease or VOUT may become
2 s/div
regulated to a higher voltage.
To avoid potential problems related to the
Figure 3 – 11 V input switching node and
minimum on-time, the switching frequency should
output voltage ripple waveforms.
be selected considering the maximum input
Topic 5

voltage and maximum minimum on-time listed in

SW (5 V/div) the datasheet. The maximum minimum on-time
should be used because the minimum on-time
typically varies with temperature, with output
current and between parts. Figure 5 shows an
example of how the minimum on-time can vary
with temperature and load [3]. Typically, a number
for the maximum minimum on-time is given in the
electrical specifications of the datasheet. Using
VOUT (20 mV/div) 2 s/div
this number is the most conservative approach.
After the maximum minimum on-time is
Figure 4 – 12 V input switching node and
found, Equation (2) can be used to calculate the
output voltage ripple waveforms.
maximum fSW. The part used in this example is
specified for a maximum minimum on-time of
The increased output voltage ripple in this
130 ns [3]. Using this with the VIN and VOUT in
waveform is a result of a violation of the minimum
this example, the fSW should be set below 769 kHz
on-time of the buck converter IC. Equation (1) is a
to always avoid pulse-skipping.
simple equation to estimate the on-time of the
converter. This equation ignores losses in the

5-2
 Figure 6 shows the thermal image of two different
converters both operating with the following
conditions: VIN = 12 V, VOUT = 1.8 V, IOUT = 8 A,
and fSW = 700 kHz. Part A has a case temperature TC
= 59.6 °C and Part B has TC = 82.4 °C. In addition to
a higher TC, the thermal image for Part B shows
higher PCB temperature and a larger thermal
footprint. Part B would have little thermal margin in
an application requiring operation up to an ambient
temperature of 85 °C. Which of these two parts are
rated for 8 A?
It turns out, both Part A and Part B are rated for
8 A! Table 1 gives a full comparison of the
specifications for these two parts. Part A and Part
Figure 5 – Example variation in minimum B have similar specifications except for one
on-time with temperature and load. important parameter; Part B is designed with
VOUT
higher RDS(ON) MOSFETs than Part A resulting in
1
f SW ≤ ⋅
tON ( MIN ) VIN ( MAX )
(2) more power dissipation in Part B. Higher RDS(ON)
MOSFETs can be advantageous in applications
Violation of the minimum on-time is not the where optimizing cost is more important than
only possible cause of increased output voltage optimizing efficiency.
ripple. For example, an unstable control loop or
poor PCB layout are other possible causes. Some Spec Part A Part B
of these different causes will be discussed in later (TPS54824) (TPS54821)
sections of this paper. VIN range 4.5 – 17 V 4.5 – 17 V
Current 8A 8A
Size 3.5 x 3.5 mm 3.5 x 3.5 mm
III. Thermal Derating RDS(ON) 14/6 mΩ 26/19 mΩ

Topic 5
Another important consideration when Modeled PLOSS 1.69 W 2.38 W
selecting a part for an application is thermal Simulated die 64 °C 81 °C
performance. It is best to keep the operating temp
temperature of the part as low as possible. In Price $$ $
extreme cases, high operating temperature may
Table 1 – Specification comparison between
cause a part to operate above its rated junction
Part A and Part B.
temperature and reach thermal shutdown. It can
also reduce the lifetime of an IC as higher
temperature accelerates failures.

TPS54824 TPS54821

Inductor
Inductor
Part B
Part A

Figure 6 – Thermal image for two parts operating in the same load conditions.

5-3
 Why is Part B rated for 8 A? Part B may be a
Inductor Current (1 A/div)
good choice for applications which do not require
operation in higher ambient temperatures. There
are also two possible application specific details
which allow Part B to better support an 8 A
application. 1 s/div
First, to reduce the operating temperature of
Part B, the power loss could be reduced by Figure 7 – Inductor current waveform
designing for a lower fSW. However lower fSW exhibiting saturation.
comes with a tradeoff of increased total solution
size and increased cost for external components. The inductor current waveform should look
Second, this example has only considered an similar to Figure 8. The inductor current should
application requiring the converter to operate at its have a constant slope during the switch intervals.
rated load of 8 A continuously for a period of time The inductor current waveform in Figure 7 exhibits
on a scale of seconds or longer. Many applications a peaking waveform. This indicates that the
do not require the part to operate at its full load inductor’s magnetic core is saturating. When the
continuously. The full load of 8 A may only be for core saturates, its permeability decreases
a short transient on the scale of milliseconds or significantly. The slope of the inductor current is
shorter. With a short transient, the die and package increasing within the switch interval because the
may thermally saturate but the PCB and ambient effective inductance of the inductor is decreasing.
air may not. In a case where the rated 8 A load is
only needed for a short period of time, Part B may
be sufficient. When evaluating the thermal
performance of a part, the effective average load
current should be considered.
TI’s WEBENCH® software is a useful tool to Inductor Current (1 A/div) 1 s/div
account for thermal performance while selecting a
part for an application. Table 1 includes rows for Figure 8 – Inductor current waveform
Topic 5

modeled PLOSS and simulated die temperature (non-saturating).

taken from WEBENCH. The modeled PLOSS
number comes from the efficiency model in Generally speaking, inductor saturation should
WEBENCH. The simulated die temperature is be avoided. It can cause damage to the converter,
from a WebTHERM™ simulation from within lead to premature overcurrent protection and limits
WEBENCH. The thermal simulation is based on the output current from the converter. The peaking
TI’s standard EVM so it is important to remember seen in Figure 7 can be observed in inductors
variations in the PCB layout affect the thermal made from a hard saturating magnetic material
performance. like ferrite and operated above their saturation
current limit. Other magnetic core materials that
offer soft saturating profiles can be more forgiving
IV. Poor Inductor Selection in these situations. It is also recommended to
Inductor selection is an important part of check how the inductor saturation profile changes
converter design. Inductors impact efficiency, with temperature and design for the worst case.
transient response and control loop stability. The Another undesirable situation that can occur is
image in Figure 7 shows what can happen when an shown in Figure 9. In this case, the converter is
improper inductor is selected. Can you see what is only running at 10% of its full rated load current
wrong with the inductor current waveform? yet the inductor is exhibiting a very large
temperature rise (about 30°C above ambient
temperature). What would cause the inductor to
get so hot?

5-4
 Typically, the inductance value is selected to
keep the current ripple between 15% and 40% of
the full load current level. For a converter with
Hot Inductor! 10% Load integrated MOSFETs, the inductance should be
selected using the rated IOUT of the converter. A
good starting point for inductor selection is 30%.
In the below Equation (4), the value for K would
IC
be 0.3 for this case.
⎛ VIN(MAX) − VOUT ⎞ ⎛ VOUT ⎞
L=⎜ ⎟⎜ ⎟
(4)
⎝ K ⋅ IOUT ⎠ ⎝ VIN(MAX) ⋅ f SW ⎠

Figure 9 – High inductor temperature rise despite There is some flexibility when it comes to
operating at 10% rated load current. inductance selection. The efficiency graph of a
converter can be shaped based on the inductance
The inductor in Figure 9 is hot because there is selected as shown in Figure 11. Assuming the
a large amount of core loss. This happens because same physical size inductors, higher inductance
the inductance value selected is too low. With a tends to increase peak efficiency. This is because
low inductance value selected, very large peak-to- there is less current ripple, core loss and RMS
peak inductor current ripple (ΔIL) results. Large current. The tradeoff is that it increases inductor
current ripple can lead to excessive core loss. A DC resistance (DCR) and tends to slow the
simplified Equation (3) for estimating core loss is transient response. Lower inductance values tend
to result in higher full load efficiency due to lower
2
PCORE ≈ k0 f SW BPK ∝ k0 f SW ΔI L2 (3) DCR and have faster inductor current slew rates.
90
where k0 is a material constant and BPK is peak
flux swing. Core loss increases approximately
Efficiency (%)

quadratically with increases in inductor current

Topic 5
ripple. A good design is shown in Figure 10. In
85
this case, the current ripple is 30% of the full load
current unlike the previous case where the ripple L = 0.68 H (40% Ripple)

was over 100% of the full load current. L = 1.5 H (18% Ripple)
L = 2.2 H (12% Ripple)

80
0 2 4 6 8
Load Current (A)
Inductor
Figure 11 – Efficiency comparison of a converter
designed with three different inductor values with
the same physical size.
IC

Good Design
Figure 10 – A well designed converter where the
inductor temperature is low at 10% load.

5-5
 V. Insufficient Capacitance This situation often arises when testing
converter evaluation modules (EVMs). If the input
Mistakes in capacitor selection can cause
supply to the converter is not properly bypassed
problems. For example, observe the output voltage
with input capacitance or there are long bench
ripple shown in Figure 12. The output voltage
power supply leads, the input disturbances like
measurement shows the converter’s response to a
those shown in Figure 13 can result in incorrect
large load step increase. As expected, the output
inferences about the performance of the device
voltage initially drops but quickly recovers. The
under test. One possible solution is to connect a
potentially undesirable aspect of Figure 12 is the
bulk input decoupling capacitor to the input of the
oscillations on the output voltage after the
EVM to avoid the perturbations. The response to
transient. Sometimes these oscillations are
the load step with a bulk decoupling capacitor is
interpreted as low phase margin in the control
shown in Figure 14. In this case, the response to
loop. What is the real cause of these oscillations?
the load transient is clean without any oscillations
on the input or output of the converter.

VIN (500 mV/div, 8 V Offset)

VOUT (20 mV/div, AC-Coupled)

VOUT (20 mV/div)

10 s/div
4 s/div
Figure 12 – Output voltage oscillation
after a load step-up.
Figure 14 – Input voltage perturbations
Topic 5

are eliminated with sufficient input

Figure 13 shows why the oscillations are
decoupling capacitance.
occurring. The converter’s input voltage has large
variations due to the load step (on the order of
Another problem that can occur with
hundreds of mV). For the most part, the converter
insufficient input decoupling is shown in Figure
rejects these input perturbations and only disturbs
15. In this situation, the converter is running close
the output by a few mV.
to its minimum input voltage when a load step-up
occurs. The input voltage waveform is similar to
VIN (500 mV/div, 8 V Offset) the waveform show in Figure 13 except it occurs
at a lower DC voltage. After the load step-up, the
input voltage dips below the input undervoltage
lockout (UVLO) level which results in the
VOUT (20 mV/div) converter turning off. The output voltage collapses
due to the perturbation on the input voltage. Once
the input voltage recovers, the converter restarts
and the output comes back in to regulation.

4 s/div

Figure 13 – Input voltage perturbations

are impacting the output voltage.

5-6
 ESR Zero

VOUT (500 mV/div, AC-Coupled)

PM >60°
PM <30°

100 s/div

Figure 15 – Input voltage dips below the Figure 16 – Replacing a ceramic output
undervoltage lockout threshold during a capacitor with a high ESR capacitor can
load step-up and causes the converter unexpectedly lead to low phase margin (PM).
to shut down and then restart.

There are several design guidelines to consider VI. Poor Control Loop
for input and output capacitors. You must ensure Compensation
sufficient input and output decoupling capacitance; After the key power components are selected
design equations located in the applications section for the converter, it is important that the control
of a converter datasheet can help. Typically, the loop is properly compensated. Figure 17 shows
“worst case” scenario to be designed for is large the switching node of a converter operating with
load transients. Capacitance also impacts steady VIN = 17 V and VOUT = 1.8 V. The switching node
state ripple and control loop bandwidth [7][8]. shows alternating narrow and wide pulses. What
It is important that parasitic resistance and causes this behavior?
inductance of capacitors is taken into account. For

Topic 5
example, do not design a converter with a low
equivalent series resistance (ESR) ceramic output
capacitor and later replace it with a (potentially
Narrow Wide Narrow
cheaper) high ESR capacitor. This can cause low
phase margin and potential instability as shown in
Figure 16. This simulation had a fixed output
capacitance and the ESR was varied from 3 mΩ to
30 mΩ. Many capacitor’s ESR can also change
dramatically with temperature and change the SW (5 V/div)
control loop dynamics. For example, an aluminum 400 ns/div
electrolytic capacitor can exhibit the same 10x
increase in ESR from room temperature to cold Figure 17 – Switching node of converter
temperature as simulated in Figure 16. It is also with wide and narrow pulses.
recommended to estimate the RMS current of the
capacitor and check to see what the temperature This behavior appears to be subharmonic
rise due to self-heating will be. oscillations that can occur with the peak current
mode control converter at >50% duty-cycle if
there is insufficient slope compensation [4]. This
waveform was taken with a peak current mode

5-7
 control converter but the duty-cycle is only 11%. considered, the margin of a nominal circuit may
With a duty-cycle <50%, insufficient slope need to be higher to always meet these
compensation is not the cause. The cause instead recommended minimum values. For example, a
is a poorly compensated design that has too little more conservative design target of 60° phase
gain margin. The measured loop Bode plot is margin and -16 dB gain margin may be used. The
shown in Figure 18 and the gain margin is less amount of added margin depends on the
than 5 dB. characteristics of the components and the range of
operating conditions in an application.

Low
Gain
Margin
Better
Gain
Margin

Figure 18 – Bode plot of converter

with low gain margin.
Figure 20 – Bode plot of the converter
To improve the gain margin, the compensation with good gain margin.
was modified to remove a zero previously in the
loop near 100 kHz. Removing this zero reduces Sometimes even if a converter is designed
the high frequency gain but comes with a tradeoff with sufficient margin on paper, it may be unstable
of reduced phase. Figure 19 shows the resulting in the final application. Figure 21 shows a
switching node and Figure 20 shows the Bode simulated Bode plot for a circuit after the initial
plot. The switching node is stable, the gain margin calculation of the compensation values. It shows
Topic 5

is improved to 13 dB and the phase margin is sufficient phase margin of 60° and gain margin of
sufficient at 55°. -16.7 dB. However, when the circuit was built and
tested in the final application, the output voltage
had an oscillation at 40 kHz as shown in Figure
SW (5 V/div) 22. Why does the output oscillate even when the
simulation shows sufficient margins?

400 ns/div

Figure 19 – Switching node of converter

with good gain margin.

For a stable control loop, the typically

recommended design goals are to have a minimum
phase margin of 45° and gain margin of -10 dB Figure 21 – Simulated Bode plot of a
[5]. When variations between components and converter with good phase and gain margin.
variations across operating conditions are

5-8
 ~40 kHz Oscillation

VOUT (200 mV/div)

SW (2 V/div)

20 s/div

Figure 22 – Output voltage oscillation.

After a review of the circuit schematic that

was built and tested, it was found that a second
stage LC filter was used in the design but was not
included in the compensation calculations or the Figure 24 – Expected Bode plot vs. actual
initial simulation. The second stage was created Bode plot with second stage LC filter.
with a ferrite bead in the output filter as shown in
Figure 23. Figure 24 shows the simulated Bode stabilize the loop specific example, it is
plot when the entire output filter is included. This recommended to adjust the compensation so that
second stage adds a double pole that causes a the crossover frequency is less than 1/3rd the LC
-180° drop in phase and peaking in the gain at the resonance frequency [5]. If the quality factor (Q
LC resonance frequency. This results in the phase factor) of the second stage is relatively high, it
dropping below 0° before the 0 dB gain crossover may require a lower crossover frequency to
frequency. The loop is unstable so the output increase the gain margin or some damping
oscillates. resistance may be needed to reduce the Q factor.
When selecting compensation, it is important This example has a second stage created by a

Topic 5
to make sure the entire output filter is included. In ferrite bead in the output filter. However, if the
addition to any second stage filtering, all load is located relatively far from the POL
capacitance connected to the output voltage on the converter, a second stage could also be created by
entire board must be included, not only the parasitic PCB inductance. The further away the
capacitance in this local to the POL converter. To load is from the POL converter, the more the
parasitic PCB inductance.

FERRITE
VIN BEAD VOUT
VIN SW

LOAD

GND
FB

COMP

Figure 23 – Simplified schematic of circuit tested.

5-9
 VII. Wrong Soft Start Time
You may come across a case where a DC/DC DC/DC
converter does not start up. A situation like what is Converter
shown in Figure 25 could be happening. The
output voltage starts to increase but then the
converter stops suddenly. The converter then tries Figure 26 – A converter charges the output
to start again after waiting some time. In this capacitors and provides any load current
example, the overcurrent protection was triggered demand during start up.
during start up. This can be caused by large output
capacitance, a heavy load during start up and/or a The following Equation (5) can be used to
short circuited output. Many converters have a estimate the current used to charge the output
“hiccup” auto restart feature where the converter capacitance during start up.
continually attempts to restart. This is the behavior
being exhibited in Figure 25. ΔV
IC = C (5)
ΔT
VOUT (500 mV/div) where C is the output capacitance, ΔV is the
change in output voltage, ΔT is the soft start time
and IC is the DC current flowing into the capacitor.
This equation assumes a straight line start up
waveform which is a fairly good approximation of
most start up profiles. A diagram showing the
output voltage profile during start up is shown in
Figure 27.
IL (5 A/div)
5 ms/div
VOUT TSS
Figure 25 – A converter keeps hitting its
overcurrent limit when attempting to start up. VOUT
Topic 5

One way to avoid this situation is to have an

appropriate start up time. Most converters have
programmable soft start times. If the soft start time Figure 27 – Converter output voltage
is too fast, the input voltage can sag, overcurrent rise during soft start.
protection can be tripped or the input bus converter
can hit its current limit. An appropriate soft start The output current from the converter supplies
time avoids these issues and reduces inrush the capacitor charging current as well as any load
current. current. Therefore, the converter output current
Some simple equations can be used to estimate during start up is
converter input and output current during soft (6)
I L = I LOAD + IC
start. If either input or output current is too high,
increase the soft start time. During soft start, the where IL is the converter output current and ILOAD
converter needs to charge the output capacitance is the load current during start up. Take care to
and bring the output voltage up to the target ensure the converter output current stays well
regulation voltage. The converter also needs to below the overcurrent protection threshold during
supply any current the load is demanding. This is start up.
depicted in Figure 26. The following Equation (7) can be used to
estimate converter input current in a buck converter

I IN ≈ D( I LOAD + IC ) (7)

5-10
where D is the duty ratio. For a buck converter, the If input decoupling capacitors are placed right
duty ratio is VOUT/VIN. If many converters are next to the converter, the switch node ringing is
supplied from the same intermediate bus, the reduced. An example placement is shown in Figure
current demand on the bus converter can be large 30. A 10 µF, 1206 size capacitor and a 0.1 µF,
if they all start up simultaneously. A technique 0603 size capacitor are connected in parallel and
commonly used to address this issue is to sequence adjacent to the converter input.
the start up intervals of the converters. This spreads
out the current demanded on the bus converter and
avoids hitting its current limit.

VIII. Poor PCB Component

Placement
Switching power converters are fairly easy to Figure 30 – Converter layout with two input
lay out on a printed circuit board (PCB). Sometimes capacitors populated right next to the IC.
simple layout mistakes can cause big problems,
however. For example, consider the converter The switch node waveform with this input
design shown in Figure 28. capacitor placement is shown in Figure 31. As you
can see, the switch node rings to about 5 V greater
than the input voltage. This is a significant reduction
from the previous layout because there is less
parasitic inductance in series with the input
capacitors.
50 ns/div

Figure 28 – Converter layout with no nearby ~5 V

input decoupling capacitor populated.

Topic 5
Because there are no input decoupling
capacitors anywhere near the VIN and GND SW (5 V/div)
terminals of the converter, the switch node of the
converter exhibits large ringing, as shown in
Figure 29. The switch node rings to about 10 V
higher than the input voltage. This can cause Figure 31 – Switch node waveform with two
additional stress to the converter, increase power input capacitors populated right next to the IC.
loss, increase EMI and potentially damage the
power MOSFETs and other internal circuitry. A third layout is shown in Figure 32. In this case,
input capacitors are populated on both sides of the
50 ns/div IC. This converter has VIN and GND pins on both
~10 V sides of the IC which enables this layout approach
[3].

SW (5 V/div)

Figure 29 – Switch node waveform with no Figure 32 – Converter layout with two input
nearby input decoupling capacitor populated. capacitors populated on each side next to the IC.

5-11
 The switch node waveform associated with IX. Poor Thermal Design
this layout is shown in Figure 33. The switch node
PCB layout is important not only for electrical
ringing is reduced to approximately 2 V higher
performance but also thermal performance.
than the input voltage. This reduced ringing is due
Besides IC specific parameters, PCB layout is a
to effective input decoupling capacitor placement
very important, if not the most important, variable
that limits parasitic inductance.
in a design affecting the thermal performance of
50 ns/div an IC. The PCB layout is important because it is a
strong determining factor for the junction to
~2 V ambient thermal resistance of the IC. As mentioned
in Section III, thermal performance matters
because poor layout can result in a part not working
as expected in an application or it can reduce the
SW (5 V/div) lifetime of the IC.
Figure 35 shows the thermal images of the
same part with two different PCB layouts. The
thermal image for both the top-side and bottom-
Figure 33 – Switch node waveform with two input
side are shown. Both boards are 2-layer boards
capacitors populated on each side next to the IC.
with 2 ounce copper. On Board A the IC
temperature is 86 °C and the maximum temperature
There are several general guidelines to follow
on the bottom layer is 62.6 °C. On Board B the IC
with a converter layout. It is important to minimize
temperature is 66 °C and the maximum temperature
the switching loop area. This is highlighted in the
on the bottom layer is 52.2 °C. Why is the operating
pink box in Figure 34. A tight layout reduces
temperature of the IC higher on Board A?
parasitic elements, improves efficiency and limits
the noise disturbances’ impact on the system.
Special care should be taken to optimize current
return paths through the ground plane. Make these
returns as short and wide as possible. Avoid having
Topic 5

a large switch node to reduce EMI. Keep sensitive

analog pins/traces like feedback and compensation
away from noisy switching pins/traces like the
switch node or bootstrap capacitor. A snubber
circuit or a boot resistor can be added to slow
down the switch node slew rate but these
approaches tend to increase power loss [9][10].
L OUT VOUT
Figure 35– Thermal images of
two different PCBs.
CIN COUT RLOAD
+
VIN
–
The IC operates at a higher temperature on
Board A because of a horizontal trace cutting
through the bottom-layer of the PCB. This is the
L OUT VOUT only difference between Board A and Board B.
This trace reduces how effectively the heat spreads
+
COUT RLOAD across the entire bottom layer. Because of this
VIN CIN
trace affecting the thermal performance, this trace
–

is visible in the thermal image of the bottom layer

of Board A.
Figure 34 – Understand current flows (red and blue
lines) and minimize the switching loop area (pink box).

5-12
 When laying out the PCB, thermal dissipation
should be kept in mind. Figure 36 illustrates how
heat transfers from the IC into the PCB and the
ambient air. Transferring heat from the IC into the
PCB is typically the most effective way to get heat
out of the IC, however some heat will also transfer
to the ambient air through the top of the IC. There
are multiple standard thermal parameters which
quantify how effective each path is at getting heat
out of the IC. For more details, see reference [6].
To maximize thermal dissipation in the layout Figure 37 – Example thermal pad package PCB
it is important to minimize cuts in the copper footprint with a recommended via pattern.
planes and to allow the heat to effectively spread
laterally across the board. Copper planes of the
PCB provide the lowest thermal resistance to X. Poor Voltage Measurement
spread the heat throughout the PCB, so cuts in the After you have built your converter, it comes
copper planes will increase the thermal resistance. time to test its performance. One common
The ground plane is typically used for spreading waveform to measure is the output voltage ripple.
the heat because this is typically the largest copper If care is not taken with this measurement, it is
area in a PCB layout. Thermal vias should be used easy to get erroneous results. This is especially
and placed to spread heat vertically in the PCB to important when millivolts matter in low output
other layers. The bottom and top layers of the PCB voltage applications. See Figure 38, for example.
are important for thermal dissipation because this
is where the heat transfers from the PCB to the VOUT (20 mV/div, AC-Coupled)
ambient air [10].

Topic 5
SW (10 V/div)

1 s/div

Figure 36 – Example heat transfer paths Figure 38 – Noisy output voltage measurement.
from the IC to the PCB to the ambient air.
The output voltage waveform in Figure 38 is
ICs with thermal pads can more effectively AC-coupled and zoomed in at an appropriate
transfer heat from the IC into the PCB in scale. This is good. However, the waveform
comparison to a part without a thermal pad, in measurement is not clean. Switching noise is
general. To maximize the heat transfer, vias should being picked up from the switch node measurement
be placed in the thermal pad’s PCB footprint to on channel 2. There also is no bandwidth limit set
provide a path for the heat to conduct vertically to on the output voltage measurement. Limiting the
other layers. A recommended via pattern, like bandwidth to 20 MHz helps to focus on the lower
what is shown in Figure 37, can be found in the frequency output voltage ripple and not on higher
PCB footprint recommendation at the end of each frequency radiated noise that is being picked up.
datasheet. Compare Figure 38 to a clean output measurement
shown in Figure 39.

5-13
 V (10 mV/div, AC-Coupled)
OUT
XI. Poor Bode Plot Measurement
Evaluating the stability of a POL converter is
an important part of validating a design. To
evaluate the stability, the Bode plot can be
measured by injecting a signal into the control
loop between VOUT and the top feedback resistor
as shown in Figure 41. Practically this is done by
adding a 10 to 50 Ω resistor into the feedback path
then injecting a signal across this resistor using a
1 s/div transformer.

Figure 39 – Clean output voltage measurement.

In Figure 39, a more accurate output voltage

measurement is observed. The output ripple due to
the output capacitors and their parasitic elements
(ESR and ESL) is clearly visible. The Y-axis scale
is zoomed in to its maximum of 10 mV/div. The
20 MHz bandwidth filtering is active which helps
to remove unrelated noise. The switch node
Figure 41 – Simplified schematic
measurement has also been removed as it is not
for Bode plot measurements.
needed.
There are a few recommendations to follow
There are some mistakes that can be made
when probing key voltage waveforms. Measure the
when taking the measurement that result in an
output voltage directly across the output capacitor.
inaccurate measurement. Figure 42 shows a loop
Consider using a “tip and barrel” approach shown in
measurement where the Bode plot is not smooth
Figure 40 instead of having a flying ground lead.
from about 50 kHz and higher. What can cause
Topic 5

This will reduce the amount of radiated noise picked

this?
up (the flying ground lead acts like an antenna).
There are also other techniques using probe sockets
that may be useful to reduce the measurement loop
area. Limiting the scope probe bandwidth to 20 MHz
helps to focus the time domain measurement. Set the
Y-axis scale to take up as much of the oscilloscope
viewing area as possible. Using 1:1 passive probes or
active probes may also be useful [11]. They enable
sub-10 mV range measurements with an oscilloscope.

Figure 42 – Bode plot with poor

measurement for high frequencies.

Figure 40 – Try using a “tip and barrel”

approach instead of a flying ground lead
when taking output voltage measurements.

5-14
 For this measurement, the signal injected into For this measurement, the amplitude of the
the loop was too large. This caused some large signal injected into the loop was too small. The
signal characteristics of the IC to affect the control equipment used to measure the loop is unable to
loop. Figure 43 shows the switching node and get an accurate measurement at lower frequencies
output voltage of the converter with a 100 kHz because the signal-to-noise ratio was too low. A
signal injected into the loop. This signal is the larger amplitude signal is typically needed at
same amplitude as the one used to measure the frequencies below the crossover frequency
Bode plot in Figure 42. Injecting too large of a because the loop will attenuate the injected signal.
signal caused the converter to skip pulses at the Alternatively, equipment used to take frequency
switching node. When the converter skips pulses, response measurements usually have settings that
the loop measurement is no longer valid because it can be adjusted to filter out some of the noise. For
is no longer a small signal measurement. Generally, example, some equipment can increase the
a POL converter will be sensitive to too large of integration time or decrease the IF filter bandwidth.
signal injection at frequencies above the crossover Figure 45 shows a loop measurement where
frequency because the loop does not attenuate the more optimal signal injection amplitude was used
signal amplitude. across the entire frequency range giving a smooth
Bode plot. For this measurement, the signal
VOUT
injection amplitude was varied versus frequency.
Larger amplitude was used below the crossover
frequency and smaller amplitude was used above
VOUT (20 mV/div) the crossover frequency. Monitoring the waveform
at the output and at the switching node can aid in
optimizing the signal injection amplitude. Figure
46 shows the switching node and output voltage
with good signal injection amplitude. The
switching node is regular and the output voltage
SW (5 V/div) 4 s/div has visible ripple at the injection frequency.

Topic 5
Figure 43 – Converter pulse-skipping
due to too large signal injection.

Figure 44 shows a loop measurement where

the Bode plot is not smooth for frequencies less
than 10 kHz. What can cause this?

Figure 45 – Bode plot with proper

measurement for low frequencies.

Figure 44 – Bode plot with poor

measurement for low frequencies.

5-15
 3. Texas Instruments, “TPS54424 4.5-V to 17-V
VOUT (AC) Input, 4-A Synchronous SWIFT™ Step-
VOUT (20 mV/div) Down Converter with Current Mode Control,”
Data Sheet, July 2017. Available: http://
www.ti.com/lit/ds/symlink/tps54424.pdf.
SW (5 V/div) 4. Texas Instruments, “Modelling, Analysis and
Compensation of the Current-Mode
Converter,” Application Report, 1999.
Available: http://www.ti.com/lit/an/slua101/
slua101.pdf.
5. Sheehan, R. and Diana, L., “Switch-mode
4 s/div power converter compensation made easy,”
Texas Instruments Power Supply Design
Seminar SEM2200, 2016.
Figure 46 – Converter output voltage and
6. Edwards, Darvin and Nguyen, Hiep,
switching node with optimal signal injection.
“Semiconductor and IC Package Thermal
Metrics,” Texas Instruments Application
XII. Summary Report, April 2016.
7. Texas Instruments, “Input and output
When designing a POL regulator, there are capacitor considerations in a synchronous
multiple stages in the design where a mistake may buck converter,” E2ETM Community Blog,
be made. These mistakes can occur when selecting Nov. 18, 2016. Available: https://e2e.ti.com/
the regulator, selecting the external components blogs_/b/powerhouse/archive/2016/11/18/
around the regulator, designing the PCB layout input-and-outputcapacitor-considerations-in-
and testing the final design. This paper covered a-synchronousbuck-converter.
ten common mistakes we have seen made
8. Score, Michael, “Ceramic or electrolytic
throughout the entire design process. The cause of
output capacitors in DC/DC converters —
each mistake was explained along with how to fix
Why not both?,” Texas Instruments Analog
Topic 5

them. This paper can be used to learn from others’

Applications Journal, 3Q 2015. Available:
mistakes so that you can avoid making them. It
http://www.ti.com/lit/an/slyt639/slyt639.pdf.
can also be used as a reference to aid in debugging
an issue you are currently having with a regulator. 9. Glaser, Chris, “Five steps to a great PCB
The cause of the problem may not be exactly the layout for a step-down converter,” Texas
same as shown in this paper but these examples Instruments Analog Applications Journal, 1Q
can be useful to brainstorm possible causes. 2015. Available: http://www.ti.com/lit/an/
slyt614/slyt614.pdf.
References 10. Kollman, Robert, “Constructing Your Power
Supply — Layout Considerations,” Texas
1. Lynch, B., and Hesse, K., “Under the Hood of Instruments Power Supply Design Seminar,
Low-Voltage DC/DC Converters,” Texas 2004. Available: http://www.ti.com/lit/
Instruments Power Supply Design Seminar slup230.
SEM1500, 2002.
11. Texas Instruments, “Understanding,
2. Shenoy, P.S., “Introduction to the Series Measuring, and Reducing Output Voltage
Capacitor Buck Converter,” Texas Instruments Ripple,” E2ETM Community Blog, Dec. 14,
Application Report, Revised May 2016. 2012. Available: https://e2e.ti.com/support/
Available: http://www.ti.com/lit/an/ power_management/simple_switcher/w/
slva750a/slva750a.pdf. simple_switcher_wiki/2243.understanding-
measuring-and-reducing-output-voltage-
ripple.

5-16
TI Worldwide Technical Support

TI Support
Thank you for your business. Find the answer to your support need or get in
touch with our support center at
www.ti.com/support
China: http://www.ti.com.cn/guidedsupport/cn/docs/supporthome.tsp
Japan: http://www.tij.co.jp/guidedsupport/jp/docs/supporthome.tsp

Technical support forums

Search through millions of technical questions and answers at TI’s E2E™
Community (engineer-to-engineer) at
e2e.ti.com
China: http://www.deyisupport.com/
Japan: http://e2e.ti.com/group/jp/

TI Training
From technology fundamentals to advanced implementation, we offer
on-demand and live training to help bring your next-generation designs to life.
Get started now at
training.ti.com
China: http://www.ti.com.cn/general/cn/docs/gencontent.tsp?contentId=71968
Japan: https://training.ti.com/jp

Important Notice: The products and services of Texas Instruments Incorporated and its
subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale.
Customers are advised to obtain the most current and complete information about TI products and
services before placing orders. TI assumes no liability for applications assistance, customer’s
applications or product designs, software performance, or infringement of patents. The publication
of information regarding any other company’s products or services does not constitute TI’s approval,
warranty or endorsement thereof.

A011617

The platform bar and E2E are trademarks of Texas Instruments. All other trademarks
are the property of their respective owners.

SLUP384
 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your non-
compliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated