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1/11
 Digital backend: the role and creation of track
m0_46291770: Thanks to the host, can you also tell me about the knowledge about
color track?

Static timing analysis—set_sense

endure10086: Well written, I have been looking for this command for a long time,
and finally found it here, thanks for sharing

Redhawk APL - DI Flow

Dreams, everything! : Blogger, hello, I can’t find the corresponding cell displayed on
subckt, but I have this file, and there is indeed a fragrant leaf cell in it, I have tried
both the absolute path and the relative path

ICC2 user guide (1) Preparing the Design

Shilulou: user guide, not lab

ICC2 user guide (1) Preparing the Design

weixin_46209586: Which lab does this correspond to?

latest articles

102 articles in 2022

ICC2
focus on

Number of followers: 51
Number of articles: 38
Number of articles read: 34696 Number
of articles collected: 451

Author:
Shilulou

The official account is continuously updated. . .

stop pin/ignore pin/exclude pin/float pin

The difference between stop pin, ignore pin, exclude pin and float pin

original
2022-12-22 13:41:06 · 422 reads · 0 comments  

2/11
CTS Debug
1.Transition Violation1) The constraints are too tight, especially the transition of
some pins in the .lib is relatively large. 2) There is a placement blockage or hard
macro blocking the buffer and the transition cannot be inserted. 3) The clock cell
has don't touch or fixed attributes, resulting in Unable to upsize4) Winding detour
due to blockage and other reasons, or clock winding level is set too low 5) Fanout is
too large 2. Latency Violation1) Too tight M

original
2022-12-19 15:19:28 · 353 reads · 0 comments  

Digital backend: the role and creation of track

1. Definition of track The EDA tool automatically generates a continuous and regular
routing track (routing track) for each layer of metal inside the chip according to the
pitch size of each layer of metal in the LEF (or tech file). The routing track refers to
the winding path of. tech lef example tech file example TRACK information stored in
DEF is as follows: TRACKS Y 9000 DO 187 STEP 9000 LAYER M5Y: direction of
TRACK 9000: starting position of TRACK DO: number of TRACK STE

original
2022-12-07 16:03:49 · 574 reading · 1 comment  

ICC2: The role and connection of secondary pg pin

1. The role of secondary pg pin 1) As a backup power supply (backup power), when
the main power supply (primary power) is powered off, the standard cell can still
maintain normal operation or at least keep the output unchanged, such as always on
buf and retention reg. 2) As a bias well potential (bias pin), it is connected to a
different power supply from the source and drain of the MOS tube. For example, in
a power domain that can be turned off, it is required that the well potential is always
in an always on state relative to the power supply. In this way The power-on and
power-off of the standard cell will not be affected, which is common in cells with b

original
2022-12-01 14:22:01 · 489 reads · 0 comments  

ICC2: Design Planning (03) Power Network Synthesis

After the shape block, pg planning can be done next. Power network creation can be
divided into the following parts: 1. Add Power Pad Before planning the power mesh,
you need to insert the power pad first, so you need to load upf in the create abstract
stage. If there is no power pad when planning the power mesh, you also need to set
up a virtual one. power pad, the place of power pad uses the place_io command like
signal IO. 1.1 Setting Power I/O Constrai

original
2022-11-29 16:19:58 · 253 reads · 0 comments  

3/11
ICC2: Design Planning (02) Shaping Placement
ICC2: Design Planning (02) Shaping Placement

original
2022-11-11 11:05:16 · 346 reads · 0 comments  

ICC2: Design Planning (01) initial_DP

1. Create Design Library The files needed for create_lib include reference library
(.ndm), Technology File (.tf), and parasitic parameter extraction rule file (.tluplus).
tech file and tluplus file can use library manager tool to generate tech_lib.ndm. 1.1
Use tech file && tluplus create_libcreate_lib -tech tech.tf -ref_lib "xx.ndm

original
2022-10-28 16:46:19 · 686 reads · 0 comments  

ICC2: technology lib

The Library Manager command is as follows: icc2_lm_shell -f
tech_only_library.tclcreate The reference script of tech-only library is as follows: ##
tech_only_library.tclcreate_workspace tech -tech tech.tfcreate_parasitic_tech -tlup
cmax.tlup -layermap layer.map -name Cmaxcreate_parasitic_tech -t

original
2022-10-28 10:00:49 · 330 reads · 0 comments  

ICC2: ETM (extract timing model)

ICC2 needs block-level ndm for top-level PR work. ICC2 can directly call PT extract
model to generate ndm for a specified block. The process is as follows. 1) Before
create_frameextract model, a frame view needs to be generated for the specified
block. 2) Environment settings set_scnario_status -active true -leakage_power true
-dynamic_power true [all_scenarios] set_app_options -n

original
2022-10-19 16:08:35 · 379 reads · 0 comments  

ICC2: clock balance group

The tool will automatically balance the clocks of a clock group according to the
definition of sdc, but the tool also provides commands to allow users to customize
the balance group. ICC2:create_clock_balance_group -name group1 -objects {clk1
clk2} -offset_latencis {0 -100} The tool defaults to the clock in the group, and the
tool also supports offset_latencies to specify the relative length. INNOVUS:
create_ccopt_skew_group

original
2022-09-30 11:16:38 · 152 reads · 0 comments  

4/11
formality: Formal verification process
The formality tool is used to verify whether the logic function has changed during
the design and development process, regardless of layout and timing, and can be
used as a substitute for dynamic simulation. Restricted by the design scale, the
simulation time is related to the number of input vectors, while formal verification
does not require input vectors. 1. After synthesizing the usage scenarios of formality:
compare the rtl netlist with the gate-level netlist, and compare before and after
inserting the dft. After back-end design: Use the integrated netlist to compare with
the netlist after back-end layout and routing, and compare before and after eco.
There are two concepts here, reference design and implement design, the former as

original
2022-09-27 14:35:44 · 1013 reading · 0 comment  

ICC2: placement stage early clock tree synthesis

Now PR tools support trial clock in the place stage. Compared with the original ideal
clock for place, the place of trial clock results in a more reasonable clock cell
position, and in most cases, the timing is improved. ICC2 supports the optimization
of icg in the setting of the trial clock. The tool automatically finds a suitable position
for the icg that caused the timing violation and its fanout cells. If there are too many
or too scattered fanouts, ICC2 also supports automatic splitting of icg. In this way,
to solve a problem that icg is too busy, all this requires only one command.
set_app_opt

original
2022-09-19 11:04:17 · 180 reads · 0 comments  

ICC2: keepout, spacing_rules, clock_cell_spacing

There are three commonly used spacing physical constraints ICC2, the first
create_keepout_margin, the second set_placement_spacing_rule, and the third
set_clock_cell_spacing1.create_keepout_margin There are two commonly used
scenarios, one is to add hard attribute keepout to hard macro (sram IP), and the
other is multiple The pin is easy to cause the cell with too high pin density (*AOI*
*OAI*, etc.). create_keepout_margin -outer { 0.1

original
2022-09-06 09:52:00 · 230 reads · 0 comments  

5/11
ICC2: parallel punch create_pg_stapling_vias
The power rail (follow pin) is not always the same as metal1. When you need to use
metal2 for power rail, but the pg pin of the standard cell is still metal1, you need to
punch holes in parallel, from metal2 to metal1. In the past, create_pg_vias -
allow_parallel_objects was used to do this, but there are two disadvantages in this
way. One is to capture all via12 (including those inside the standard cell and those
generated by the pin winding), and add routing blockage to prevent when creating
pg via generate d

original
2022-08-17 09:07:53 · 172 reads · 0 comments  

ICC2: derive_preferred_macro_locations
When using create_placement -floorplan to do auto floorplan, some hard macro
locations are determined in advance and can be set as fixed attributes, or you can
use derive_preferred_macro_locations to record the location of the specified hard
macro priority place. The example is as follows: set macro [get_cells
xx]derive_preferred_macro_locations $macro -file preferred.tcl #Open
preferred.tcl, yes

original
2022-09-05 11:40:57 · 81 reads · 0 comments  

ICC2: macro-only placement

Both ICC and INNOVUS have the function of auto floorplan. The general method is
to set the IP IO sram that can determine the specific location first, and then use the
auto floorplan function to let the tool automatically place the floorplan. The
placement of the tool is from the module distribution. From the looks of it, it has a
certain reference value. ICC2 supports create_placement to only place hard macros.
The specific command is as follows: set_app_option -name
plan.macro.macro_place_only -value truecreate_placemen

original
2022-09-05 11:17:46 · 171 reads · 0 comments  

ICC2: Channel automatically adds soft blk method

After the floorplan, soft placement blockage needs to be added to the channel
(between the hard macro and the hard macro or between the block boundary). The
traditional method is to add it manually or reset_placement after create_placement.
In fact, the tool gives smarter and faster commands, derive_placement_blockages
First, you need to constrain the channel width and give a width threshold.
set_app_options -name place.floorplan.sliver

original
2022-09-05 11:12:40 · 183 reads · 0 comments  

6/11
ICC2: Application of change_link
When the ndm is updated, the number of hard macro pins or the names are not
correct. At this time, the hard macro cannot participate in create_placement or
place_opt, and the Error is as follows. Error: The cell xx does not have any
boundary. (DPUI-057) The chang_link command needs to be used at this time.
Example: To change the power pin name of a hard macro from VDD to VDDP, first
we need to disconnect the deleted pin. set cell xxdiscon

original
2022-09-05 11:07:04 · 146 reads · 0 comments  

ICC2: Use global route to analyze winding

If the analysis and winding follow the complete process, the larger the project, the
longer the time-consuming. Therefore, generally after the placement, the winding is
performed to estimate the subsequent winding results. If this is slow, you can use
the global route congestion map to analyze. route_global -floorplan true -
congestion_map_only true -virtual_flat all_routing and then open Global Route
CongestionView->Map>Global Route Congestion through the graphical interface

original
2022-09-05 11:03:35 · 206 reads · 0 comments  

End of line spacing

Both end of line spacing and diff net via_cut spacing represent a type of DRC
problem, and the specific spacing requirements are determined according to the
relevant constraints of the tech file. The end of line spacing refers to the spacing
requirements between the end of line edge and the adjacent metal of the same layer,
where the end of line edge is defined as the end of line edge when the common side
width of two adjacent convex corners is less than the threshold, As shown in the
figure below, the metal wire where the end of line edge is located is called the end of
line wire.

original
2022-08-31 10:20:19 · 216 reads · 0 comments  

Static timing analysis - pessimistic path removal (CRPR:

Clock Reconvergence Pessimism Removal)
When doing timing analysis, the launch clock path and the capture clock path have a
common path (common path). If the ocv analysis mode is used, the cells on the
common path will have different delay values. In order to eliminate this pessimistic
situation, the eda tool Introduce crpr (clock reconvergence pessimism removal), also
called cppr (clock pathpessimism removal), to smooth out the differences on the
public path. In ICC2, use the following command to enable crpr:set_app_options -

original
2022-08-25 15:07:39 · 734 reads · 0 comments  

7/11
Static Timing Analysis - Clock Skew (Clock Skew: Global
Skew and Local Skew)
Classification and Analysis of Clock Skew

original
2022-08-24 09:59:54 · 401 readings · 0 comments  

ICC2: clock tree analysis example

Common examples of clock tree

original
2022-06-30 19:42:46 · 502 reads · 0 comments  

ICC2: Analyze_design_violations, an artifact of timing analysis

ICC2 analysis timing uses the analyze timing violations command

original
2022-06-29 13:10:46 · 500 reads · 0 comments  

ICC2 user guide (4) Routing and Postroute Optimization

ICC2 (4) Routing and Postroute Optimization

original
2022-06-18 16:47:51 · 883 reading · 4 comments  

ICC2 user guide (3) Clock Tree Synthesis

ICC2 (3) Clock Tree Synthesis user guide analysis

original
2022-06-07 22:56:54 · 3436 reading · 1 comment  

ICC2 checks floorplan using report_placement

ICC2 checks floorplan using report_placement

original
2022-06-06 21:58:35 · 441 reads · 0 comments  

ICC2 user guide (1) Preparing the Design

ICC2 Preparing the Design part user guide interpretation

original
2022-06-05 16:03:33 · 2920 reads · 2 comments  

ICC2 (3) common commands in the route phase

Common commands in the ICC2 route phase

original
2022-05-28 08:35:17 · 1327 reads · 0 comments  

8/11
ICC2 user guide (2) Placement and Optimization
ICC2 place stage user guide

original
2022-05-25 21:48:27 · 2980 reads · 0 comments  

ICC2 add_buffer_on_route
ICC2 add_buffer_on_route repair transition

original
2022-05-22 15:30:14 · 715 reads · 0 comments  

ICC2 split_fanout
Use split_fanout to solve the fanout problem and indirectly solve the transition
problem

original
2022-05-21 11:24:25 · 399 reads · 0 comments  

Common commands in ICC2 (3) CTS stage

Common commands in the ICC2 clock opt phase

original
2022-05-15 10:31:50 · 2508 reading · 0 comments  

Common commands in ICC2 (2) place stage

Common commands in the ICC2 place phase

original
2022-04-21 14:34:47 · 2377 reads · 0 comments  

ICC2 (2) place —— congestion

The method of reducing congestion and related commands in the place stage

original
2022-04-21 14:02:20 · 1415 reads · 0 comments  

ICC2 (1) import design —— MCMM

ICC2 MCMM related commands

original
2022-04-19 17:34:20 · 1524 reads · 0 comments  

9/11
 ICC2 (1) import design —— tluplus
Itf to tluplus related commands TLUPlus is a binary table format for storing RC
coefficients. The TLUPlus model can estimate the RC calculation net delay by
including the influence of width, space, density and temperature on the resistivity.
1.2 The method of generating TLUplus Itf file to TLUplus command: grdgenxo -
itf2TLUPlus -i xx.itf-o xx.tlu+itf: interconnect technology format file Itf can also be
converted to nxtgrd format file with parameters such as thickness and area of ​each
layer.. .

original
2022-04-19 13:19:21 · 1111 reads · 0 comments  

ICC2 (1) import design —— NDM

Scripts and FAQs about NDM

original
2022-04-18 17:45:05 · 4014 reading · 0 comments  

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