CH CAMERA MODULE OV7670

User Manual

Introduction:
Here we introduced OV7670 camera module , including the communication of camera module and
Arduino UNO, the using ways to take photo via camera module, and so on. This is an Arduino camera
module, adopted the Surveillance cameras digital image processing chip-OV0706, specially designed for
image acquisition and processing application, based on TTL communication interface, very convenient to
connect with Arduino controller, able to read image and data via UART serial port, and then perform some
image processing.

Step 1: General description

This camera module can perform image processing such as AWB (auto white balance), AE (automatic
exposure) and AGC (automatic gain control), for the video signal coming from CMOS sensor. What’s more,
in fusion of other advanced technology such as image enhancement processing under low illumination,
and image noise intelligent forecast and suppress, this module would output high quality digital video
signals by standard CCIR656 interface. OV7670 built-in JPEG decoder supported reatime encoding for
collected image, and external controller can easily read the M – JPEG video streams, achieving the camera
design of double stream. OV7670 supported motion detection and OSD display function of screen
characters and pattern overlay, capable of self-defining detection area and sensitivity.

Step 2: Test OV7670 camera module - Needed tool for testing

Hardware
SD Module
Arduino Uno
Jumper Wire
USB cable
OV7670 camera module
Software
Camera_VC0706_TEST
Arduino IDE（download it from official website）
Step 3: Hardware connection

Connect the hardware as the diagram shows.

Step 4: Software use and code programming
1- First, download the two files of Camera_OV0706_lib and Camera_OV0706_TEST from
the Software
2- Unzip it.
3- Put the unzipped file of Camera_OV0706_lib into the Arduino IDE folder of Libraries.
4- Open unzipped file of Camera_OV0706_TEST, and the program the code into UNO. The detailed
steps are demonstrated in the pictures.
5- Click Tools and then choose the board of Arduino UNO.
6- Click Tools / Serial Port，and then choose the corresponding COM number.
7- And then click the button of programming like below in red rectangle, program the code into the
UNO board until done uploading appears.
8- Finally open the monitoring serial port as below in red rectangle.
9- When the serial port display the data like demonstrated below, you can press the digital keys to
take a photo.
10- If photo was taken successfully, the serial port would be displayed.
11- Until now, the module testing has been completed. Thanks for reading.
 Advanced Information
Preliminary Datasheet

TM
OV7670 CMOS VGA (640x480) C AMERACHIP with OmniPixel ® Technology

General Description Applications

The OV7670/OV7171 CAMERACHIPTM is a low voltage • Cellular and Picture Phones
CMOS image sensor that provides the full functionality of • Toys
a single-chip VGA camera and image processor in a small • PC Multimedia
footprint package. The OV7670/OV7171 provides
full-frame, sub-sampled or windowed 8-bit images in a • Digital Still Cameras
wide range of formats, controlled through the Serial
Camera Control Bus (SCCB) interface. Key Specifications
This product has an image array capable of operating at Array Element (VGA) 640 x 480
up to 30 frames per second (fps) in VGA with complete Digital Core 1.8VDC +10%
user control over image quality, formatting and output data Power Supply Analog 2.45V to 3.0V
transfer. All required image processing functions,
I/O 1.7V to 3.0V
including exposure control, gamma, white balance, color
saturation, hue control and more, are also programmable Power Active TBD
through the SCCB interface. In addition, OmniVision Requirements Standby < 20 µA
CAMERACHIPs use proprietary sensor technology to Temperature Operation -30°C to 70°C
improve image quality by reducing or eliminating common Range Stable Image 0°C to 50°C
lighting/electrical sources of image contamination, such • YUV/YCbCr 4:2:2
as fixed pattern noise (FPN), smearing, blooming, etc., to • RGB565/555
Output Formats (8-bit)
produce a clean, fully stable color image. • GRB 4:2:2
• Raw RGB Data
Lens Size 1/6"
Note: The OV7670/OV7171 uses a
Pb lead-free package.
Chief Ray Angle 24°
Maximum Image
30 fps for VGA
Transfer Rate
Features Sensitivity 1.1 V/Lux-sec
• High sensitivity for low-light operation S/N Ratio 40 dB
• Low operating voltage for embedded portable apps Dynamic Range TBD
• Standard SCCB interface compatible with I2C Scan Mode Progressive
interface Electronics Exposure Up to 510:1 (for selected fps)
• Supports VGA, CIF, and resolutions lower than CIF Pixel Size 3.6 µm x 3.6 µm
for RGB (GRB 4:2:2, RGB565/555), YUV (4:2:2) and Dark Current 12 mV/s at 60°C
YCbCr (4:2:2) formats Well Capacity 17 K e
• VarioPixel® method for sub-sampling Image Area 2.36 mm x 1.76 mm
• Automatic image control functions including: Package Dimensions 3785 µm x 4235 µm
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB), Figure 1 OV7670/OV7171 Pin Diagram (Top View)
Automatic Band Filter (ABF), and Automatic
Black-Level Calibration (ABLC)
• Image quality controls including color saturation,
hue, gamma, sharpness (edge enhancement), and A1 A2 A3 A4 A5

anti-blooming AVDD SIO_D SIO_C D1 D3

• ISP includes noise reduction and defect correction B1 B2 B3 B4 B5

• Supports LED and flash strobe mode
PWDN
• Supports scaling
VREF2 AGND D0 D2

• Lens shading correction C1 C2

• Flicker (50/60 Hz) auto detection DVDD VREF1

• Saturation level auto adjust (UV adjust) OV7670/OV7171
D1 D2
• Edge enhancement level auto adjust
VSYNC HREF
• De-noise level auto adjust
Ordering Information
E1 E2 E3 E4 E5

PCLK STROBE XCLK D7 D5

Product Package F1 F2 F3 F4 F5

OV07670-VL2A (Color, lead-free) 24 pin CSP2 DOVDD RESET DOGND D6 D4

OV07171-VL2A (B&W, lead-free) 24 pin CSP2

Functional Description
Figure 2 shows the functional block diagram of the OV7670/OV7171 image sensor. The OV7670/OV7171 includes:
• Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode)
• Analog Signal Processor
• A/D Converters
• Test Pattern Generator
• Digital Signal Processor (DSP)
• Image Scaler
• Timing Generator
• Digital Video Port
• SCCB Interface
• LED and Strobe Flash Control Output

Figure 2 Functional Block Diagram

Buffer Buffer

Test
Pattern
Generator
G
DSP Image Video
Analog FIFO
(Lens shading Scaler Port
Processing A/D correction, D[7:0]
de-noise, white/
R black pixel
50/60 Hz correction, auto
white balance,
Auto etc.)
B Detect

Column Sense Amp Exposure/Gain

Detect
Row Select

Image Array
(656 x 488)
Registers

SCCB
Clock Video Timing Generator
Interface
Exposure/Gain
Control

XCLK STROBE HREF PCLK VSYNC RESET PWDN SIO_C SIO_D

 Functional Description

Image Sensor Array Test Pattern Generator

The OV7670/OV7171 sensor has an image array of The Test Pattern Generator features the following:
656 x 488 pixels for a total of 320,128 pixels, of which • 8-bar color bar pattern
640 x 480 pixels are active (307,200 pixels). Figure 3 • Fade-to-gray color bar pattern
shows a cross-section of the image sensor array.
• Shift "1" in output pin
Figure 3 Image Sensor Array
Microlens

Glass
Digital Signal Processor (DSP)

This block controls the interpolation from Raw data to

RGB and some image quality control.
• Edge enhancement (a two-dimensional high pass
Red
filter)
Blue Green
• Color space converter (can change Raw data to RGB
or YUV/YCbCr)
• RGB matrix to eliminate color cross talk
Timing Generator • Hue and saturation control
• White/black pixel correction
In general, the timing generator controls the following
functions: • De-noise
• Array control and frame generation • Lens shading correction
• Internal timing signal generation and distribution • Programmable gamma control
• Frame rate timing • Transfer 10-bit data to 8-bit
• Automatic Exposure Control (AEC)
• External timing outputs (VSYNC, HREF/HSYNC, and
PCLK) Image Scaler

This block controls all output and data formatting required

prior to sending the image out. This block scales
Analog Signal Processor YUV/RGB output from VGA to CIF and almost any size
under CIF.
This block performs all analog image functions including:
• Automatic Gain Control (AGC)
• Automatic White Balance (AWB)
Digital Video Port

Register bits COM2[1:0] increase IOL/IOH drive current

A/D Converters and can be adjusted as a function of the customer’s
loading.
After the Analog Processing block, the bayer pattern Raw
signal is fed to a 10-bit analog-to-digital (A/D) converter
shared by G and BR channels. This A/D converter
operates at speeds up to 12 MHz and is fully synchronous
SCCB Interface
to the pixel rate (actual conversion rate is related to the
frame rate). The Serial Camera Control Bus (SCCB) interface controls
the CAMERACHIP operation. Refer to OmniVision
In addition to the A/D conversion, this block also has the Technologies Serial Camera Control Bus (SCCB)
following functions: Specification for detailed usage of the serial control port.
• Digital Black-Level Calibration (BLC)
• Optional U/V channel delay
• Additional A/D range controls
LED and Strobe Flash Control Output
The OV7670/OV7171 has a Strobe mode that allows it to
In general, the combination of the A/D Range Multiplier work with an external flash and LED.
and A/D Range Control sets the A/D range and maximum
value to allow the user to adjust the final image brightness
as a function of the individual application.
 Pin Description

Pin Description

Table 1 Pin Description

Pin Number Name Pin Type Function/Description

A1 AVDD Power Analog power supply

A2 SIO_D I/O SCCB serial interface data I/O

A3 SIO_C Input SCCB serial interface clock input

A4 D1a Output YUV/RGB video component output bit[1]

A5 D3 Output YUV/RGB video component output bit[3]

Power Down Mode Selection

B1 PWDN Input (0)b 0: Normal mode
1: Power down mode

B2 VREF2 Reference Reference voltage - connect to ground using a 0.1 µF capacitor

B3 AGND Power Analog ground

B4 D0 Output YUV/RGB video component output bit[0]

B5 D2 Output YUV/RGB video component output bit[2]

C1 DVDD Power Power supply (+1.8 VDC) for digital logic core

C2 VREF1 Reference Reference voltage - connect to ground using a 0.1 µF capacitor

D1 VSYNC Output Vertical sync output

D2 HREF Output HREF output

E1 PCLK Output Pixel clock output

E2 STROBE Output LED/strobe control output

E3 XCLK Input System clock input

E4 D7 Output YUV/RGB video component output bit[7]

E5 D5 Output YUV/RGB video component output bit[5]

F1 DOVDD Power Digital power supply for I/O (1.7V ~ 3.0V)

Clears all registers and resets them to their default values.

F2 RESET Input (0) 0: Normal mode
1: Reset mode

F3 DOGND Power Digital ground

F4 D6 Output YUV/RGB video component output bit[6]

F5 D4 Output YUV/RGB video component output bit[4]

a. D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB)

b. Input (0) represents an internal pull-down resistor.
Electrical Characteristics

Table 2 Absolute Maximum Ratings

Ambient Storage Temperature -40ºC to +95ºC

VDD-A 4.5 V

Supply Voltages (with respect to Ground) VDD-C 3V

VDD-IO 4.5 V

All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+0.5V

Lead-free Temperature, Surface-mount process 245ºC

ESD Rating, Human Body model 2000V

NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 3 DC Characteristics (-30°C < TA < 70°C)

Symbol Parameter Condition Min Typ Max Unit

VDD-A DC supply voltage – Analog – 2.45 2.75 3.0 V

VDD-C DC supply voltage – Digital Core – 1.62 1.8 1.98 V

VDD-IO DC supply voltage – I/O power – 1.7 – 3.0V V

IDDA Active (Operating) Current See Note a 10 + 8b mA

IDDS-SCCB Standby Current 1 mA

See Note c
IDDS-PWDN Standby Current 10 20 µA

VIH Input voltage HIGH CMOS 0.7 x VDD-IO V

VIL Input voltage LOW 0.3 x VDD-IO V

VOH Output voltage HIGH CMOS 0.9 x VDD-IO V

VOL Output voltage LOW 0.1 x VDD-IO V

IOH Output current HIGH See Note d 8 mA

IOL Output current LOW 15 mA

IL Input/Output Leakage GND to VDD-IO ±1 µA

a. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V

IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loading
b. IDD-C = 10mA, IDD-A = 8mA, without loading
c. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V
IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby
d. Standard Output Loading = 25pF, 1.2KΩ
 Electrical Characteristics

Table 4 Functional and AC Characteristics (-30°C < TA < 70°C)

Symbol Parameter Min Typ Max Unit
Functional Characteristics
A/D Differential Non-Linearity + 1/2 LSB
A/D Integral Non-Linearity +1 LSB
AGC Range 30 dB
Red/Blue Adjustment Range 12 dB
Inputs (PWDN, CLK, RESET)

fCLK Input Clock Frequency 10 24 48 MHz

tCLK Input Clock Period 21 42 100 ns

tCLK:DC Clock Duty Cycle 45 50 55 %

tS:RESET Setting time after software/hardware reset 1 ms

tS:REG Settling time for register change (10 frames required) 300 ms
SCCB Timing (see Figure 4)

fSIO_C Clock Frequency 400 KHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tAA SIO_C low to Data Out valid 100 900 ns

tBUF Bus free time before new START 1.3 µs

tHD:STA START condition Hold time 600 ns

tSU:STA START condition Setup time 600 ns

tHD:DAT Data-in Hold time 0 µs

tSU:DAT Data-in Setup time 100 ns

tSU:STO STOP condition Setup time 600 ns

tR, tF SCCB Rise/Fall times 300 ns

tDH Data-out Hold time 50 ns

Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10)

tPDV PCLK[↓] to Data-out Valid 5 ns

tSU D[7:0] Setup time 15 ns

tHD D[7:0] Hold time 8 ns

tPHH PCLK[↓] to HREF[↑] 0 5 ns

tPHL PCLK[↓] to HREF[↓] 0 5 ns

• VDD: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V

• Rise/Fall Times: I/O: 5ns, Maximum
AC SCCB: 300ns, Maximum
Conditions: • Input Capacitance: 10pf
• Output Loading: 25pF, 1.2KΩ to 2.5V
• fCLK: 24MHz
Timing Specifications

Figure 4 SCCB Timing Diagram

tF t HIGH tR
tLOW

SIO_C
t HD:STA t HD:DAT t SU:DAT
tSU:STA tSU:STO

SIO_D
IN
t BUF
tAA t DH
SIO_D
OUT

Figure 5 Horizontal Timing

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

Figure 6 VGA Frame Timing

510 x tLINE

VSYNC
480 x tLINE
3 x tLINE 17 tLINE
tLINE = 784 tP 10 tLINE
144 tP
HREF

640 tP
80 tP 45 tP 19 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P639
Row 0 Row 1 Row 2 Row 479
NOTE:
For Raw data, tP = tPCLK
For YUV/RGB, tP = 2 x tPCLK
 Timing Specifications

Figure 7 QVGA Frame Timing

VGA HREF
(see Figure 7,
VGA Frame Timing)

QVGA HREF

Figure 8 QQVGA Frame Timing

VGA HREF
(see Figure 7,
VGA Frame Timing)

QQVGA HREF
(1 from 4,
120 from 480)

Figure 9 CIF Frame Timing

VGA HREF
(see Figure 7,
VGA Frame Timing)

CIF HREF
(3 from 5)

Figure 10 QCIF Frame Timing

QVGA HREF
(see Figure 7,
QVGA Frame Timing)

QCIF HREF
(3 from 5)
Figure 11 RGB 565 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[7] R4 G2 D[7]
D[6] D[6]
D[5] G0 D[5]
D[4] B4 D[4]
D[3] R0 D[3]
D[2] G5 D[2]
D[1] D[1]
D[0] G3 B0 D[0]

Figure 12 RGB 555 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[7] X G2 D[7]
D[6] R4 D[6]
D[5] G0 D[5]
D[4] B4 D[4]
D[3] D[3]
D[2] R0 D[2]
D[1] G4 D[1]
D[0] G3 B0 D[0]
 Register Set

Register Set
Table 5 provides a list and description of the Device Control registers contained in the OV7670/OV7171. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.

Table 5 Device Control Register List

Address Register Default

(Hex) Name (Hex) R/W Description
AGC – Gain control gain setting
00 GAIN 00 RW Bit[7:0]: AGC[7:0] (see VREF[7:6] (0x03) for AGC[9:8])
• Range: [00] to [FF]
AWB – Blue channel gain setting
01 BLUE 80 RW
• Range: [00] to [FF]
AWB – Red channel gain setting
02 RED 80 RW
• Range: [00] to [FF]
Vertical Frame Control
Bit[7:6]: AGC[9:8] (see GAIN[7:0] (0x00) for AGC[7:0])
03 VREF 03 RW Bit[5:4]: Reserved
Bit[3:2]: VREF end low 2 bits (high 8 bits at VSTOP[7:0]
Bit[1:0]: VREF start low 2 bits (high 8 bits at VSTRT[7:0]
Common Control 1
Bit[7]: Reserved
Bit[6]: CCIR656 format
04 COM1 00 RW 0: Disable
1: Enable
Bit[5:2]: Reserved
Bit[1:0]: AEC low 2 LSB (see registers AECHH for AEC[15:10] and
AECH for AEC[9:2])
U/B Average Level
05 BAVE 00 RW
Automatically updated based on chip output format
Y/Gb Average Level
06 GbAVE 00 RW
Automatically updated based on chip output format
Exposure Value - AEC MSB 5 bits
Bit[7:6]: Reserved
07 AECHH 00 RW
Bit[5:0]: AEC[15:10] (see registers AECH for AEC[9:2] and COM1
for AEC[1:0])
V/R Average Level
08 RAVE 00 RW
Automatically updated based on chip output format
Common Control 2
Bit[7:5]: Reserved
Bit[4]: Soft sleep mode
Bit[3:2]: Reserved
09 COM2 01 RW Bit[1:0]: Output Drive Capability
00: 1x
01: 2x
10: 3x
11: 4x
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
0A PID 76 R Product ID Number MSB (Read only)
0B VER 70 R Product ID Number LSB (Read only)
Common Control 3
Bit[7]: Reserved
Bit[6]: Output data MSB and LSB swap
Bit[5]: Tri-state option for output clock at power-down period
0: Tri-state at this period
1: No tri-state at this period
Bit[4]: Tri-state option for output data at power-down period
0: Tri-state at this period
1: No tri-state at this period
0C COM3 00 RW Bit[3]: Scale enable
0: Disable
1: Enable - if set to a pre-defined format (see
COM7[5:3]), then COM14[3] must be set to 1 for
manual adjustment.
Bit[2]: DCW enable
0: Disable
1: Enable - if set to a pre-defined format (see
COM7[5:3]), then COM14[3] must be set to 1 for
manual adjustment.
Bit[1:0]: Reserved
Common Control 4
Bit[7:6]: Reserved
Bit[5:4]: Average option (must be same value as COM17[7:6])
0D COM4 40 RW 00: Full window
01: 1/2 window
10: 1/4 window
11: 1/4 window
Bit[3:0]: Reserved
Common Control 5
0E COM5 01 RW
Bit[7:0]: Reserved
Common Control 6
Bit[7]: Output of optical black line option
0: Disable HREF at optical black
1: Enable HREF at optical black
Bit[6]: BLC input selection
0F COM6 43 RW 0: Use electrical black line as BLC signal
1: Use optical black line as BLC signal
Bit[5]: Digital BLC enable
Bit[4:2]: Reserved
Bit[1]: Reset all timing when format changes
Bit[0]: Reserved
Exposure Value
10 AECH 40 RW Bit[7:0]: AEC[9:2] (see registers AECHH for AEC[15:10] and
COM1 for AEC[1:0])
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Internal Clock
Bit[7]: Digital PLL option
0: Disable double clock option, meaning the maximum
PCLK can be as high as half input clock
11 CLKRC 80 RW 1: Enable double clock option, meaning the maximum
PCLK can be as high as input clock
Bit[6]: Use external clock directly (no clock pre-scale available)
Bit[5:0]: Internal clock pre-scalar
F(internal clock) = F(input clock)/(Bit[5:0]+1)
• Range: [0 0000] to [1 1111]
Common Control 7
Bit[7]: SCCB Register Reset
0: No change
1: Resets all registers to default values
Bit[6]: Reserved
Bit[5]: Output format - CIF selection
Bit[4]: Output format - QVGA selection
Bit[3]: Output format - QCIF selection
Bit[2]: Output format - RGB selection (see below)
12 COM7 00 RW
Bit[1]: Color bar
0: Disable
1: Enable
Bit[0]: Output format - Raw RGB (see below)

COM7[2] COM7[0]
YUV 0 0
RGB 1 0
Bayer RAW 0 1
Processed Bayer RAW 1 1
Common Control 8
Bit[7]: Enable fast AGC/AEC algorithm
Bit[6]: AEC - Step size limit
0: Step size is limited to vertical blank
1: Unlimited step size
Bit[5]: Banding filter ON/OFF - In order to turn ON the banding
filter, BD50ST (0x9D) or BD60ST (0x9E) must be set to a
13 COM8 8F RW non-zero value.
0: ON
1: OFF
Bit[4:3]: Reserved
Bit[2]: AGC Enable
Bit[1]: AWB Enable
Bit[0]: AEC Enable
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 9
Bit[7]: Reserved
Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x
001: 4x
010 8x
14 COM9 4A RW 011: 16x
100: 32x
101 64x
110: 128x
111: Not allowed
Bit[3:1]: Reserved
Bit[0]: Freeze AGC/AEC
Common Control 10
Bit[7]: Reserved
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
0: Free running PCLK
1: PCLK does not toggle during horizontal blank
15 COM10 00 RW Bit[4]: PCLK reverse
Bit[3]: HREF reverse
Bit[2]: VSYNC option
0: VSYNC changes on falling edge of PCLK
1: VSYNC changes on rising edge of PCLK
Bit[1]: VSYNC negative
Bit[0]: HSYNC negative
16 RSVD XX – Reserved
Output Format - Horizontal Frame (HREF column) start high 8-bit (low
17 HSTART 11 RW
3 bits are at HREF[2:0])
Output Format - Horizontal Frame (HREF column) end high 8-bit (low
18 HSTOP 61 RW
3 bits are at HREF[5:3])
Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at
19 VSTRT 03 RW
VREF[1:0])
Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at
1A VSTOP 7B RW
VREF[3:2])
Data Format - Pixel Delay Select (delays timing of the D[7:0] data relative
to HREF in pixel units)
1B PSHFT 00 RW
• Range: [00] (no delay) to [FF] (256 pixel delay which accounts for
whole array)
1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)
1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Mirror/VFlip Enable
Bit[7:6]: Reserved
Bit[5]: Mirror
0: Normal image
1: Mirror image
1E MVFP 00 RW Bit[4]: VFlip enable
0: Normal image
1: Vertically flip image
Bit[3]: Reserved
Bit[2]: Black sun enable
Bit[1:0]: Reserved
1F LAEC 00 RW Reserved
ADC Control
Bit[7:4]: Reserved
Bit[3]: ADC range adjustment
0: 1x range
20 ADCCTR0 04 RW 1: 1.5x range
Bit[2:0]: ADC reference adjustment
000: 0.8x
100: 1x
111: 1.2x
21 ADCCTR1 02 RW Bit[7:0]: Reserved
22 ADCCTR2 01 RW Bit[7:0]: Reserved
23 ADCCTR3 80 RW Bit[7:0]: Reserved
24 AEW 75 RW AGC/AEC - Stable Operating Region (Upper Limit)
25 AEB 63 RW AGC/AEC - Stable Operating Region (Lower Limit)
AGC/AEC Fast Mode Operating Region
26 VPT D4 RW Bit[7:4]: High nibble of upper limit of fast mode control zone
Bit[3:0]: High nibble of lower limit of fast mode control zone
B Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]: Bias adjustment sign
27 BBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
Gb Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]: Bias adjustment sign
28 GbBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
29 RSVD XX – Reserved
Dummy Pixel Insert MSB
Bit[7:4]: 4 MSB for dummy pixel insert in horizontal direction
2A EXHCH 00 RW
Bit[3:2]: HSYNC falling edge delay 2 MSB
Bit[1:0]: HSYNC rising edge delay 2 MSB
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Dummy Pixel Insert LSB
2B EXHCL 00 RW
8 LSB for dummy pixel insert in horizontal direction
R Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]: Bias adjustment sign
2C RBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
2D ADVFL 00 RW LSB of insert dummy lines in vertical direction (1 bit equals 1 line)
2E ADVFH 00 RW MSB of insert dummy lines in vertical direction
2F YAVE 00 RW Y/G Channel Average Value
30 HSYST 08 RW HSYNC Rising Edge Delay (low 8 bits)
31 HSYEN 30 RW HSYNC Falling Edge Delay (low 8 bits)
HREF Control
Bit[7:6]: HREF edge offset to data output
32 HREF 80 RW
Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP)
Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART)
Array Current Control
33 CHLF 08 RW
Bit[7:0]: Reserved
Array Reference Control
34 ARBLM 03 RW
Bit[7:0]: Reserved
35-36 RSVD XX – Reserved
ADC Control
37 ADC 04 RW
Bit[7:0]: Reserved
ADC and Analog Common Mode Control
38 ACOM 12 RW
Bit[7:0]: Reserved
ADC Offset Control
39 OFON 00 RW
Bit[7:0]: Reserved
Line Buffer Test Option
Bit[7:6]: Reserved
Bit[5]: Negative image enable
0: Normal image
1: Negative image
Bit[4]: UV output value
0: Use normal UV output
3A TSLB 0C RW 1: Use fixed UV value set in registers MANU and MANV
as UV output instead of chip output
Bit[3]: Output sequence (use with register COM13[1] (0x3D))
TSLB[3], COM13[1]:
00: Y U Y V
01: Y V Y U
10: U Y V Y
11: V Y U Y
Bit[2:0]: Reserved
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 11
Bit[7]: Night mode
0: Night mode disable
1: Night mode enable - The frame rate is reduced
automatically while the minimum frame rate is limited
by COM11[6:5]. Also, ADVFH and ADVFL will be
automatically updated.
Bit[6:5]: Minimum frame rate of night mode
00: Same as normal mode frame rate
01: 1/2 of normal mode frame rate
10: 1/4 of normal mode frame rate
3B COM11 00 RW 11: 1/8 of normal mode frame rate
Bit[4]: D56_Auto
0: Disable 50/60 Hz auto detection
1: Enable 50/60 Hz auto detection
Bit[3]: Banding filter value select (effective only when
COM11[4] = 0)
0: Select BD60ST[7:0] (0x9E) as Banding Filter Value
1: Select BD50ST[7:0] (0x9D) as Banding Filter Value
Bit[2]: Reserved
Bit[1]: Exposure timing can be less than limit of banding filter
when light is too strong
Bit[0]: Reserved
Common Control 12
Bit[7]: HREF option
3C COM12 40 RW 0: No HREF when VSYNC is low
1: Always has HREF
Bit[6:0]: Reserved
Common Control 13
Bit[7]: Gamma enable
Bit[6]: UV saturation level - UV auto adjustment. Result is saved
in register SATCTR[3:0] (0xC9)
Bit[5:2]: Reserved
3D COM13 99 RW Bit[1]: UV swap (use with register TSLB[3] (0x3A))
TSLB[3], COM13[1]:
00: Y U Y V
01: Y V Y U
10: U Y V Y
11: V Y U Y
Bit[0]: Reserved
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 14
Bit[7:5]: Reserved
Bit[4]: DCW and scaling PCLK enable
0: Normal PCLK
1: DCW and scaling PCLK, controlled by register
COM14[2:0] and SCALING_PCLK_DIV[3:0] (0x73))
Bit[3]: Manual scaling enable for pre-defined resolution modes
such as CIF, QCIF, and QVGA
3E COM14 0E RW 0: Scaling parameter cannot be adjusted manually
1: Scaling parameter can be adjusted manually
Bit[2:0]: PCLK divider (only when COM14[4] = 1)
000: Divided by 1
001: Divided by 2
010 Divided by 4
011: Divided by 8
100: Divided by 16
101~111: Not allowed
Edge Enhancement Adjustment
3F EDGE 88 RW Bit[7:5]: Reserved
Bit[4:0]: Edge enhancement factor
Common Control 15
Bit[7:6]: Data format - output full range enable
0x: Output range: [10] to [F0]
10: Output range: [01] to [FE]
11: Output range: [00] to [FF]
40 COM15 C0 RW Bit[5:4]: RGB 555/565 option (must set COM7[2] = 1 and
COM7[0] = 0)
x0: Normal RGB output
01: RGB 565
11: RGB 555
Bit[3:0]: Reserved
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 16
Bit[7:6]: Reserved
Bit[5]: Enable edge enhancement threshold auto-adjustment for
YUV output (result is saved in register EDGE[4:0] (0x3F)
and range is controlled by registers REG75[4:0] (0x75)
and REG76[4:0] (0x76))
0: Disable
1: Enable
Bit[4]: De-noise threshold auto-adjustment (result is saved in
41 COM16 10 RW register DNSTH (0x4C) and range is controlled by register
REG77[7:0] (0x77))
0: Disable
1: Enable
Bit[3]: AWB gain enable
Bit[2]: Reserved
Bit[1]: Color matrix coefficient double option
0: Original matrix
1: Double of original matrix
Bit[0]: Reserved
Common Control 17
Bit[7:6]: AEC window must be the same value as COM4[5:4])
00: Normal
01: 1/2
10: 1/4
42 COM17 08 RW 11: 1/4
Bit[5:4]: Reserved
Bit[3]: DSP color bar enable
0: Disable
1: Enable
Bit[2:0]: Reserved
43 AWBC1 14 RW Reserved
44 AWBC2 F0 RW Reserved
45 AWBC3 45 RW Reserved
46 AWBC4 61 RW Reserved
47 AWBC5 51 RW Reserved
48 AWBC6 79 RW Reserved
49-4A RSVD XX – Reserved
Register 4B
4B REG4B 00 RW Bit[7:1]: Reserved
Bit[0]: UV average enable
4C DNSTH 00 RW De-noise Threshold
4D-4E RSVD XX – Reserved
4F MTX1 40 RW Matrix Coefficient 1
50 MTX2 34 RW Matrix Coefficient 2
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
51 MTX3 0C RW Matrix Coefficient 3
52 MTX4 17 RW Matrix Coefficient 4
53 MTX5 29 RW Matrix Coefficient 5
54 MTX6 40 RW Matrix Coefficient 6
55 BRIGHT 00 RW Brightness Control
56 CONTRAS 40 RW Contrast Control

57 CONTRAS- 80 RW Contrast Center

CENTER
Matrix Coefficient Sign for coefficient 5 to 0
Bit[7]: Auto contrast center enable
0: Disable, center is set by register
CONTRAS-CENTER (0x57)
1: Enable, register CONTRAS-CENTER is updated
58 MTXS 1E RW automatically
Bit[6]: Reserved
Bit[5:0]: Matrix coefficient sign
0: Plus
1: Minus
59-61 RSVD XX – AWB Control
62 LCC1 00 RW Lens Correction Option 1
63 LCC2 00 RW Lens Correction Option 2
64 LCC3 10 RW Lens Correction Option 3
65 LCC4 80 RW Lens Correction Option 4
Lens Correction Control
Bit[7:3]: Reserved
66 LCC5 00 RW Bit[2]: Lens correction control select
Bit[1]: Reserved
Bit[0]: Lens correction enable
67 MANU 80 RW Manual U Value (effective only when register TSLB[4] is high)
68 MANV 80 RW Manual V Value (effective only when register TSLB[4] is high)
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Fix Gain Control
Bit[7:6]: Fix gain for Gr channel
00: 1x
01: 1.25x
10: 1.5x
11: 1.75x
Bit[5:4]: Fix gain for Gb channel
00: 1x
01: 1.25x
10: 1.5x
69 GFIX 00 RW 11: 1.75x
Bit[3:2]: Fix gain for R channel
00: 1x
01: 1.25x
10: 1.5x
11: 1.75x
Bit[1:0]: Fix gain for B channel
00: 1x
01: 1.25x
10: 1.5x
11: 1.75x
6A GGAIN 00 RW G Channel AWB Gain
Bit[7:6]: PLL control
00: Bypass PLL
01: Input clock x4
10: Input clock x8
11: Input clock x16
6B DBLV 3A RW Bit[5]: Reserved
Bit[4]: Regulator control
0: Enable internal regulator
1: Bypass internal regulator
Bit[3:0]: Clock divider control for DSP scale control (valid only
when COM14[3] = 1)
6C AWBCTR3 02 RW AWB Control 3
6D AWBCTR2 55 RW AWB Control 2
6E AWBCTR1 00 RW AWB Control 1
6F AWBCTR0 9A RW AWB Control 0
Bit[7]: Test_pattern[0] - works with test_pattern[1] test_pattern
(SCALING_XSC[7], SCALING_YSC[7]):
00: No test output
70 SCALING_ 4A RW 01: Shifting "1"
XSC
10: 8-bar color bar
11: Fade to gray color bar
Bit[6:0]: Horizontal scale factor
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
Bit[7]: Test_pattern[1] - works with test_pattern[0] test_pattern
(SCALING_XSC[7], SCALING_YSC[7])::
00: No test output
71 SCALING_ 35 RW 01: Shifting "1"
YSC
10: 8-bar color bar
11: Fade to gray color bar
Bit[6:0]: Vertical scale factor

SCALING_ DCW Control

72 DCWCTR 11 RW
Bit[7:0]: DCW control parameter
Bit[7:4]: Reserved
Bit[3:0]: Clock divider control for DSP scale control (valid only
when COM14[3] = 1). Should change with COM14[2:0].
0000: Divided by 1
73 SCALING_ 00 RW 0001: Divided by 2
PCLK_DIV
0010: Divided by 4
0011: Divided by 8
0100: Divided by 16
0101~1111: Not allowed
Bit[7:5]: Reserved
Bit[4]: DG_Manu
0: Digital gain control by VREF[7:6]
1: Digital gain control by REG74[1:0]
Bit[3:2]: Reserved
74 REG74 00 RW
Bit[1:0]: Digital gain manual control
00: Bypass
01: 1x
10: 2x
11: 4x
Register 75
75 REG75 0F RW Bit[7:5]: Reserved
Bit[4:0]: Edge enhancement lower limit
Register 76
Bit[7]: Reserved
Bit[6]: White pixel correction enable
0: Disable
76 REG76 01 RW 1: Enable
Bit[5]: Black pixel correction enable
0: Disable
1: Enable
Bit[4:0]: Edge enhancement higher limit
Register 77
77 REG77 10 RW
Bit[7:0]: Offset, de-noise range control
78-79 RSVD XX – Reserved
7A GAM1 02 RW Gamma Curve 1st Segment Input End Point 0x010 Output Value
7B GAM2 07 RW Gamma Curve 2nd Segment Input End Point 0x020 Output Value
7C GAM3 1F RW Gamma Curve 3rd Segment Input End Point 0x040 Output Value
 Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
7D GAM4 49 RW Gamma Curve 4th Segment Input End Point 0x080 Output Value
7E GAM5 5A RW Gamma Curve 5th Segment Input End Point 0x0A0 Output Value
7F GAM6 6A RW Gamma Curve 6th Segment Input End Point 0x0C0 Output Value
80 GAM7 79 RW Gamma Curve 7th Segment Input End Point 0x0E0 Output Value
89 GAM8 87 RW Gamma Curve 8th Segment Input End Point 0x100 Output Value
89 GAM9 94 RW Gamma Curve 9th Segment Input End Point 0x120 Output Value
89 GAM10 9F RW Gamma Curve 10th Segment Input End Point 0x140 Output Value
89 GAM11 AF RW Gamma Curve 11th Segment Input End Point 0x180 Output Value
86 GAM12 BB RW Gamma Curve 12th Segment Input End Point 0x1C0 Output Value
87 GAM13 CF RW Gamma Curve 13th Segment Input End Point 0x240 Output Value
88 GAM14 EE RW Gamma Curve 14th Segment Input End Point 0x2C0 Output Value
89 GAM15 EE RW Gamma Curve 15th Segment Input End Point 0x340 Output Value
8A-91 RSVD XX – Reserved
92 DM_LNL 00 RW Dummy Line low 8 bits
93 DM_LNH 00 RW Dummy Line high 8 bits
94 LCC6 50 RW Lens Correction Option 6 (effective only when LCC5[2] is high)
95 LCC7 50 RW Lens Correction Option 7 (effective only when LCC5[2] is high)
96-9C RSVD XX – Reserved
50 Hz Banding Filter Value
9D BD50ST 99 RW
(effective only when COM8[5] is high and COM11[3] is high)
60 Hz Banding Filter Value
9E BD60ST 7F RW
(effective only when COM8[5] is high and COM11[3] is low)
9F-AB XX – Histogram-based AEC/AGC Control
Register AC
Bit[7]: Strobe enable
Bit[6]: R / G / B gain controlled by STR_R (0xAD) / STR_G
(0xAE) / STR_B (0xAF) for LED output frame
Bit[5:4]: Xenon mode option
00: 1 line
01: 2 lines
AC STR-OPT 00 RW
10: 3 lines
11: 4 lines
Bit[3:2]: Reserved
Bit[1:0]: Mode select
00: Xenon
01: LED 1&2
1x: LED 3
AD STR_R 80 RW R Gain for LED Output Frame
AE STR_G 80 RW G Gain for LED Output Frame
AF STR_B 80 RW B Gain for LED Output Frame
Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description
B0-B2 RSVD XX – Reserved
B3 THL_ST 80 RW Digital BLC Target
B4 RSVD XX – Reserved
B5 THL_DLT 04 RW Digital BLC Stable Range
B6-BD RSVD XX – Reserved
Bit[7]: Reserved
BE AD-CHB 00 RW Bit[6]: Sign bit
Bit[5:0]: ADC offset value
Bit[7]: Reserved
BF AD-CHR 00 RW Bit[6]: Sign bit
Bit[5:0]: ADC offset value
Bit[7]: Reserved
C0 AD-CHGb 00 RW Bit[6]: Sign bit
Bit[5:0]: ADC offset value
Bit[7]: Reserved
C1 AD-CHGr 00 RW Bit[6]: Sign bit
Bit[5:0]: ADC offset value
C2-C8 RSVD XX – Reserved
Saturation Control
C9 SATCTR C0 RW Bit[7:4]: UV saturation control min
Bit[3:0]: UV saturation control result
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
 Package Specifications

Package Specifications
The OV7670/OV7171 uses a 24-ball Chip Scale Package 2 (CSP2). Refer to Figure 13 for package information, Table 6 for
package dimensions and Figure 14 for the array center on the chip.

Note: For OVT devices that are lead-free, all part marking letters are
lower case. Underlining the last digit of the lot number indicates CSP2 is
used.

Figure 13 OV7670/OV7171 Package Specifications

A
S1 J1
1 2 3 4 5 S2 5 4 3 2 1

A A

B B
J2
B C C
wxyz
D D abcd
E E

F F

Center of BGA (Die) =

Top View (Bumps Down) Center of the package
Bottom View (Bumps Up)

Glass
Die Part Marking Code:
w - OVT Product Version
C3 x - Year the part is assembled
C2 C y - Month the part is assembled
z - Wafer number
abcd - Last four digits of lot number
C1 Side View

Table 6 OV7670/OV7171 Package Dimensions

Parameter Symbol Minimum Nominal Maximum Unit

Package Body Dimension X A 3760 3785 3810 µm
Package Body Dimension Y B 4210 4235 4260 µm
Package Height C 825 885 945 µm
Ball Height C1 130 160 190 µm
Package Body Thickness C2 680 725 770 µm
Thickness of Glass Surface to Wafer C3 425 445 465 µm
Ball Diameter D 270 300 330 µm
Total Pin Count N 24
Pin Count X-axis N1 5
Pin Count Y-axis N2 6
Pins Pitch X-axis J1 620 µm
Pins Pitch Y-axis J2 620 µm
Edge-to-Pin Center Distance Analog X S1 623 653 683 µm
Edge-to-Pin Center Distance Analog Y S2 538 568 598 µm
Sensor Array Center

Figure 14 OV7670/OV7171 Sensor Array Center

A1 A2 A3 A4 A5

Package Center 2361.6 µm

(0,0)

1756.8 µm

Sensor
Array

Array Center
(201.8 µm, 486.38 µm)
OV7670/OV7171

TOP VIEW

NOTES: 1. This drawing is not to scale and is for reference only.

2. As most optical assemblies invert and mirror the image, the chip is typically mounted
with pins A1 to A5 oriented down on the PCB.
 Package Specifications

IR Reflow Ramp Rate Requirements

OV7670/OV7171 Lead-Free Packaged Devices

Note: For OVT devices that are lead-free, all part marking letters are
lower case

Figure 15 IR Reflow Ramp Rate Requirements

300.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
280.0

260.0

240.0

220.0

200.0

180.0
Temperature (∞C )

160.0

140.0

120.0

100.0

80.0

60.0

40.0

20.0
0.0 0.6 1.1 1.6 2.2 2.8 3.3 3.9
0.0
-22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369
Time (sec)

-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)

Table 7 Reflow Conditions

Condition Exposure
Average Ramp-up Rate (30°C to 217°C) Less than 3°C per second
> 100°C Between 330 - 600 seconds
> 150°C At least 210 seconds
> 217°C At least 30 seconds (30 ~ 120 seconds)
Peak Temperature 245°C
Cool-down Rate (Peak to 50°C) Less than 6°C per second
Time from 30°C to 255°C No greater than 390 seconds
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