LH28F008SC PDF

LH28F008SC 8M (1M × 8) Flash Memory
FEATURES 42-PIN CSP TOP VIEW
• High-Density Symmetrically-Blocked
1 2 3 4 5 6 7
Architecture
– Sixteen 64K Erasable Blocks A A5 A8 A11 VPP A12 A15 A17
• High-Performance B A4 A7 A10 VCC A13 NC A18

– 85 ns Read Access Time
C A6 A9 RP CE A14 A16 A19
• Enhanced Automated Suspend Options
– Byte Write Suspend to Read D A3 DQ1 NC VCC DQ4 DQ7 NC
– Block Erase Suspend to Byte Write
– Block Erase Suspend to Read E A2 A0 DQ3 GND DQ6 OE NC
• Enhanced Data Protection Features F A1 DQ0 DQ2 GND DQ5 RY/BY WE

– Absolute Protection with VPP = GND
– Flexible Block Locking
– Block Erase/Byte Write Lockout during 28F008SC-20
Power Transitions Figure 1. CSP 42-Pin Configuration

• Extended Cycling Capability
– 100,000 Block Erase Cycles 40-PIN TSOP TOP VIEW
– 1.6 Million Block Erase Cycles/Chip
• Low Power Management A19 1 40 NC
– Deep Power-Down Mode A18 2 39 NC
– Automatic Power Saving Mode Decreases A17 3 38 WE
ICC in Static Mode A16 4 37 OE

A15 5 36 RY/BY
• Automated Byte Write and Block Erase A14 6 35 DQ7
– Command User Interface A13 7 34 DQ6
– Status Register A12 8 33 DQ5
• SmartVoltage Technology CE 9 32 DQ4
– 3.3 V or 5 V VCC VCC 10 31 VCC
– 3.3 V, 5 V, or 12 V VPP VPP 11 30 GND

RP 12 29 GND
• SRAM - Compatible Write Interface A11 13 28 DQ3
• ETOX™ V Nonvolatile Flash Technology A10 14 27 DQ2
A9 15 26 DQ1
• Industry - Standard Packaging 16
A8 25 DQ0
– 42-Pin, .67 mm × 8 mm2 CSP Package 17 A0
A7 24
– 40-Pin, 1.2 mm × 10 mm × 20 mm A6 18 23 A1
TSOP (Type I) Package A5 19 22 A2
– 44-Pin, 600-mil, SOP Package A4 20 21 A3
28F008SC-1
Figure 2. TSOP 40-Pin Configuration
1
44-PIN SOP TOP VIEW New Features

The LH28F008SC SmartVoltage FlashFile memory
VPP 1 44 VCC maintains backwards-compatiblity with SHARP’S
RP 2 43 CE 28F008SA. Key enhancements over the 28F008SA
include:
A11 3 42 A12
A10 4 41 A13 • SmartVoltage Technology
A9 5 40 A14 • Enhanced Suspend Capabilities
A8 6 39 A15 • In-System Block Locking
A7 7 38 A16
Both devices share a compatible pinout, status reg-
A6 8 37 A17 ister, and software command set. These similarities
A5 9 36 A18 enable a clean upgrade from the 28F008SA to
A4 10 35 A19 LH28F008SC. When upgrading, it is important to note
NC 11 34 NC the following differences:
NC 12 33 NC • Because of new feature support, the two devices
A3 13 32 NC have different device codes. This allows for soft-
ware optimization.
A2 14 31 NC
A1 15 30 WE • VPPLK has been lowered from 6.5 V to 1.5 V to
support 3.3 V and 5 V block erase, byte write, and
A0 16 29 OE
lock-bit configuration operations. Designs that
DQ0 17 28 RY/BY
switch VPP off during read operations should make
DQ1 18 27 DQ7 sure that the VPP voltage transitions to GND.
DQ2 19 26 DQ6 • To take advantage of SmartVoltage technology,
DQ3 20 25 DQ5 allow VPP connection to 3.3 V or 5 V.
GND 21 24 DQ4
GND 22 23 VCC DESCRIPTION
The LH28F008SC is a high-performance 8M Smart-
28F008SC-2
Voltage FlashFile memory organized as 1M of 8 bits. The
Figure 3. SOP 44-Pin Configuration 1M of data is arranged in sixteen 64K blocks which are
individually erasable, lockable, and unlockable in-system.
INTRODUCTION The memory map is shown in Figure 5.
SHARP’S LH28F008SC FlashFile™ memory with SmartVoltage technology provides a choice of VCC
SmartVoltage technology is a high-density, low-cost, non- and VPP combinations, as shown in the Voltage Combi-
volatile, read/write storage solution for a wide range of nations Table, to meet system performance and power
applications. Its symmetrically-blocked architecture, flex- expectations. 3.3 V VCC consumes approximately one-
ible voltage and extended cycling provide for highly flex- fourth the power of 5 V VCC. But, 5 V VCC provides the
ible component suitable for resident flash arrays, SIMMs highest read performance. VPP at 3.3 V and 5 V elimi-
and memory cards. Its enhanced suspend capabilities pro- nates the need for a separate 12 V converter, while
vide for an ideal solution for code and data storage appli- VPP = 12 V maximizes block erase and byte write per-
cations. For secure code storage applications, such as formance. In addition to flexible erase and program volt-
networking, where code is either directly executed out of ages, the dedicated VPP pin gives complete data
flash or downloaded to DRAM, the LH28F008SC offers protection when VPP ≤ VPPLK.
three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software VCC and VPP Voltage Combinations
block locking. These alternatives give designers ultimate Offered by SmartVoltage Technology
control of their code security needs.
The LH28F008SC is manufactured on SHARP’s VCC VOLTAGE VPP VOLTAGE
0.4 µm ETOX™ V process technology. It comes in in- 3.3 V 3.3 V, 5 V, 12 V
dustry-standard packages: the 40-pin TSOP, ideal for
board constrained applications, and the rugged 44-pin 5V 5 V, 12 V
SOP. Based on the 28F008SA architecture, the
LH28F008SC enables quick and easy upgrades for
designs demanding the state-of-the art.
2
8M (1M × 8) Flash Memory LH28F008SC
DQ0 - DQ7
OUTPUT INPUT
BUFFER BUFFER
IDENTIFIER I/O LOGIC RP

REGISTER
OUTPUT
MULTIPLEXER DATA
STATUS REGISTER
REGISTER
CE
COMMAND WE
DATA
REGISTER OE
COMPARATOR
RP
Y-GATING
A0 - A19 INPUT WRITE STATE
BUFFER RY/BY
MACHINE
Y-DECODER
ADDRESS
LATCH PROGRAM/
...
16 64KB BLOCKS VPP

X-DECODER ERASE
VOLTAGE
SWITCH
ADDRESS
COUNTER
VCC
GND
28F008SC-3
Figure 4. LH28F008SC Block Diagram
Internal VCC and VPP detection Circuitry automati- Writing memory data is performed in byte increments
cally configures the device for optimized read and write typically within 6 µs (5 V VCC, 12 V VPP). Byte write sus-
operations. pend mode enables the system to read data or execute
A Command User Interface (CUI) serves as the in- code from any other flash memory array location.
terface between the system processor and internal op- Individual block locking uses a combination of bits,
eration of the device. A valid command sequence written sixteen block lock-bits and a master lock-bit, to lock and
to the CUI initiates device automation. An Internal Write unlock blocks. Block lock-bits gate block erase and byte
State Machine (WSM) automatically executes the algo-
write operations, while the master lock-bit gates block
rithms and timings necessary for block erase, byte write,
lock-bit modification. Lock-bit configuration operations
and lock-bit configuration operations.
(Set Block, Lock-Bit, Set Master Lock-Bit, and Clear
A block erase operation erases one of the device’s Block Lock-Bits commands) set and cleared lock-bits.
64K blocks typically within 1 second (5 V VCC, 12 V VPP)
independent of other blocks. Each block can be inde- The status register indicates when the WSM’s block
pendently erased 100,000 times (1.6 million block erases erase, byte write, or lock-bit configuration operation is
per device). Block erase suspend mode allows system finished.
software to suspend block erase to read or write data
from any other block.
3
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION
ADDRESS INPUTS: Inputs for addresses during read and write operations.
A0 - A19 INPUT
Addresses are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins
DQ0 - DQ7 INPUT/OUTPUT
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and
CE » INPUT sense amplifiers. CE » high deselects the device and reduces power consumption to
standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP » high enables normal operation. When driven low, RP» inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP» at VHH enables setting of the
RP » INPUT
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP » = VHH overrides block lock-bits thereby enabling block erase and byte write
operation to locked memeory blocks. Block erase, byte write, or lock-bit configuration
with VIH < RP » < VHH produce spurious results and should not be attempted.
OE » INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
WE INPUT
latched on the rising edge of the WE Pulse.
READY/BUSY: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY »/BY » high indicates that the WSM is ready for new commands, block erase is
RY »/BY » OUTPUT
suspended, and byte write is inactive, byte write is suspended, or the device is in
deep power-down mode. RY »/BY » is always active and does not float when the chip
is deselected or data outputs are disabled.
BLOCK ERASE/BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VLKO,
VPP SUPPLY memory contents cannot be altered. Block erase, byte write, and lock-bit configura-
tion with an invalid VPP (see DC Characteristics) produce spurious results and
should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 3.3 V or 5 V
operation. To switch from one voltage to another, ramp VCC down to GND and then
VCC SUPPLY ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see DC Characteristics) produce spurious results and should not be attempted.
GND SUPPLY GROUND: Do not float any pins
NC NO CONNECT: Lead is not internal connected; it may be driven or floated.
4
The RY »/BY » output gives an additional indicator of Commands are written using standard microproces-
WSM activity by providing both a hardware signal of sor write timings. The CUI contents serve as input to
status (versus software polling) and status masking the WSM, which controls the block erase, byte write,
(interrupt masking for background block erase, for and lock-bit configuration. The internal algorithms are
example). Status polling using RY »/BY » minimizes both regulated by the WSM, including pulse repetition, inter-
CPU overhead and system power consumption. When nal verification, and margining of data. Addresses and
low, RY /» BY » indicates that the WSM is performing a block data are internally latch during write cycles. Writing the
erase, byte write, or lock-bit configuration. RY »/BY » high appropriate command outputs array data, accesses the
indicates that the WSM is ready for a new command, identifier codes, or outputs status register data.
block erase is suspended (and byte write is inactive),
byte write is suspended, or the device is in deep power- Interface software that initiates and polls progress of
down mode. block erase, byte write, and lock-bit configuration can
The access time is 85 ns (tAVAV) over the commer- be stored in any block. This code is copied to and ex-
cial temperature range (0°C to +70°C) and VCC supply ecuted from system RAM during flash memory updates.
voltage range of 4.75 V - 5.25 V. At lower VCC voltages, After successful completion, reads are again possible
the access times are 90 ns (4.5 V - 5.5 V) and 120 ns via the Read Array command. Block erase suspend al-
(3.0 V - 3.6 V). lows sytem software to suspend a block. Byte write sus-
pend allows system software to suspend a byte write to
The Automatic Power Savings (APS) feature substan-
read data from any other flash memory array location.
tially reduces active current when the device is in static
mode (addresses not switching). In APS mode, the typi-
cal ICCR current is 1 mA at 5 V VCC.
When CE » and RP » pins are at VCC, the ICC CMOS
FFFFF
standby mode is enabled. When the RP » pin is at GND, 64KB BLOCK 15
deep power-down mode is enabled which minimizes F0000
EFFFF
power consumption and provides write protection dur- 64KB BLOCK 14
E0000
ing reset. A reset time (tPHQV) is required from RP » DFFFF
switching high until outputs are valid. Likewise, the de- 64KB BLOCK 13
D0000
vice has a wake time (tPHEL) from RP »-high until writes CFFFF
64KB BLOCK 12
to the CUI are recognized. With RP » at GND, the WSM C0000
is reset and the status register is cleared. BFFFF
64KB BLOCK 11
B0000
The device is available in 40-pin TSOP (Thin Small AFFFF
Outline Package, 1.2 mm thick) and 44-pin SOP (Small 64KB BLOCK 10
A0000
Outline Package). Pinouts are shown in Figures 1 and 2. 9FFFF
64KB BLOCK 9
90000
PRINCIPLES OF OPERATION 8FFFF
64KB BLOCK 8
The LH28F008SC SmartVoltage FlashFile memory 80000
7FFFF
includes an on-chip WSM to manage block erase, byte 64KB BLOCK 7
70000
write, and lock-bit configuration functions. It allows for: 6FFFF
100% TTL-level control inputs, fixed power supplies dur- 64KB BLOCK 6
60000
ing block erasure, byte write, and lock-bit configuration, 5FFFF
and minimal processor overhead with RAM-like inter- 64KB BLOCK 5
50000
face timings. 4FFFF
64KB BLOCK 4
After initial device power-up or return from deep 40000
power-down mode (see Bus Operations), the device 3FFFF
64KB BLOCK 3
defaults to read array mode. Manipulation of external 30000
memory control pins allow array read, standby, and out- 2FFFF
64KB BLOCK 2
put disable operations. 20000
1FFFF
Status register and identifier codes can be accessed 64KB BLOCK 1
10000
through the CUI independent of the VPP voltage. High 0FFFF
voltage on VPP enables successful block erasure, byte 64KB BLOCK 0
00000
writing, and lock-bit configuration. All functions associ-
ated with altering memory contents–block erase, byte 28F008SC-4
write, Lock-bit configuration, status, and identifier codes-
are accessed via the CUI and verified through the sta- Figure 4. Memory Map
tus register.
5
Data Protection Standby

Depending on the application, the system designer CE » at a logic-high level (VIH) places the device in
may choose to make the VPP power supply switchable standby mode which substantially reduces device power
(available only when memory block erases, byte writes, consumption. DQ0 - DQ7 outputs are placed in a high-
or lock-bit configurations are required) or hardwired to impedance state independent of OE .» If deselected dur-
VPPH1/2/3. The device accommodates either design prac- ing block erase, byte write, or lock-bit configuration, the
tice and encourages optimization of the processor- device continues functioning, and consuming
memory interface. active power until the operation completes.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, byte write,
Deep Power-Down
or lock-bit configuration command sequences, provides RP » at VIL initiates the deep power-down mode.
protection from unwanted operations even when high
voltage is applied to VPP. All write functions are disabled In read modes, RP -» low deselects the memory, places
when VCC is below the write lockout voltage VLKO or output drivers in a high-impedance state and turns off
when RP » is at VIL. The device’s block locking capability all internal circuits. RP » must be held low for a minimum
provides additional protection from inadvertent code or of 100 ns. Time tPHQV is required after return from power-
data alteration by gating erase and byte write down until initial memory access outputs are valid. Af-
operations. ter this wake-up interval, normal operation is restored.
The CUI is reset to read array mode and status register
is set to 80H.
BUS OPERATION
During block erase, byte write, or lock-bit configura-
The local CPU reads and writes flash memory
tion modes, RP »-low will abort the operation. RY »/BY »
in-system. All bus cycles to or from the flash memory
remains low until the reset operation is complete.
conform to standard microprocessor bus cycles.
Memory contents being altered are no longer valid; the
data may be partially erased or written. Time tPHWL is
Read required after RP » goes to logic-high (VIH) before an-
Information can be read from any block, identifier other command can be written.
codes, or status register independent of the VPP volt- As with any automated device, it is important to
age. RP » can be at either VIH or VHH. assert RP » during system reset. When the system comes
The first task is to write the appropriate read mode out of reset, it expects to read from the flash memory.
command (Read, Array, Read Identifier Codes, or Read Automated flash memories provide status information
Status Register) to the CUI. Upon initial device power- when accessed during block erase, byte write, or lock-
up or after exit from deep power-down mode, the de- bit configuration modes. If a CPU reset occurs with no
vice automatically resets to read array mode. Four flash memory reset, proper CPU initialization may not
control pins dictate the data flow in and out of the com- occur because the flash memory may be providing sta-
ponent: CE », OE », WE », and RP ». CE » and OE » must be tus information instead of array data. SHARP’s flash
driven active to obtain data at the outputs. CE » is the memories allow proper CPU initialization following a
device selection control, and when active enables the system reset through the use of the RP » input. In this
selected memory device. OE » is the data output application, RP » is controlled by the same RESET sig-
(DQ0 - DQ7) control and when active drives the selected nal that resets the system CPU.
memory data onto the I/O bus. WE » must be at VIH and
RP » must be at VIH or VHH. Figure 15 illustrates a read Read Identifier Codes Operation
cycle.
The read identifier codes operation outputs the manu-
facturer code, device code, block lock configuration
Output Disable codes for each block, and the master lock configuration
With OE » at a logic-high level (VIH), the device otuputs code (see Figure 5). Using the manufacturer and de-
are disabled. Output pins DQ0 - DQ7 are placed in a vice codes, the system CPU can automatically match
high-impedance state. the device with its proper algorithms. The block lock and
master lock configuration codes identify locked and
unlocked blocks and master lock-bit setting.
6
Write
FFFFF Writing commands to the CUI enable reading of
F0004
RESERVED FOR device data and identifier codes. They also control
FUTURE IMPLEMENTATION inspection and clearing of the status register. When
F0003 VPP = VPPH1/2/3, the CUI additionally controls block era-
F0002 BLOCK 15 LOCK CONFIGURATION CODE sure, byte write, and lock-bit configuration.
F0001 The Block Erase command requires appropriate com-
RESERVED FOR mand data and an address within the block to be erased.
FUTURE IMPLEMENTATION The Byte Write command requires the command and
F0000 BLOCK 15 address of the location to be written. Set Master and
Block Lock-Bit commands require the command and
...
...
(BLOCKS 2 THROUGH 14) address within the device (Master Lock) or block within
the device (Block Lock) to be locked. The Clear Block
1FFFF Lock-Bits command requires the command and address
RESERVED FOR
within the device.
10004
FUTURE IMPLEMENTATION
The CUI does not occupy an addressable memory
10003 location. It is written when WE » and CE » are active. The
10002 BLOCK 1 LOCK CONFIGURATION CODE address and data needed to execute a command are
10001
latched on the rising edge of WE » or CE » (whichever
goes high first). Standard microprocessor write timings
RESERVED FOR
FUTURE IMPLEMENTATION are used. Figures 16 and 17 illustrate WE » and CE » con-
10000 BLOCK 1 trolled write operations.
0FFFF
RESERVED FOR COMMAND DEFINITIONS
FUTURE IMPLEMENTATION
00004 When the VPP voltage ≤ VPPLK, Read operations
from the status register, identifier codes, or blocks are
00003 MASTER LOCK CONFIGURATION CODE enabled. Placing VPPH1/2/3 on VPP enables successful
block erase, byte write and lock-bit configuration
00002 BLOCK 0 LOCK CONFIGURATION CODE
operations.
00001 DEVICE CODE Device operations are selected by writing specific
commands into the CUI. The Command Definitions Table
00000 MANUFACTURER CODE defines these commands.
BLOCK 0
28F008SC-5 Read Array Command

Figure 5. Device Identifier Code Memory Map Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the Read
Array command. The device remains enabled for reads
until another command is written. Once the internal
WSM has started a block erase, byte write or lock-bit
configuration, the device will not recognize the Read
Array command until the WSM completes its operation
unless the WSM is suspended via an Erase Suspend
or Byte Write Suspend command. The Read Array com-
mand functions independently of the VPP voltage and
RP » can be VIH or VHH.
7
BUS OPERATIONS
MODE RP » CE » OE » WE ADDRESS VPP DQ0 - DQ7 RY »/BY » NOTE
Read VIH or VHH VIL VIL VIH X X DOUT X 1, 2, 3
Output Disable VIH or VHH VIL VIH VIH X X High-Z X 3
Standby VIH or VHH VIH X X X X High-Z X 3
Deep Power Down VIL X X X X X High-Z VOH 4
Read Identifier Codes VIH or VHH VIL VIL VIH See Figure 5 X Note 5 VOH
Write VIH or VHH VIL VIH VIL X X DIN X 3, 6, 7
NOTES:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for
VPPLK and VPPH1/2/3 voltages.
3. RY »/BY » is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when
the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode.
4. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
5. See Read Identifier Codes Command Section for read identifier code data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and VCC = VCC1/2/3.
Block erase, byte write, or lock-bit configuration with V IH < RP » < VHH produce spurious results and should not be attempted.
7. Refer to Command Definitions Table for valid DIN during a write operation.
8
Command Definitions9
BUS FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND CYCLES NOTE
REQ'D OPER.1 ADDRESS2 DATA3 OPER.1 ADDRESS2 DATA3
Read Array/Reset 1 Write X FFH

Read Identifier Codes ≥2 Write X 90H Read IA ID 4
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 Write BA 20H Write BA D0H 5
Byte Write 2 Write WA 40H or 10H Write WD 5, 6
Block Erase and Byte
1 Write X B0H WA 5
Write Suspend
Block Erase and Byte
1 Write X D0H 5
Write Resume
Set Block Lock-Bit 2 Write BA 60H Write BA 01H 7
Set Master Lock-Bit 2 Write X 60H Write X F1H 7
Clear Block Lock Bits 2 Write X 60H Write X D0H 8
NOTES:
1. Bus operations are defined in Bus Definition Table.
2. X = Any valid address within the device.
IA = Idendifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Status Register for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE » or CE » (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes.
See Read Identifier Code Command Section for read identifier code data.
5. If the block is locked, RP » must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte
write to locked block while RP » is VIH.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP » must be at VHH to set a block lock-bit. RP » must be at VHH to set the master lock-bit. If the master
lock-bit is not set, a block lock-bit can be set while RP » is VIH.
8. If the master lock-bit is set, RP » must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all
block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP » is VIH.
9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
9
Read Identifier Codes Command Clear Status Register Command

The identifier code operation is initiated by writing Status register bits SR.5, SR.4, SR.3 and SR.1 are
the Read Identifier Codes command. Following the com- set to '1' by the WSM and can only be reset by the Clear
mand write, read cycles from addresses shown in Fig- Status Register command. These bits indicate various
ure 5 retrieve the manufacturer, device, block lock failure conditions (see Status Register). By allowing sys-
configuration and master lock configuration codes (see tem software to reset these bits, several operations
Identifier Code Table for code values). To terminate the (such as cumulatively erasing or locking multiple blocks
operation, write another valid command. Like the Read or writing several bytes in sequence) may be performed.
Array command, the Read Identifier Codes command The status register may be polled to determine if an
functions independently of the VPP and RP » can be VIH error occurred during the sequence.
or VHH. Following the Read Identifier Codes command,
To clear the status register, the Clear Status Regis-
the following information can be read:
ter command (50H) is written. It functions independently
of the applied VPP Voltage. RP » can be VIH or VHH. This
Identifier Codes command is not functional during block erase or byte
write suspend modes.
CODE ADDRESS DATA
Block Erase Command
Manufacturer Code 00000 89
Erase is executed one block at a time and initiated
Device Code 00001 A6 by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This com-
Block Lock Configurations X00021 mand sequence requires appropriate sequencing and
an address within the block to be erased (erase changes
• Block is Unlocked DQ0 = 0
all block data to FFH). Block preconditioning, erase, and
• Block is Locked DQ0 = 1 verify are handled internally by the WSM (invisible to
the system). After the two-cycle block erase sequence
• Reserved for Future Use DQ1 - DQ7 is written, the device automatically outputs status reg-
ister data when read (see Figure 6). The CPU can
Master Lock Configuration 00003
detect block erase completion by analyzing the output
• Device is Unlocked DQ0 = 0 data of the RY »/BY » or status register bit SR.7.
• Device is Locked DQ0 = 1 When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
• Reserved for Future Use DQ1 - DQ7 detected, the status register should be cleared before
system software attempts corrective actions. The CUI
NOTE: remains in read status register mode until a new com-
1. X selects the specific block lock configuration code to be read.
mand is issued.
See Figure 5 for the device identifier code memory map.
This two-step command sequence of set-up followed
by execution ensures that block contents are not acci-
Read Status Register Command dentally erased. An invalid Block Erase command
sequence will result in both status register bits
The status register may be read to determine when
SR.4 and SR.5 being set to '1'. Also, reliable block era-
a block erase, byte write, or lock-bit configuration is com-
sure can only occur when V CC = V CC1/2/3 and
plete and whether the operation completed success-
VPP = VPPH1/2/3. In the absence of this high voltage,
fully. It may be read at any time by writing the Read
block contents are protected against erasure. If block
Status Register command. After writing this command,
erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5
all subsequent read operations output data from the
will be set to '1'. Successful block erase requires that
status register until another valid command is written.
the corresponding block lock-bit be cleared or, if set,
The status register contents are latched on the falling
that RP » = VHH. If block erase is attempted when the
edge of OE » or CE », whichever occurs. OE » or CE » must
corresponding block lock-bit is set and RP » = VIH, SR.1
toggle to VIH before further reads to update the status
and SR.5 will be set to '1'. Block erase operations with
register latch. The Read Status Register command func-
VIH < RP » < VHH produce spurious results and should
tions independently of the VPP voltage. RP » can be VIH
not be attempted.
or VHH.
10
Byte Write Command Byte Write Suspend Command Section), a byte write
operation can also be suspended. During a byte write
Byte write is executed by a two-cycle command
operation with block erase suspended, status register
sequence. Byte write setup (standard 40H or alternate
bit SR.7 will return to '0' and the RY »/BY » output will tran-
10H) is written, followed by a second write that speci-
sition to VOL. However, SR.6 will remain '1' to indicate
fies the address and data (latched on the rising edge of
block erase suspend status.
WE )» . The WSM then takes over, controlling the byte write
and write verify algorithms internally. After the byte write The only other valid commands while block erase is
sequence is written, the device automatically outputs suspended are Read Status Register and Block Erase
status register data when read (see Figure 7). The CPU Resume. After a Block Erase Resume command is writ-
can detect the completion of the byte write event by ten to the flash memory, the WSM will continue the block
analyzing the RY »/BY » pin or status register bit SR.7. erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY »/BY » will return to VOL. After
When byte write is complete, status register bit SR.4
the Erase Resume command is written, the device au-
should be checked. If byte write error is detected, the
tomatically outputs status register data when read (see
status register should be cleared. The internal WSM
Figure 8). VPP must remain at VPPH1/2/3 (the same VPP
verify only detects errors for '1's that do not success-
level used for block erase) while block erase is sus-
fully write to '0's. The CUI remains in read status regis-
pended. RP » must also remain at VIH or VHH (the same
ter mode until it receives another command.
RP » level used for block erase). Block erase cannot re-
Reliable byte writes can only occur when sume until byte write operations initiated during block
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of erase suspend have completed.
this high voltage, memory contents are protected against
byte writes. If byte write is attempted while VPP ≤ VPPLK, Byte Write Suspend Command
status register bits SR.4 and SR.5 will be set to '1'. Suc-
cessful byte write requires that the corresponding block The Byte Write Suspend command allows byte write
lock-bit be cleared or, if set, that RP » = VHH. If byte write interruption to read data in other flash memory loca-
is attempted when the corresponding block lock-bit is tions. Once the byte write process starts, writing the
set and RP » = VIH, SR.1 and SR.4 will be set to '1'. Byte Byte Write Suspend command resquests that the WSM
write operations with VIH < RP » < VHH produce spurious suspend the byte write sequence at a predetermined
results and should not be attempted. point in the algorithm. The device continues to output
status register data when read after the Byte Write Sus-
Block Erase Suspend Command pend command is written. Polling status register bits
SR.7 and SR.2 can determine when the byte write
The Block Erase Suspend command allows block- operation has been suspended (both will be set to '1').
erase interruption to read or byte-write data in another RY »/BY » will also transition to VOH. Specification tWHRH1
block of memory. Once the block-erase process starts, defines the byte write suspend latency.
writing the Block Erase Suspend command requests
At this point, a Read Array command can be written
that the WSM suspend the block erase sequence at a
to read data from locations other than that which is sus-
predetermined point in the algorithm. The device out-
pended. The only other valid commands while byte write
puts status register data when read after the Block Erase
is suspended are Read Status Register and Byte Write
Suspend command is written. Polling status register bits
Resume. After Byte Write Resume command is written
SR.7 and SR.6 can determine when the block erase
to the flash memory, the WSM will continue the byte
operation has been suspended (both will be set to '1').
write process. Status register bits SR.2 and SR.7 will
RY »/BY » will also transition to VOH. Specification tWHRH2
automatically clear and RY »/BY » will return to VOL. After
defines the block erase suspend latency.
the Byte Write Resume command is written, the device
At this point, a Read Array command can be written automatically outputs status register data when read
to read data from blocks other than that which is sus- (see Figure 9). VPP must remain at VPPH1/2/3 (the same
pended. A Byte Write command sequence can also be VPP level used for byte write) while in byte write sus-
issued during erase suspend to program data in other pend mode. RP » must also remain at VIH or VHH (the
blocks. Using the Byte Write Suspend command (see same RP » level used for byte write).
11
Set Block and Master Clear Block Lock-Bits Command

Lock-Bit Commands
All set block lock-bits are cleared in parallel via the
A flexible block locking and unlocking scheme is Clear Block Lock-Bits command. With the master lock-
enabled via a combination of block lock-bits and a mas- bit not set, block lock-bits can be cleared using only the
ter lock-bit. The block lock-bits gate program and erase Clear Block Lock-Bits command. If the master lock-bit
operations while the master lock-bit gates block-lock bit is set, clearing block lock-bits requires both the Clear
modification. With the master lock-bit not set, individual Block Lock-Bits command and VHH on the RP » pin. See
block lock-bits can be set using the Set Block Lock-Bit Write Protection Analysis Table for a summary of hard-
command. The Set Master Lock-Bit command, in con- ware and software white protection options.
junction with RP » = VHH, sets the master lock-bit. After
Clear block lock-bits operation is executed by a two-
the master lock-bit is set, subsequent setting of block
cycle command sequence. A clear block lock-bits setup
lock-bits requires both the Set Block Lock-Bit command
is first written. After the command is written, the device
and VHH on the RP » pin. See Write Protection Analysis
automatically outputs status register data when read
Table for a summary of hardware and software write
(see Figure 11). The CPU can detect completion of the
protection options.
clear block lock-bits event by analyzing the RY »/BY » Pin
Set block lock-bit and master lock-bit are executed output or status register bit SR.7.
by a two-cycle command sequence. The set block or
When the operation is complete, status register bit
master lock-bit setup along with appropriate block or
SR.5 should be checked. If a clear block lock-bit error is
device address is written followed by either the set block
detected, the status register should be cleared. The CUI
lock-bit confirm (and an address within the block to be
will remain in read status register mode until another
locked) or the set master lock-bit confirm (and any
command is issued.
device address). The WSM then controls the set lock-
bit algorithm. After the sequence is written, the device This two-step sequence of set-up followed by execu-
automatically outputs status register data when read tion ensures that block lock-bits are not accidentally
(see Figure 10). The CPU can detect the completion of cleared. An invalid Clear Block Lock-Bits command
the set lock-bit event by analyzing the RY »/BY » pin out- sequence will result in status register bits SR.4 and SR.5
put or status register bit SR.7. being set to “1”. Also, a reliable clear block lock bits
operation can only occur when VCC = VCC1/2/3 and
When the set lock-bit operation is complete, status
VPP = VPPH1/2/3. If a clear block lock-bits operation is
register, bit SR.4 should be checked. If an error is
attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set
detected, the status register should be cleared. The CUI
to '1'. In the absence of this high voltage, the block lock-
will remain in read status register mode until a new com-
bits content are protected against alteration. A success-
mand is issued.
ful clear block lock-bits operation requires that the master
This two-step sequence of set-up followed by execu- lock-bit is not set or, if the master lock-bit is set, that
tion ensures that lock-bits are not accidentally set. An RP » = VHH. If it is attempted with the master lock-bit set
invalid Set Block or Master Lock-Bit command will and RP » = VIH, SR.1 and SR.5 will be set to '1' and the
result in status register bits SR.4 and SR.5 being set operation will fail. A clear block lock-bits operation with
to '1'. Also, reliable operations occur only when VIH < RP » < VHH produce spurious results and should
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of not be attempted.
this high voltage, lock-bit contents are protected against
If a clear block lock-bits operation is aborted due to
alteration.
VPP or VCC transitioning out of valid range or RP »
A successful set block lock-bit operation requires that active transition, block lock-bit values are left in an
the master lock-bit be cleared or, if the master lock-bit undetermined state. A repeat of clear block lock-bits is
is set, that RP » = VHH. If it is attempted with the master required to initialize block lock-bit contents to known
lock-bit set and RP » = VIH, SR.1 and SR.4 will be set to value. Once the master lock-bit is set, it cannont be
'1' and the operation will fail. Set block lock-bit opera- cleared.
tions while VIH < RP » < VHH produce spurious results
and should not be attempted. A successful set master
lock-bit operation requires that RP » = VHH. If it is at-
tempted with RP » = VIH, SR.1 and SR.4 will be set to '1'
and the operation will fail. Set master lock-bit opera-
tions with VIH < RP » < VHH produce spurious results and
should not be attempted.
12
Write Protection Alternatives

MASTER BLOCK
OPERATION RP# EFFECT
LOCK-BIT LOCK-BIT
0 VIH or VHH Block Erase and Byte Write Enabled.

Block Erase or
X VIH Block is locked. Block Erase and Byte Write Disabled.
Byte Write 1
VHH Block Lock-Bit Override. Block Erase and Byte Write Enabled.
0 X VIH or VHH Set Block Lock-Bit Enabled.

Set Block
VIH Master Lock-Bit is Set. Set Block Lock-Bit Disabled.
Lock Bit 1 X
VHH Master Lock-Bit Override. Set Block Lock-Bit Enabled.
Set Master VIH Set Master Lock-Bit Disabled.

X X
Lock-Bit VHH Set Master Lock-Bit Enabled.
0 X VIH or VHH Clear Block Lock-Bits Enable.

Clear Block
VIH Master Lock-Bit is Set. Clear Block Lock-Bits Disabled.
Lock-Bits 1 X
VHH Master Lock-Bit Override. Clear Block Lock-Bits Enabled.
Status Register Definition
WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R
7 6 5 4 3 2 1 0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS 1. Check RY »/BY » or SR.7 to determine block erase, byte
1 = Ready write, or lock-bit configuration completion. SR.6 - SR.0 are
0 = Busy invalid while SR.7 = '0'.
SR.6 = ERASE SUSPEND STATUS 2. If both SR.5 and SR.4 are '1's after a block erase or lock-
1 = Block Erase Suspended bit configuration attempt, an improper command sequence
0 = Block Erase in Progress/Completed was entered.
3. SR.3 does not provide a continuous indication of VPP level.
SR.5 = ERASE AND CLEAR LOCK-BIT STATUS The WSM interrogates and indicates the VPP level only
1 = Error in Block Erasure or Clear Lock-Bits after Block Erase, Byte Write, Set Block/Master Lock-Bit,
0 = Successful Block Erase or Clear Lock-Bits or Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to report accurate feedback only when
SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS VPP = VPPH1/2/3.
1 = Error in Byte Write or Set Master/Block Lock Bit
0 = Successful Byte Write or Set Master/Block 4. SR.1 does not provide a continuous indication of master
0 = Lock-Bit and block lock-bit values. The WSM interrogates the master
lock-bit, block lock-bit, and RP » only after Block Erase, Byte
SR.3 = VPP STATUS (VPPS) Write, or Lock-Bit configuration command sequences. It
1 = VPP Low Detect, Operation Abort informs the system, depending on the attempted operation,
0 = VPP OK if the block lock-bit is set, master lock-bit is set, and/or RP »
is not VHH. Reading the block lock and master lock configu-
SR.2 = BYTE WRITE SUSPEND STATUS ration codes after writing the Read identifier Codes com-
1 = Byte Write Suspended mand indicates master and block lock-bit status.
0 = Byte Write in Progress/Completed
5. SR.0 is reserved for future use and should be masked out
when polling the status register.
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or
1 = RP » Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
13
START BUS
COMMAND COMMENTS
OPERATION
WRITE 20H Write Erase Data = 20H

BLOCK ADDRESS Setup Addr = Within block to be
erased
WRITE D0H Write Erase Data = D0H
BLOCK ADDRESS
Confirm Addr = Within block to be
erased
READ STATUS
REGISTER Read Status Register Data
NO SUSPEND BLOCK
ERASE LOOP Standby Check SR.7
1 = WSM Ready
0 SUSPEND YES 0 = WSM Busy
SR.7 = BLOCK
ERASE? Repeat for subsequent block erasures.
1
Full status check can be done after each block erase or
FULL STATUS after a sequence of block erasures.
CHECK IF DESIRED
Write FFH after the last operation to place
device in read array mode.
BLOCK ERASE
COMPLETED
FULL STATUS CHECK PROCEDURE
STATUS REGISTER BUS

DATA COMMAND COMMENTS
OPERATION
(see above)
Standby Check SR.3
1 = VPP Low Detect
1 VPP RANGE Standby Check SR.1
SR.3 =
ERROR 1 = Device Protect Detect
RP = VIH Block Lock-Bit is Set
0 Only required for systems
implemening lock-bit
configuration
1 DEVICE
SR.1 = PROTECT Standby Check SR.4, 5
ERROR Both 1 = Command Sequence
Error
0
Standby Check SR.5
COMMAND 1 = Block Erase Error
1
SR.4, 5 = SEQUENCE
ERROR SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
0
before full status is checked.
If error is detected, clear the Status Register before attempting

1 BLOCK ERASE retry or other error recovery.
SR.5 =
ERROR
BLOCK ERASE
SUCCESSFUL
28F008SC-6
Figure 6. Automated Block Erase Flowchart
14
START BUS
COMMAND COMMENTS
OPERATION
WRITE 40H Write Setup Data = 40H

ADDRESS Byte Write Addr = Location to be written
Write Byte Data = Data to be written

WRITE BYTE DATA Write Addr = Location to be written
AND ADDRESS
Read Status Register Data

READ STATUS
REGISTER Standy Check SR.7
NO ERASE SUSPEND 1 = WSM Ready
WRITE LOOP 0 = WSM Busy
0 SUSPEND YES
SR.7 = BYTE Repeat for subsequent byte writes.
WRITE?
SR full status check can be done after each byte write or
1 after a sequence of byte writes.
FULL STATUS Write FFH after the last byte write operation to place
CHECK IF DESIRED
device in read array mode.
BYTE WRITE
COMPLETED
READ STATUS BUS

REGISTER DATA COMMAND COMMENTS
OPERATION
(see above)
Standby Check SR.3
1 = VPP Low Detect
SR.3 =
RP = VIH Block Lock-Bit is Set
0 Only required for systems
implemening lock-bit
configuration
1 DEVICE
SR.1 = PROTECT Standby Check SR.4
ERROR 1 = Data Write Error
0
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple locations are written
1 BYTE WRITE
SR.4 =
ERROR
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
BYTE WRITE
SUCCESSFUL
28F008SC-7
Figure 7. Automated Byte Write Flowchart
15
START BUS COMMAND COMMENTS

OPERATION
Write Erase Data = B0H

WRITE B0H Suspend Addr = X
Addr = X
READ
STATUS REGISTER Standby Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby Check SR.6
0 1 = Erase Suspended
SR.7 = 0 = Erase Completed
Write Erase D = D0H
1 Resume Addr = X
0 BLOCK
SR.6 =
ERASE COMPLETED
Read READ or Byte Write

BYTE
WRITE ?
Read Byte
Array Data NO Write Loop
DONE ?
YES
WRITE D0H WRITE FFH
BLOCK READ ARRAY DATA

ERASE RESUMED
28F008SC-8
Figure 7. Block Erase Suspend/Resume Flowchart
16
START BUS COMMAND COMMENTS

OPERATION
Write Byte Write Data = B0H

WRITE B0H
Suspend Addr = X

READ Addr = X
STATUS REGISTER
Standby Check SR.7

1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Standby Check SR.2
1 = Byte Write Suspended
1 0 = Byte Write Completed
Write Read Data = FFH

Array Addr = X
0 BYTE WRITE
SR.2 =
COMPLETED
Read Read Array locations other
than that being written.
1
Write Byte Write Data = D0H
WRITE FFH Resume Addr = X
READ ARRAY DATA
DONE NO
READING
YES
WRITE D0H WRITE FFH
BYTE READ ARRAY DATA

WRITE RESUMED
28F008SC-9
Figure 9. Byte Write Suspend/Resume Flowchart
17
START BUS
COMMAND COMMENTS
OPERATION
Write Set Data = 60H

WRITE 60H
BLOCK/DEVICE ADDRESS Block/Master Addr = Block Address (Block),
Lock-Bit Setup Device Address (Master)
Write Set Data = 01H (Block)

WRITE 01H/F1H Block or Master F1H (Master)
BLOCK/DEVICE ADDRESS Lock-Bit Confirm Addr = Block Address (Block),
Device Address (Master)
READ STATUS REGISTER

Standby Check SR.7

1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Repeat for subsequent lock-bit set operations.
1 Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
FULL STATUS
CHECK IF DESIRED Write FFH after the last lock-bit set operation to place device
in read array mode.
SET LOCK-BIT
COMPLETED
READ STATUS BUS

OPERATION
(see above)
Standby Check SR.3
1 = VPP Error Detect

SR.3 =
RP = VIH
0 (Set Master Lock-Bit Operation)
RP = VIH, Master Lock-Bit is Set
(Set Block Lock-Bit Operation)
1 DEVICE
SR.1 = PROTECT Standby Check SR.4, 5
ERROR
Both 1 = Command
0 Sequence Error
Standby Check SR.4

1 COMMAND 1 = Set Lock-Bit Error
SR.4, 5 = SEQUENCE
ERROR
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
0 Register command in cases where multiple lock-bits are set
1 SET LOCK-BIT If error is detected clear the Status Register before attempting
SR.4 =
ERROR retry or other error recovery.
SET LOCK-BIT
SUCCESSFUL
28F008SC-10
Figure 10. Set Block and Master Lock-Bit Flowchart
18
START BUS
COMMAND COMMENTS
OPERATION
Write Clear Block Data = 60H

WRITE 60H
Lock-Bits Setup Addr = X
Write Clear Block Data = D0H

WRITE D0H Lock-Bits Addr = X
Confirm
READ STATUS REGISTER
Standby Check SR.7
1 = WSM Ready
0 = WSM Busy
0
SR.7 = Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
FULL STATUS
CHECK IF DESIRED
CLEAR BLOCK
LOCK-BITS COMPLETE
READ STATUS BUS

OPERATION
(see above)
Standby Check SR.3
1 = VPP Error Detect

SR.3 =
RP = VIH, Master Lock-Bit is Set
0
Standby Check SR.4, 5
Both 1 = Command
DEVICE
1
PROTECT
Sequence Error
SR.1 =
ERROR
Standby Check SR.5
YES 1 = Clear Block Lock-Bit Error
COMMAND SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
1 Register command.
SR.4, 5 = SEQUENCE
ERROR
If error is detected, clear the Status Register before attemping
retry or other error recovery.
1 CLEAR BLOCK
SR.5 = LOCK-BITS ERROR
YES
CLEAR BLOCK
LOCK-BITS
SUCCESSFUL
28F008SC-11
Figure 11. Clear Block Lock-Bits Flowchart
19
DESIGN CONSIDERATIONS VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target
Three-Line Output Control system requires that the printed circuit board designer
The device will often be used in large memory pay attention to the VPP Power supply trace. The VPP
arrays. SHARP provides three control inputs to accom- pin supplies the memory cell current for byte writing and
modate multiple memory connections. Three-line block erasing. Use similar trace widths and layout con-
control provides for: siderations given to the VCC power bus. Adequate VPP
supply traces and decoupling will decrease VPP voltage
• Lowest possible memory power dissipation spikes and overshoots.
• Complete assurance that data bus contention will
not occur. VCC, VPP, RP » Transitions
To use these control input efficiently, an address Block erase, byte write and lock-bit configuration are
decoder should enable CE » while OE » should be connected not guaranteed if VPP falls outside of a valid VPPH1/2/3
to all memory devices and the system’s READ control line. range, VCC falls outside of a valid VCC1/2/3 range, or
This assures that only selected memory devices have ac- RP » ≠ VIH or VHH. If VPP error is detected, status register
tive outputs while deselected memory devices are in bit SR.3 is set to '1' along with SR.4 or SR.5,
standby mode. RP » should be connected to the system depending on the attempted operation. If RP » transitions
POWERGOOD signal to prevent unintended writes dur- to VIL during block erase, byte write, or lock-bit configu-
ing system power transitions. POWERGOOD should also ration, RY »/BY » will remain low until the reset operation
toggle during system reset. is complete. Then, the opration will abort and the
device will enter deep power-down. The aborted opera-
RY /» BY » and Block Erase, Byte Write, and tion may leave data partially altered. Therefore, the com-
Lock-Bit Configuration Polling mand sequence must be repeated after normal
operation is restored. Device power-off or RP » transiitions
RY »/BY » is a full CMOS output that provides a hard-
to VIL clear the status register.
ware method of detecting block erase, byte write and
block-bit configuration completion. It transitions low af- The CUI latches commands issued by system soft-
ter lock erase, byte write, or lock-bit configuration com- ware and is not altered by VPP or CE » transitions or WSM
mands and returns to VOH when the WSM has finished actions. Its state is read array mode upon power-up,
executing the internal algorithm. after exit from deep power-down or after VCC transitions
below VLKO.
RY »/BY » can be connected to an interrupt input of the
system CPU or controller. It is active at all times. After block erase, byte write, or lock-bit configura-
RY »/BY » is also VOH when the device is in block erase tion, even after VPP transitions down to VPPLK, the CUI
suspend (with byte write inactive), byte write suspend must be placed in read array mode via the Read Array
or deep power-down modes. command if subsequent access to the memory array is
desired.
Power Supply Decoupling
Power-Up/Down Protection
Flash memory power switching characteristics
require careful device decoupling. System designers are The device is designed to offer protection against
interested in three supply current issues; standby cur- accidental block erasure, byte writing, or lock-bit con-
rent levels, active current levels and transient peaks pro- figuration during power transitions. Upon power-up, the
duced by falling and rising edges of CE » and OE » . device is indifferent as to which power supply (VPP or
Transient current magnitudes depend on the device out- VCC) powers-up first. Internal circuitry resets the CUI to
puts’ capacitive and inductive loading. Two-line control read array mode at power-up.
and proper decoupling capacitor selection will suppress
A system designer must guard against spurious
transient voltage peaks. Each device should have a
writes for VCC voltages above VLKO when VPP is active.
0.1 µF ceramic capacitor connected between its VCC
Since both WE » and CE » must be low for a command
and GND and between its VPP and GND. These high-
write, driving either to VIH will inhibit writes. The CUI’s
frequency, low inductance capacitors should be placed
two-step command sequence archiecture provides
as close as possible to package leads. Additionally, for
added level of protection against data alteration.
every eight devices, a 4.7 µF electrolytic capacitor
should be placed at the array’s power supply connec- In-system block lock and unlock capability prevents
tion betweenV CC and GND. The bulk capacitor will over- inadvertent data alteration. The device is disabled while
come voltage slumps caused by PC board trace RP » = VIL regardless of its control inputs state.
inductance.
20
Power Dissipation NOTICE: This datasheet contains information on

products in the design phase of development. Do not
When designing portable systems, designers must
finalize a design with this information. Revised informa-
consider battery power consumption not only during
tion will be published when the product is available.
device operation, but also for data retention during sys-
Veryify with your local SHARP sales office that you have
tem idle time. Flash memory’s nonvolatility increases
the latest datasheet before finalizing a design.
usable battery life because data is retained when sys-
tem power is removed. *WARNING: Stressing the device beyond the “Abso-
lute Maximum Ratings” may cause permanent damage.
In addition, deep power-down mode ensures
These are stress ratings only. Operation beyond the
extremely low power consumption even when system
“Operating Conditions” is not recommended and ex-
power is applied. For example, portable computing prod-
tended exposure beyond the “Operating Conditions” may
ucts and other power sensitive applications that use an
affect device reliability.
array of devices for solid-state storage can consume
negligible power by lowering RP » to VIL standby or sleep NOTES:
modes. If access is again needed, the devices can be 1. Operating temperature is for commercial product defined by
this specification.
read following the tPHQV and tPHWL wake-up cycles re- 2. All specified voltages are with respect to GND. Minimum DC
quired after RP » is first raised to VIH. See AC Character- voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP
istics - Read Only and Write Operations and Figures 16 pins. During transitions, this level may undershoot to -2.0 V for
and 17 for more information. periods < 20 ns. Maximum DC voltage on input/output pins and
VCC is VCC + 5.0 V which, during transitions, may overshoot to
VCC + 2.0 V for periods < 20 ns.
ELECTRICAL SPECIFICATIONS 3. Maximum DC voltage on VPP and RP » may overshoot to
+14.0 V for periods < 20 ns.
Absolute Maximum Ratings* 4. Output shorted for no more than on second. No more than one
output shorted at a time.
Commercial Operating Temperature
during Read, Block Erase, Byte Write,
and Lock-Bit Configuration ............... 0°C to +70°C1
Temperature under Bias ...................... -10°C to +80°C
Storage Temperature: ......................... 65°C to +125°C
Voltage On Any Pin
(except VCC, VPP and RP ») ................ -2 V to +7.0 V2
VCC Supply Voltage ........................... -2.0 V to +7.0 V2
VPP Update Voltage during Block Erase,
Byte Write,and Lock-Bit
Configuration ............................ -2.0 V to +14.0 V2, 3
RP » Voltage with Respect to GND
during Lock-Bit Configuration
Operations ...............................-2.0 V to +14.0 V2, 3
Output Short Circuit Current .......................... 100 mA4
Operating Conditions
Temperature and VCC Operating Conditions
SYMBOL PARAMETER MIN. MAX. UNIT TEST CONDITION
TA Operating Temperature 0 +70 °C Ambient Temperature
VCC1 VCC Supply Voltage (3.3 V ± 0.3 V) 3.0 3.6 V
VCC2 VCC Supply Voltage (5 V ± 5%) 4.75 5.25 V
VCC3 VCC Supply Voltage (5 V ± 10%) 4.50 5.50 V
21
Capacitance
TA = +25°C, f = 1 MHz
SYMBOL PARAMETER TYP. MAX. UNITS CONDITIONS
CIN Input Capacitance 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
AC INPUT/OUTPUT TEST CONDITIONS
3.0 1.3 V
INPUT 1.5 TEST POINTS 1.5 OUTPUT
0.0
1N914
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
RL = 3.3 kΩ
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns. 28F008SC-12 DEVICE
UNDER OUT
Figure 12. Transient Input/Output Reference TEST
Waveform for VCC = 3.3 V ±0.3 V and VCC = 5 V ±5% CL
(High Speed Testing Configuration)
NOTE: CL Includes Jig Capacitance

28F008SC-14
2.4
2.0 2.0
INPUT TEST POINTS OUTPUT Figure 14. Transient Equivalent
0.45 0.8 0.8
Testing Load Circuit
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL) Test Configuration Capacitance
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise Loading Value
and fall times (10% to 90%) < 10 ns.
28F008SC-13
TEST CONFIGURATION CL (pF)

Figure 13. Transient Input/Output Reference
Waveform for VCC = 5 V ±10% VCC = 3.3 V ± 0.3 V 50
(Standard Testing Configuration)
VCC = 5 V ± 0.5% 30
VCC = 5 V ± 10% 100
22
DC CHARACTERISTICS
VCC = 3.3 V VCC = 5 V
SYM. PARAMETER UNIT TEST CONDITIONS NOTE
TYP. MAX. TYP. MAX.
ILI Input Load Current ±0.5 ±1 µA VCC = VCC MAX., VIN = VCC or GND 1
ILO Output Leakage Current ±0.5 ±10 µA VCC = VCC MAX., VOUT = VCC or GND 1
CMOS Inputs, VCC = VCC MAX.

100 100 µA
CE » = RP » = VCC ±0.2 V
ICCS VCC Standby Current 1, 3, 6
TTL Inputs, VCC = VCC MAX.
2 2 mA
CE » = RP » = VIH
VCC Deep Power-Down RP » = GND ±0.2 V IOUT

ICCD 10 10 µA 1
Current (RY »/BY ») = 0 mA
CMOS Inputs VCC = VCC MAX.,
12 35 mA CE » = GND, f = 5 MHz (3.3 V),
f = 8 MHz (5 V), IOUT = 0 mA
ICCR VCC Read Current 1, 5, 6
TTL Inputs, VCC = VCC MAX.,
14 50 mA CE » = VIH, f = 5 MHz (3.3 V),
f = 8 MHz, (5 V) IOUT = 0 mA
17 mA VPP = 3.3 V ±0.3 V

VCC Byte Write or Set
ICCW 17 35 mA VPP = 5.0 V ±10% 1, 7
Lock-Bit Current
12 30 mA VPP = 12.0 V ± 5%
17 mA VPP = 3.3 V ±0.3 V

VCC Block Erase or
ICCE Clear Block Lock-Bits 17 30 mA VPP = 5.0 V ±10% 1, 7
Current
12 25 mA VPP = 12.0 V ±5%
VCC Byte Write or

ICCWS
Block Erase Suspend 6 10 mA CE » = VIH 1, 2
ICCES
Current
IPPS VPP Standby or Read ±15 ±15 µA VPP ≤ VCC

1
IPPR Current 200 200 µA VPP > VCC
VPP Deep Power-Down

IPPD 5 5 µA RP » = GND ± 0.2V 1
Current
40 mA VPP = 3.3 V ± 0.3 V

VPP Byte Write or Set
IPPW 40 40 mA VPP = 5.0 V ±10% 1, 7
Lock-Bit Current
15 15 mA VPP = 12.0 V ±5%
20 mA VPP = 3.3 V ± 0.3 V

VPP Block Erase or
IPPE 20 20 mA VPP = 5.0 V ± 105 1, 7
Clear Lock-Bit Current
15 15 mA VPP = 12.0 V ±5%
VPP Byte Write or
IPPWS
Block Erase Suspend 200 200 µA VPP = VPPH1/2/3 1
IPPES
Current
23
DC CHARACTERISTICS (Continued)
VCC = 3.3 V VCC = 5 V
SYM. PARAMETER UNIT TEST CONDITIONS NOTE
MIN. MAX. MIN. MAX.
VIL Input Low Voltage -0.5 0.8 -0.5 0.8 V 7
VIH Input High Voltage 2.0 VCC + 0.5 2.0 VCC + 0.5 V 7
VCC = VCC MIN.,

VOL Output Low Voltage 0.4 0.45 V 3, 7
IOL = 5.8 mA
Output High Voltage VCC = VCC MIN.,
VOH1 2.4 2.4 V 3, 7
(TTL) IOH = 2.5 mA
VCC = VCC MIN.,
0.85 VCC 0.85 VCC V 4, 7
Output High Voltage IOH = 2.5 µA
VOH2
(CMOS) VCC = VCC MIN.,
VCC - 0.4 VCC - 0.4 V
IOH = 100 µA
VPP Lockout during
VPPLK 1.5 1.5 V
Normal Operations
VPP during Byte Write,
VPPH1 Block Erase, or Lock- 3.0 3.6 V
Bit Operations
VPPH2 Block Erase, or Lock- 4.5 5.5 4.5 5.5 V
Bit Operations
VPPH3 Block Erase, or Lock- 11.4 12.6 11.4 12.6 V
Bit Operations
VLKO VCC Lockout Voltage 2.0 2.0 V
Set Master Lock-Bit

VHH RP » Unlock Voltage 11.4 12.6 11.4 12.6 V Override Master and 8
Block Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact
SHARP’s Application Support Hotline or your local sales office for information about typical specifications.
2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device’s current
draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY »/BY ».
4. Block erases, byte writes, and lock-bit configurations are inhibited when V PP ≤ VPPLK, and not guaranteed in the range between VPPLK
(MAX.) and VPPH1(MIN.), between V PPH1(MAX.) and VPPH2 (MIN.), between VPPH2 (MAX.) and VPPH3 (MIN.), and above VPPH3 (MAX.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5 V VCC and 3 mA at 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
7. Sampled, but not 100% tested.
8. Master lock-bit set operations are inhibited when RP » = VIH. Block lock-bit configuration operations are inhibited when the master lock
bit is set and RP » = VIH. Block erases and byte writes are inhibited when the corresponding block-lock bit is set and RP » = VIH.
Block erase, byte write, and lock-bit configuration operations are not guaranteed with V IH < RP » < VHH.
24
AC CHARACTERISTICS - Read Only Operations1

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
LH28F008SC-120 LH28F008SC-150
SYMBOL PARAMETER UNIT NOTE
MIN. MAX. MIN. MAX.
tAVAV Read Cycle Time 120 150 ns
tAVQV Address to Output Delay 120 150 ns
tELQV CE » to Output Delay 120 150 ns 2
tPHQV RP » High to Output Delay 600 600 ns
tGLQV OE » to Output Delay 50 55 ns 2
tELQX CE » to Output in Low Z 0 0 ns 3
tEHQZ CE » High to Output in High Z 55 55 ns 3
tGLQX CE » to Output in Low Z 0 0 ns 3
tGHQZ OE » High to Output in High Z 20 25 ns 3
Output Hold from Addresses, CE »

tOH 0 0 ns 3
or OE » change, whichever is first
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
LH28F00SC-855 LH28F00SC-906 LH28F00SA-1206

SYMBOL PARAMETER VCC ± 5% VCC ± 10% VCC ± 10% UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX.
tAVAV Read Cycle Time 85 90 120 ns
tAVQV Address to Output Delay 85 90 120 ns
tELQV CE » to Output Delay 85 90 120 ns 2
tPHQV RP » High to Output Delay 400 400 400 ns
tGLQV OE » to Output Delay 40 45 50 ns 2
tELQX CE » to Output in Low Z 0 0 0 ns 3
tEHQZ CE » High to Output in High Z 55 55 55 ns 3
tGLQX CE » to Output in Low Z 0 0 0 ns 3
tGHQZ OE » High to Output in High Z 10 10 15 ns 3
Output Hold from Addresses, CE »

tOH 0 0 0 ns 3
or OE » change, whichever is first
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE » may be delayed to to tELQV - tGLQV after the falling edge of CE » without inpact on tELQV.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing
characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing
characteristics.
25
DEVICE AND
ADDRESS DATA
STANDBY SELECTION VALID
VIH
...
ADDRESSES (A) ADDRESSES STABLE
VIL ...
tAVAV
VIH
CE (E)
VIL ...
tAVEL tEHQZ
VIH
OE (G)
VIL ...
tGHQZ
VIH
...
WE (W)
VIL
tGLQV
tELQV
tGLQX tOH
tELQX
...
DATA (D/Q) VOH HIGH-Z HIGH-Z
VALID OUTPUT
(DQ0 - DQ7) V
OL ...
tAVQV
...
VCC
tPHQV
VIH ...
RP (P) VIL
28F008SC-15
Figure 15. AC Waveforms for Read Operations
26
AC CHARACTERISTICS - Write Operations1

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
LH28F008SC-120 LH28F008SC-150
MIN. MAX. MIN. MAX.
tAVAV Write Cycle Time 120 150 ns
tPHWL RP » High Recovery to WE Going Low 1 1 µs 2
tELWL CE » Setup to WE Going Low 10 10 ns
tWLWH WE Pulse Width 50 50 ns
tPHHWH RP » VHH Setup to WE Going High 100 100 ns 2
tVPWH VPP Setup to WE Going High 100 100 ns 2
tAVWH Address Setup to WE Going High 50 50 ns 3
tDVWH Data Setup to WE Going High 50 50 ns 3
tWHDX Data Hold from WE High 5 5 ns
tWHAX Address Hold from WE High 5 5 ns
tWHEH CE » Hold from WE High 10 10 ns
tWHWL WE Pulse Width High 30 30 ns
tWHRL WE High to RY »/BY » Going Low 100 100 ns
tWHGL Write Recovery before Read 0 0 ns
tQVVL VPP Hold from Valid SRD, RY »/BY » High 0 0 ns 2, 4
tQVPH RP » VHH Hold from Valid SRD, RY »/BY » High 0 0 ns 2, 4
NOTE:
1. See 5 V VCC AC Characteristics - Write Operations for Notes 1 through 5.
27
AC CHARACTERISTICS - Write Operations1

VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
LH28F008SC-856 LH28F008SC-907 LH28F008SC-1208

tAVAV Write Cycle Time 85 90 120 ns
RP » High Recovery to WE
tPHWL 1 1 1 µs 2
Going Low
tELWL CE » Setup to WE Going Low 10 10 10 ns
tWLWH WE Pulse Width 40 40 40 ns
RP » VHH Setup to WE
tPHHWH 100 100 100 ns 2
Going High
VPP Setup to WE
tVPWH 100 100 100 ns 2
Going High
Address Setup to WE
tAVWH 40 40 40 ns 3
Going High
Data Setup to WE
tDVWH 40 40 40 ns 3
Going High
tWHDX Data Hold from WE High 5 5 5 ns
Address Hold from

tWHAX 5 5 5 ns
WE High
tWHEH CE » Hold from WE High 10 10 10 ns
tWHWL WE Pulse Width High 30 30 30 ns
WE High to RY »/BY » Going

tWHRL 90 90 ns
Low
Write Recovery before

tWHGL 0 0 0 ns
Read
VPP Hold from Valid SRD,

tQVVL 0 0 0 ns 2, 4
RY »/BY » High
RP » VHH Hold from Valid

tQVPH 0 0 0 ns 2, 4
SRD, RY »/BY » High
NOTES:
1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are
the same as during read-only operations. Refer to AC Characteristics for read-only operations.
3. Refer to Command Definitions Table for valid A IN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP » should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)
for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characters.
28
1 2 3 4 5 6
VIH
ADDRESSES (A) AIN AIN
VIL
tAVAV tAVWH
tWHAX
VIH
CE (E)
VIL
tELWL
tWHEH tWHGL
VIH
OE (G)
VIL
tWHWL tWHQV1, 2, 3, 4
VIH
WE (W)
VIL
tWLWH
tDVWH
tWHOX
VIH HIGH-Z VALID

DATA (D/Q) DIN DIN DIN
VIL SRD
tPHWL tWHPL
VIH
RY/BY (R)
VIL
tPHHWH tQVPH
VHH
RP (P) VIH
VIL
tVPWH tQVVL
VPPH3, 2, 1
VPP (V) VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write set-up.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
008SC-16
Figure 16. AC Waveforms for WE » Controlled Write Operations
29
ALTERNATIVE CE » - Controlled Writes1

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
LH28F008SC-120 LH28F008SC-150
MIN. MAX. MIN. MAX.
tAVAV Write Cycle Time 120 150 ns
tPHEL RP » High Recovery to CE » Going Low 1 1 µs 2
tWLEL WE Setup to CE »# Going Low 0 0 ns
tELEH CE » Pulse Width 70 70 ns
tPHHEH RP » VHH Setup to CE » Going High 100 100 ns 2
tVPEH VPP Setup to CE » Going High 100 100 ns 2
tAVEH Address Setup to CE » Going High 50 50 ns 3
tDVEH Data Setup to CE » Going High 50 50 ns 3
tEHDX Data Hold from CE » High 5 5 ns
tEHAX Address Hold from CE » High 5 5 ns
tEHWH WE Hold from CE » High 0 0 ns
tEHEL CE » Pulse Width High 25 25 ns
tEHRL CE » High to RY »/BY » Going Low 100 100 ns
tEHGL Write Recovery before Read 0 0 µs
tQVVL VPP Hold from Valid SRD, RY »/BY » High 0 0 ns 2, 4
tQVPH RP » VHH Hold from Valid SRD, RY »/BY » High 0 0 ns 2, 4
NOTE:
1. See 5 V VCC Alternative CE » Controlled Writes for Notes 1 through 5.
30
ALTERNATIVE CE » - Controlled Writes1 (Continued)

VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
LH28F008SC-856 LH28F008SC-907 LH28F008SC-1207

tAVAV Write Cycle Time 85 90 120 ns
RP » High Recovery to
tPHEL 1 1 1 µs 2
CE » Going Low
WE Setup to CE »
tWLEL 0 0 0 ns
Going Low
tELEH CE » Pulse Width 50 50 50 ns
RP » VHH Setup to CE »
tPHHEH 100 100 100 ns 2
Going High
VPP Setup to CE »
tVPEH 100 100 100 ns 2
Going High
Address Setup to CE »
tAVEH 40 40 40 ns 3
Going High
tDVEH Data Setup to CE » Going High 40 40 40 ns 3
tEHDX Data Hold from CE » High 5 5 5 ns
tEHAX Address Hold from CE » High 5 5 5 ns
tEHWH WE Hold from CE » High 0 0 0 ns
tEHEL CE » Pulse Width High 25 25 25 ns
tEHRL CE » High to RY »/BY » Going Low 90 90 90 ns
tEHGL Write Recovery before Read 0 0 0 µs

VPP Hold from Valid SRD,
tQVVL 0 0 0 ns 2, 4
RY »/BY » High
RP » VHH Hold from Valid SRD,
tQVPH 0 0 0 ns 2, 4
RY »/BY » High
NOTES:
1. In systems where CE » defines the write pulse width (within a longer WE » timing waveform), all setup, hold, and inactive WE »
times should be measured relative to the CE » waveform.
3. Refer to Command Definitions Table for valid A IN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP » should be held at VHH) until determination of block erase, byte write,
or lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
31
1 2 3 4 5 6
VIH
ADDRESSES (A) AIN AIN
VIL
tAVAV tAVEH
tEHAX
VIH
WE (E)
VIL
tWLEL
tEHWH tEHGL
VIH
OE (G)
VIL
tEHEL tEHQV1, 2, 3, 4
VIH
CE (E)
VIL
tELEH
tDVEH
tEHDX
VIH HIGH-Z VALID

DATA (D/Q) DIN DIN DIN
VIL SRD
tPHEL tEHRL
VIH
RY/BY (R)
VIL
tPHHEH tQVPH
VHH
RP (P) VIH
VIL
tVPEH tQVVL
VPPH3, 2, 1
VPP (V) VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write set-up.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
008SC-17
Figure 17. Alternate AC Waveform for CE » Controlled Write Operations
32
RESET OPERATIONS
VIH
RY/BY (R)
VIL
VIH
RP (P)
VIL
tPLPH
A. Reset During Read Array Mode
VIH
RY/BY (R)
VIL
tPLRH
VIH
RP (P)
VIL
tPLPH
B. Reset During Block Erase, Byte Write, or Lock-Bit Configuration
28F008SC-18
Figure 18. AC Waveform for Reset Operation
Reset AC Specifications1
VCC = 3.3 V VCC = 5 V

MIN. MAX. MIN. MAX.
RP » Pulse Low Time (If RP » is tied to VCC, this

tPLPH 100 100 ns
specification is not applicable)
RP » Low to Reset during Block Erase, Byte Write, or

tPLRH 20 12 µs 2,3
Lock-Bit Configuration
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP » is asserted while a block erase, byte write, or lock-bit configuration operation is not executing,
the reset will complete within 100 ns.
3. A reset time tPHQV, is required from the latter of RY »/BY » or RP » going high until outputs are valid.
33
BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE3, 4

VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
VPP = 3.3 V VPP = 53 V VPP = 12 V

SYM. PARAMETER UNIT NOTE
TYP.1 MIN. MAX. TYP.1 MIN. MAX. TYP.1 MIN. MAX.
tWHQV1
Byte Write Time 17 15 TBD 9.3 8.2 TBD 7.6 6.7 TBD µs 2
tEHQV1
Block Write Time 1.1 1 TBD 0.6 0.5 TBD 0.5 0.4 TBD sec 2
tWHQV2
Block Erase Time 1.8 1.5 TBD 1.2 1 TBD 1.1 0.8 TBD sec 2
tEHQV2
tWHQV3
Set Lock-Bit Time 21 18 TBD 13.3 11.2 TBD 11.6 9.7 TBD µs 2
tEHQV3
tWHQV4 Clear Block Lock-Bits

1.8 1.5 TBD 1.2 1 TBD 1.1 0.8 TBD sec 2
tEHQV4 Time
tWHRH1 Byte Write Suspend

6 7 5 7 5 6 µs
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend

16.2 20 9.6 12 9.6 12 µs
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
VPP = 53 V VPP = 12 V
SYM. PARAMETER UNIT NOTE
TYP.1 MIN. MAX. TYP.1 MIN. MAX.
tWHQV1
Byte Write Time 8 6.5 TBD 6 4.8 TBD µs 2
tEHQV1
Block Write Time 0.5 0.4 TBD 0.4 0.3 TBD sec 2
tWHQV2
Block Erase Time 1.1 0.9 TBD 1.0 0.3 TBD sec 2
tEHQV2
tWHQV3
Set Lock-Bit Time 12 9.5 TBD 10 7.8 TBD µs 2
tEHQV3
tWHQV4
Clear Block Lock-Bits Time 1.1 0.9 TBD 1.0 0.3 TBD sec 2
tEHQV4
tWHRH1 Byte Write Suspend

5 6 4 5 µs
tWHRH2 Erase Suspend Latency

9.6 12 9.6 12 µs
tEHRH2 Time to Read
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based
on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled but not 100% tested.
34
44SOP (SOP044-P-0600)
1.27 [0.050]
0.50 [0.020] TYP.
0.30 [0.012]
44 23
13.40 [0.528] 16.40 [0.646]

14.40 [0.567]
13.00 [0.512] 15.60 [0.614]
1 22 SEE
DETAIL
0.20 [0.008] 2.9 [0.114]

28.40 [1.118]
0.10 [0.004] 2.5 [0.098] DETAIL
28.00 [1.102]
1.275 [0.050]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
2.9 [0.114] 3.25 [0.128]
2.5 [0.098] 2.45 [0.096]
0.25 [0.010] 0 - 10°

0.05 [0.002]
0.80 [0.031]
1.275 [0.050]
MAXIMUM LIMIT
DIMENSIONS IN MM [INCHES]
MINIMUM LIMIT 44SOP
35
42CSP (CSP042-P-0808)
INDEX
8.20 [0.323]
7.80 [0.307]
8.20 [0.323]
7.80 [0.307]
0.10 [0.004]
(See Detail) 0.40 [0.016]

TYP.
0.10 [0.004] DETAIL
0.67 [0.026]
1.20 [0.047]
TYP.
MAX.
1.0 [1.039] 1.0 [1.039]
TYP. TYP.
0.25 [0.010]
MIN.
1.0 [1.039]
TYP.
1.0 [1.039]
TYP.
0.48 [0.019] 0.30 [0.012]

0.42 [0.017] 0.15 [0.006]
MAXIMUM LIMIT
MINIMUM LIMIT 42CSP
36
40TSOP (TSOP040-P-1020)
1 40
0.50 [0.020]
10.20 [0.402]
TYP.
9.80 [0.386]
0.25 [0.010]
0.15 [0.006]
20 21
1.10 [0.043]
0.90 [0.035]
SEE DETAIL
1.19
0.49 [0.019]
[0.047]
0.39 [0.015] DETAIL
MAX.
0.125 [0.005]
18.60 [0.732]
18.20 [0.717]
19.30 [0.760]
18.70 [0.736]
0.49 [0.019] 0 - 10°
20.30 [0.799] 0.39 [0.015]
19.70 [0.776] 0.18 [0.007]
0.22 [0.009] 0.08 [0.003]
0.02 [0.001]
MAXIMUM LIMIT
MINIMUM LIMIT 40TSOP
ORDERING INFORMATION
LH28F008SC X -85
Device Type Package Speed
85 Access Time (ns)
T 40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020)

N 44-pin, 600-mil SOP (SOP044-P-0600)
B 42-pin, .67 mm x 8 mm2 CSP (CSP042-P-0808)
8M (1M x 8) Flash Memory
Example: LH28F008SCT-85 (1M x 8) Flash Memory, 85 ns, 40-pin TSOP)

28F008SC-19
37
LIFE SUPPORT POLICY

SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
NORTH AMERICA EUROPE ASIA
SHARP Electronics Corporation SHARP Electronics (Europe) GmbH SHARP Corporation

Microelectronics Group Microelectronics Division Integrated Circuits Group
5700 NW Pacific Rim Blvd., M/S 20 Sonninstraße 3 2613-1 Ichinomoto-Cho
Camas, WA 98607, U.S.A. 20097 Hamburg, Germany Tenri-City, Nara, 632, Japan
Phone: (360) 834-2500 Phone: (49) 40 2376-2286 Phone: (07436) 5-1321
Telex: 49608472 (SHARPCAM) Telex: 2161867 (HEEG D) Telex: LABOMETA-B J63428
Facsimile: (360) 834-8903 Facsimile: (49) 40 2376-2232 Facsimile: (07436) 5-1532
http://www.sharpmeg.com
©1997 by SHARP Corporation Reference Code SMT96114

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LH28F008SC 8M (1M × 8) Flash Memory

FEATURES 42-PIN CSP TOP VIEW

• High-Performance B A4 A7 A10 VCC A13 NC A18

• Enhanced Data Protection Features F A1 DQ0 DQ2 GND DQ5 RY/BY WE

Power Transitions Figure 1. CSP 42-Pin Configuration

ICC in Static Mode A16 4 37 OE

– 3.3 V or 5 V VCC VCC 10 31 VCC

– 3.3 V, 5 V, or 12 V VPP VPP 11 30 GND

Figure 2. TSOP 40-Pin Configuration

44-PIN SOP TOP VIEW New Features

IDENTIFIER I/O LOGIC RP

16 64KB BLOCKS VPP

Figure 4. LH28F008SC Block Diagram

SYMBOL TYPE NAME AND FUNCTION

NC NO CONNECT: Lead is not internal connected; it may be driven or floated.

Data Protection Standby

28F008SC-5 Read Array Command

MODE RP » CE » OE » WE ADDRESS VPP DQ0 - DQ7 RY »/BY » NOTE

Read VIH or VHH VIL VIL VIH X X DOUT X 1, 2, 3

Output Disable VIH or VHH VIL VIH VIH X X High-Z X 3

Standby VIH or VHH VIH X X X X High-Z X 3

Deep Power Down VIL X X X X X High-Z VOH 4

Write VIH or VHH VIL VIH VIL X X DIN X 3, 6, 7

BUS FIRST BUS CYCLE SECOND BUS CYCLE

Read Array/Reset 1 Write X FFH

Read Identifier Codes Command Clear Status Register Command

Set Block and Master Clear Block Lock-Bits Command

Write Protection Alternatives

0 VIH or VHH Block Erase and Byte Write Enabled.

0 X VIH or VHH Set Block Lock-Bit Enabled.

Set Master VIH Set Master Lock-Bit Disabled.

0 X VIH or VHH Clear Block Lock-Bits Enable.

Status Register Definition

WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

WRITE 20H Write Erase Data = 20H

FULL STATUS CHECK PROCEDURE

STATUS REGISTER BUS

If error is detected, clear the Status Register before attempting

Figure 6. Automated Block Erase Flowchart

WRITE 40H Write Setup Data = 40H

Write Byte Data = Data to be written

Read Status Register Data

FULL STATUS CHECK PROCEDURE

READ STATUS BUS

Figure 7. Automated Byte Write Flowchart

START BUS COMMAND COMMENTS

Write Erase Data = B0H

Read READ or Byte Write

WRITE D0H WRITE FFH

BLOCK READ ARRAY DATA

Figure 7. Block Erase Suspend/Resume Flowchart

START BUS COMMAND COMMENTS

Write Byte Write Data = B0H

Read Status Register Data

Standby Check SR.7

Write Read Data = FFH

READ ARRAY DATA

WRITE D0H WRITE FFH