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SN54AHCT244, SN74AHCT244
SCLS228M – OCTOBER 1995 – REVISED JULY 2014
SNx4AHCT244 Octal Buffers/Drivers With 3-State Outputs

1 Features 3 Description
•
1 Inputs Are TTL-Voltage Compatible These octal buffers/drivers are designed specifically
to improve both the performance and density of
• Latch-Up Performance Exceeds 250 mA 3-state memory-address drivers, clock drivers, and
Per JESD 17 bus-oriented receivers and transmitters.
• On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise Device Information(1)
Noted. On All Other Products, Production PART NUMBER PACKAGE BODY SIZE (NOM)
Processing Does Not Necessarily Include Testing PDIP (20) 25.40 mm x 6.35 mm
of All Parameters. SOP (20) 12.60 mm x 5.30 mm
SNx4AHCT244 SSOP (20) 7.50 mm x 5.30 mm
2 Applications TVSOP (20) 5.00 mm x 4.40 mm
• Network Switches TSSOP (20) 6.50 mm x 4.40 mm
• Power Infrastructures (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• PCs and Notebooks
• Wearable Health and Fitness Devices
• Tests and Measurements
4 Simplified Schematic
1 19
1OE 2OE
2 18 11 9
1A1 1Y1 2A1 2Y1
4 16 13 7
1A2 1Y2 2A2 2Y2
6 14 15 5
1A3 1Y3 2A3 2Y3
8 12 17 3
1A4 1Y4 2A4 2Y4
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SCLS228M – OCTOBER 1995 – REVISED JULY 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................... 8
2 Applications ........................................................... 1 9.2 Functional Block Diagram ......................................... 8
3 Description ............................................................. 1 9.3 Feature Description................................................... 8
9.4 Device Functional Modes.......................................... 8
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2 10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
6 Pin Configuration and Functions ......................... 3
10.2 Typical Application ................................................. 9
7 Specifications......................................................... 4
11 Power Supply Recommendations ..................... 10
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4 12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
7.3 Recommended Operating Conditions....................... 4
12.2 Layout Example .................................................... 10
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics........................................... 5 13 Device and Documentation Support ................. 11
7.6 Switching Characteristics .......................................... 5 13.1 Related Links ........................................................ 11
7.7 Noise Characteristics ................................................ 5 13.2 Trademarks ........................................................... 11
7.8 Operating Characteristics.......................................... 6 13.3 Electrostatic Discharge Caution ............................ 11
7.9 Typical Characteristics .............................................. 6 13.4 Glossary ................................................................ 11
8 Parameter Measurement Information .................. 7 14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
9 Detailed Description .............................................. 8
5 Revision History
Changes from Revision L (July 2003) to Revision M Page
• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1
• Added Military Disclaimer to Features List ............................................................................................................................ 1
• Added Handling Ratings table. .............................................................................................................................................. 4
• Changed MAX operating temperature from 85°C to 125°C in Recommended Operating Conditions table. ......................... 4
• Added Thermal Information table. ......................................................................................................................................... 4
• Added Typical Characteristics section. .................................................................................................................................. 6
• Added Detailed Description section. ...................................................................................................................................... 8
• Added Application and Implementation section. ................................................................................................................... 9
• Added Layout section. ......................................................................................................................................................... 10
2 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT244 SN74AHCT244

www.ti.com SCLS228M – OCTOBER 1995 – REVISED JULY 2014
6 Pin Configuration and Functions

SN54AHCT244 . . . J OR W PACKAGE
SN74AHCT244 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1OE 1 20 VCC
1A1 2 19 2OE
2Y4 3 18 1Y1
1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
2Y2 7 14 1Y3
1A4 8 13 2A2
2Y1 9 12 1Y4
GND 10 11 2A1
SN54AHCT244 . . . FK PACKAGE
(TOP VIEW)
1OE
2OE
VCC
2Y4
1A1
3 2 1 20 19
1A2 4 18 1Y1
2Y3 5 17 2A4
1A3 6 16 1Y2
2Y2 7 15 2A3
1A4 8 14 1Y3
9 10 11 12 13
2Y1
2A1
1Y4
2A2
GND
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1OE I Output Enable 1
2 1A1 I Input 1A1
3 2Y4 O Input 2Y4
4 1A2 I Input 1A2
5 2Y3 O Input 2Y3
6 1A3 I Input 1A3
7 2Y2 O Input 2Y2
8 1A4 I Input 1A4
9 2Y1 O Input 2Y1
10 GND – Ground Pin
11 2A1 I Output 2A1
12 1Y4 O Output 1Y4
13 2A2 I Output 2A2
14 1Y3 O Output 1Y3
15 2A3 I Output 2A3
16 1Y2 O Output 1Y2
17 2A4 I Output 2A4
18 1Y1 O Output 1Y1
19 2OE I Output Enable 2
20 VCC – Power Pin
Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
VO Output voltage range (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±75 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 2000
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 2000
JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)

SN54AHCT244 SN74AHCT244
UNIT
MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current –8 –8 mA
IOL Low-level output current 8 8 mA
TA Operating free-air temperature –55 125 –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information

SN74AHCT244
THERMAL METRIC (1) DB DGV DW N NS PW UNIT
20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 99.9 119.2 83.0 54.9 80.4 105.4
RθJC(top) Junction-to-case (top) thermal resistance 61.7 34.5 48.9 41.7 46.9 39.5
RθJB Junction-to-board thermal resistance 55.2 60.7 50.5 35.8 47.9 56.4 °C/W
ψJT Junction-to-top characterization parameter 22.6 1.2 21.1 27.9 19.9 3.1
ψJB Junction-to-board characterization parameter 54.8 60.0 50.1 35.7 47.5 55.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54AHCT244 SN74AHCT244
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –50 µA 4.4 4.5 4.4 4.4
VOH 4.5 V V
IOH = –8 mA 3.94 3.8 3.8
IOL = 50 µA 0.1 0.1 0.1
VOL 4.5 V V
IOL = 8 mA 0.36 0.44 0.44
VO = VCC or GND ±0.2
IOZ 5.5 V ±2.5 ±2.5 µA
5
0 V to
II VI = 5.5 V or GND ±0.1 ±1 (1) ±1 µA
5.5 V
VI = VCC or IO = 0
ICC 5.5 V 4 40 40 µA
GND,
One input at 3.4 V,
∆ICC (2) Other inputs at VCC or 5.5 V 1.35 1.5 1.5 mA
GND
Ci VI = VCC or GND 5V 2.5 10 10 pF
Co VO = VCC or GND 5V 3 pF
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
(2) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
7.6 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
FROM TO LOAD TA = 25°C SN54AHCT244 SN74AHCT244
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 5.4 (1) 7.4 (1) 1 (1) 8.5 (1) 1 8.5
A Y CL = 15 pF (1) (1) (1) (1)
ns
tPHL 5.4 7.4 1 8.5 1 8.5
tPZH 7.7 (1) 10.4 (1) 1 (1) 12 (1) 1 12
OE Y CL = 15 pF ns
tPZL 7.7 (1) 10.4 (1) 1 (1) 12 (1) 1 12
tPHZ 5 (1) 9.4 (1) 1 (1) 10 (1) 1 10
OE Y CL = 15 pF (1) (1) (1)
ns
tPLZ 5 9.4 1 10 (1) 1 10
tPLH 5.9 8.4 1 9.5 1 9.5
A Y CL = 50 pF ns
tPHL 5.9 8.4 1 9.5 1 9.5
tPZH 8.2 11.4 1 13 1 13
OE Y CL = 50 pF ns
tPZL 8.2 11.4 1 13 1 13
tPHZ 8.8 11.4 1 13 1 13
OE Y CL = 50 pF ns
tPLZ 8.8 11.4 1 13 1 13
tsk(o) CL = 50 pF 1 (2) 1 ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

(2) On products compliant to MIL-PRF-38535, this parameter does not apply.
7.7 Noise Characteristics (1)

VCC = 5 V, CL = 50 pF, TA = 25°C
SN74AHCT244
PARAMETER UNIT
MIN TYP MAX
VOH(V) Quiet output, minimum dynamic VOH 4.1 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
(1) Characteristics are for surface-mount packages only.

7.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 8.2 pF
7.9 Typical Characteristics
7
TPD in ns
6
5
TPD (ns)
0
-100 -50 0 50 100 150
Temperature (°C) D001
Figure 1. TPD vs Temperature, 15 pF Load

8 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC
LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input 1.5 V
tw 0V
th
3V tsu
3V
Input 1.5 V 1.5 V
Data Input 1.5 V 1.5 V
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
3V 3V
Output
Input 1.5 V 1.5 V 1.5 V 1.5 V
Control
0V 0V
tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2 VOH – 0.3 V
50% VCC 50% VCC S1 at GND 50% VCC
Output
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms

9 Detailed Description
9.1 Overview
The SNx4AHCT244 devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-
sinking capability of the driver.
9.2 Functional Block Diagram
1
DIR
19
OE
2
A1
18
B1
To Seven Other Channels
9.3 Feature Description

• VCC is optimized at 5 V
• Allows up voltage translation from 3.3 V to 5 V
– Inputs Accept VIH levels of 2 V
• Slow edge rates minimize output ringing
• Inputs are TTL-Voltage compatible
9.4 Device Functional Modes
Table 1. Function Table

(Each 4-Bit Buffer/Driver)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

10 Application and Implementation

10.1 Application Information
The SN74AHCT244 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. Figure 3 shows this type of
translation.
10.2 Typical Application

Regulated 3.3 V 5-V Regulated
OE VCC
5-V Sub-system
A1 Y1
µC µC
System Logic System Logic
LEDs
A4 Y4
GND
Figure 3. Specific Application Schematic
10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure

1. Recommended Input conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 25 mA on the output and 50 mA total for the part
– Outputs should not be pulled above VCC

Typical Application (continued)

10.2.3 Application Curves
Output
Input
Figure 4. Application Curve
11 Power Supply Recommendations

The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines

When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 5 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example

Vcc
Input
Unused Input Output Output

Unused Input
Input
Figure 5. Layout Diagram

13 Device and Documentation Support
13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54AHCT244 Click here Click here Click here Click here Click here
SN74AHCT244 Click here Click here Click here Click here Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-9678301Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9678301Q2A
SNJ54AHCT
244FK
5962-9678301QRA ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9678301QR Samples
& Green A
SNJ54AHCT244J
5962-9678301QSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9678301QS Samples
& Green A
SNJ54AHCT244W
SN74AHCT244DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB244 Samples
SN74AHCT244DGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB244 Samples
SN74AHCT244DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT244 Samples
SN74AHCT244DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT244 Samples
SN74AHCT244N ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT244N Samples
Non-Green
SN74AHCT244NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT244 Samples
SN74AHCT244PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB244 Samples
SN74AHCT244PWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB244 Samples
SN74AHCT244PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HB244 Samples
SN74AHCT244PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB244 Samples
SNJ54AHCT244FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9678301Q2A
SNJ54AHCT
244FK
SNJ54AHCT244J ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9678301QR Samples
& Green A
SNJ54AHCT244J
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SNJ54AHCT244W ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9678301QS Samples
& Green A
SNJ54AHCT244W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHCT244, SN74AHCT244 :
Addendum-Page 2
• Catalog : SN74AHCT244
• Automotive : SN74AHCT244-Q1, SN74AHCT244-Q1
• Enhanced Product : SN74AHCT244-EP, SN74AHCT244-EP
• Military : SN54AHCT244
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHCT244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74AHCT244DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT244DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74AHCT244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74AHCT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74AHCT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74AHCT244PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT244DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74AHCT244DGVR TVSOP DGV 20 2000 356.0 356.0 35.0
SN74AHCT244DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74AHCT244NSR SO NS 20 2000 367.0 367.0 45.0
SN74AHCT244PWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74AHCT244PWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74AHCT244PWRG4 TSSOP PW 20 2000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9678301Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9678301QSA W CFP 20 1 506.98 26.16 6220 NA
SN74AHCT244DW DW SOIC 20 25 507 12.83 5080 6.6
SN74AHCT244N N PDIP 20 20 506 13.97 11230 4.32
SN74AHCT244PW PW TSSOP 20 70 530 10.2 3600 3.5
SN74AHCT244PWG4 PW TSSOP 20 70 530 10.2 3600 3.5
SNJ54AHCT244FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54AHCT244W W CFP 20 1 506.98 26.16 6220 NA
PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
6.6 5.85
6.4
NOTE 3
10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE 0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1
2X
7.5
5.85
6.9
NOTE 3
10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4
2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE
0.95 0.05 MIN

0 -8 0.55
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
5. Reference JEDEC registration MO-150.
www.ti.com
DB0020A SSOP - 2 mm max height
20X (1.85) SYMM
1 (R0.05) TYP
20X (0.45) 20
SYMM
18X (0.65)
10 11
(7)

EXPOSED METAL SHOWN
SCALE: 10X

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)

www.ti.com
DB0020A SSOP - 2 mm max height
20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(7)

SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN
0,23
0,40 0,07 M
0,13
24 13
0,16 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
0°–8°
0,75
1 12
0,50
A
Seating Plane
0,15
1,20 MAX 0,08
0,05
PINS **
14 16 20 24 38 48 56
DIM
A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40
A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC
10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1
13.0 2X
12.6 11.43
NOTE 3
10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4
0.33
TYP
0.10
0.25
SEE DETAIL A GAGE PLANE
1.27 0.3
0 -8 0.40 0.1
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
5. Reference JEDEC registration MS-013.
www.ti.com
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2) SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10 11
(9.3)

SCALE:6X

METAL OPENING
OPENING SOLDER MASK
0.07 MAX 0.07 MIN

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

www.ti.com
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10 11
(9.3)

SCALE:6X
4220724/A 05/2016
NOTES: (continued)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

SNx4AHCT244 Octal Buffers/Drivers With 3-State Outputs

• Network Switches TSSOP (20) 6.50 mm x 4.40 mm

• Updated document to new TI data sheet format. ................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated

Product Folder Links: SN54AHCT244 SN74AHCT244

6 Pin Configuration and Functions

Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

7.2 Handling Ratings

7.3 Recommended Operating Conditions (1)

7.4 Thermal Information

4 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated

Product Folder Links: SN54AHCT244 SN74AHCT244

7.5 Electrical Characteristics

7.6 Switching Characteristics

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.7 Noise Characteristics (1)

(1) Characteristics are for surface-mount packages only.

Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 5

7.8 Operating Characteristics

7.9 Typical Characteristics

Figure 1. TPD vs Temperature, 15 pF Load

6 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated

Product Folder Links: SN54AHCT244 SN74AHCT244

8 Parameter Measurement Information

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

tPLH tPHL tPZL tPLZ

NOTES: A. CL includes probe and jig capacitance.

Figure 2. Load Circuit and Voltage Waveforms

Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 7

9.2 Functional Block Diagram

To Seven Other Channels

9.3 Feature Description

9.4 Device Functional Modes

Table 1. Function Table

8 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated

Product Folder Links: SN54AHCT244 SN74AHCT244

10 Application and Implementation

10.2 Typical Application

Figure 3. Specific Application Schematic

10.2.1 Design Requirements

10.2.2 Detailed Design Procedure

Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Application (continued)

Figure 4. Application Curve

11 Power Supply Recommendations

12.1 Layout Guidelines

12.2 Layout Example

Unused Input Output Output

Figure 5. Layout Diagram

10 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated

Product Folder Links: SN54AHCT244 SN74AHCT244

13 Device and Documentation Support

13.1 Related Links

Table 2. Related Links

14 Mechanical, Packaging, and Orderable Information

Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 11

OTHER QUALIFIED VERSIONS OF SN54AHCT244, SN74AHCT244 :