SN74HC32, SN54HC32

SCLS200F – DECEMBER 1982 – REVISED APRIL 2021

SNx4HC32 Quadruple 2-Input OR Gates

1 Features 3 Description
• Buffered inputs This device contains four independent 2-input OR
• Wide operating voltage range: 2 V to 6 V gates. Each gate performs the Boolean function
• Wide operating temperature range: Y = A + B in positive logic.
–40°C to +85°C
Device Information(1)
• Supports fanout up to 10 LSTTL loads
PART NUMBER PACKAGE BODY SIZE (NOM)
• Significant power reduction compared to LSTTL
logic ICs SN74HC32D SOIC (14) 8.70 mm × 3.90 mm
SN74HC32DB SSOP (14) 6.50 mm × 5.30 mm
2 Applications SN74HC32N PDIP (14) 19.30 mm × 6.40 mm
• User fewer inputs to monitor error signals SN74HC32NS SO (14) 10.20 mm × 5.30 mm
• Combine active-low enable signals SN74HC32PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC32J CDIP (14) 21.30 mm × 7.60 mm
SN54HC32W CFP (14) 9.20 mm × 6.29 mm
SN54HC32FK LCCC (20) 8.90 mm × 8.90 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

1A 1 14 VCC
1B 2 13 4B
3 12
1Y 4A
2A 4 11 4Y
5 10
2B 3B
2Y 6 9 3A
GND 7 8 3Y

Functional pinout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.11 Typical Characteristics.............................................. 7
2 Applications..................................................................... 1 7 Parameter Measurement Information............................ 8
3 Description.......................................................................1 8 Detailed Description........................................................9
4 Revision History.............................................................. 2 8.1 Overview..................................................................... 9
5 Pin Configuration and Functions...................................3 8.2 Functional Block Diagram........................................... 9
Pin Functions.................................................................... 3 8.3 Feature Description.....................................................9
6 Specifications.................................................................. 4 8.4 Device Functional Modes..........................................10
6.1 Absolute Maximum Ratings........................................ 4 9 Layout.............................................................................13
6.2 ESD Ratings............................................................... 4 9.1 Layout Guidelines..................................................... 13
6.3 Recommended Operating Conditions.........................4 9.2 Layout Example........................................................ 13
6.4 Thermal Information - 74.............................................5 10 Device and Documentation Support..........................14
6.5 Thermal Information - 54.............................................5 10.1 Documentation Support.......................................... 14
6.6 Electrical Characteristics - 74..................................... 5 10.2 Related Links.......................................................... 14
6.7 Electrical Characteristics - 54..................................... 6 10.3 Support Resources................................................. 14
6.8 Switching Characteristics - 74.....................................6 10.4 Trademarks............................................................. 14
6.9 Switching Characteristics - 54.....................................7 10.5 Electrostatic Discharge Caution..............................14
6.10 Operating Characteristics......................................... 7 10.6 Glossary..................................................................14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2016) to Revision F (April 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• Updated thermal values for the commercial device............................................................................................5

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5 Pin Configuration and Functions

1B 1A NC VCC 4B
1A 1 14 VCC
1B 2 13 4B 3 2 1 20 19
1Y 4 18 4A
1Y 3 12 4A
2A NC 5 17 NC
4 11 4Y
2B 2A 6 16 4Y
5 10 3B
2Y 6 9 3A NC 7 15 NC
GND 7 8 3Y 2B 8 14 3B
9 10 11 12 13
Figure 5-1. D, DB, N, NS, PW, J, or W Package 2Y GND NC 3Y 3A
14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP Figure 5-2. FK Package
Top View 20-Pin LCCC
Top View

Pin Functions
PIN
D, DB, N, I/O DESCRIPTION
NAME NS, PW, J, FK
or W
1A 1 2 Input Channel 1, Input A
1B 2 3 Input Channel 1, Input B
1Y 3 4 Output Channel 1, Output Y
2A 4 6 Input Channel 2, Input A
2B 5 8 Input Channel 2, Input B
2Y 6 9 Output Channel 2, Output Y
GND 7 10 — Ground
3Y 8 12 Output Channel 3, Output Y
3A 9 13 Input Channel 3, Input A
3B 10 14 Input Channel 3, Input B
4Y 11 16 Output Channel 4, Output Y
4A 12 18 Input Channel 4, Input A
4B 13 19 Input Channel 4, Input B
VCC 14 20 — Positive Supply
1, 5, 7, 11, 15,
NC — Not internally connected
17

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±750
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
Δt/Δv Input transition rise and fall rate VCC = 4.5 V 500 ns
VCC = 6 V 400
SN54HC32 –55 125
TA Operating free-air temperature °C
SN74HC32 –40 85

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6.4 Thermal Information - 74

SN74HC32
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SOP) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient thermal
RθJA 133.6 111.3 67.0 122.6 151.7 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 89.0 61.2 55.0 81.8 79.4 °C/W
resistance
Junction-to-board thermal
RθJB 89.5 61.6 46.7 83.8 94.7 °C/W
resistance
Junction-to-top characterization
ΨJT 45.5 20.8 35.1 45.4 25.2 °C/W
parameter
Junction-to-board
ΨJB 89.1 60.9 46.5 83.4 94.1 °C/W
characterization parameter
Junction-to-case (bottom)
RθJC(bot) N/A N/A N/A N/A N/A °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Thermal Information - 54

SN54HC32
THERMAL METRIC(1) J (CDIP) W (CFP) FK (LCCC) UNIT
14 PINS 14 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance — — — °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.9 88.3 61.0 °C/W
RθJB Junction-to-board thermal resistance 80.1 156.0 59.6 °C/W
Junction-to-top characterization
ΨJT — — — °C/W
parameter
Junction-to-board characterization
ΨJB — — — °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) 25.1 15.2 11.7 °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Electrical Characteristics - 74

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9
IOH = -20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH
VOH 6V 5.9 5.999 5.9 V
output voltage or VIL
IOH = -4 mA 4.5 V 3.98 4.3 3.84
IOH = -5.2 mA 6V 5.48 5.8 5.34

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 0.002 0.1 0.1
IOL = 20 µA
4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL IOL = 20 µA 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.33
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 µA
current
VI = VCC
ICC Supply current VI = VCC or 0 6V 2 20 µA
or 0
Input
Ci 2 V to 6 V 3 10 10 pF
capacitance

6.7 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9 1.9
IOH = –20
4.5 V 4.4 4.499 4.4 4.4
µA
6V 5.9 5.999 5.9 5.9
High-level VI = VIH or
VOH V
output voltage VIL IOH = –4
4.5 V 3.98 4.3 3.84 3.7
mA
IOH = –5.2
6V 5.48 5.8 5.34 5.2
mA
2V 0.002 0.1 0.1 0.1
IOL = 20
4.5 V 0.001 0.1 0.1 0.1
µA
Low-level output VI = VIH or 6V 0.001 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33 0.4
IOL = 5.2
6V 0.15 0.26 0.33 0.4
mA
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 ±1 µA
current
VI = VCC or
ICC Supply current IO = 0 6V 2 20 40 µA
0
Input 2 V to
Ci 3 10 10 10 pF
capacitance 6V

6.8 Switching Characteristics - 74

CL = 50 pF, over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 50 100 125
tpd Propagation delay A or B Y 4.5 V 10 20 25 ns
6V 8 17 21

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CL = 50 pF, over operating free-air temperature range (unless otherwise noted)

Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 38 75 95
tt Transition-time Y 4.5 V 8 15 19 ns
6V 6 13 16

6.9 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 50 100 125 150
tpd Propagation delay A or B Y 4.5 V 10 20 25 30 ns
6V 8 17 21 25
2V 38 75 95 110
tt Transition-time Y 4.5 V 8 15 19 22 ns
6V 6 13 16 19

6.10 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 20 pF
per gate

6.11 Typical Characteristics

TA = 25°C

7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)

Figure 6-1. Typical output voltage in the high state Figure 6-2. Typical output voltage in the low state
(VOH) (VOL)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC
90% 90%
Point
Input
10% 10%
0V
From Output tr(1) tf(1)
Under Test
VOH
CL(1) 90% 90%
Output
10% 10%
VOL
A. CL= 50 pF and includes probe and jig capacitance. tr(1) tf(1)

Figure 7-1. Load Circuit A. tt is the greater of tr and tf.

Figure 7-2. Voltage Waveforms Transition Times
VCC
Input 50% 50%
0V
(1) (1)
tPLH tPHL
VOH
Output 50% 50%
VOL
tPHL(1) tPLH(1)
VOH
Output 50% 50%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in
positive logic.
8.2 Functional Block Diagram

xA

xY

xB

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74HC32 can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUT
A B Y
L L L
H X H
X H H

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Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

In this application, three 2-input OR gates are combined to produce a 4-input OR gate function as shown in
Figure 9-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
This device is used to directly control the Enable pin of a fan driver. The fan driver requires only one input signal
to be HIGH before being enabled, and should be disabled in the event that all signals go LOW. The 4-input OR
gate function combines the four individual overheat signals into a single active-high enable signal.
9.2 Typical Application

Device 1 Device 2
Overhe at Overhe at

Fan
Driver

EN

Device 3 Device 4
Overhe at Overhe at

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC32 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

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CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HC32, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC32 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 9.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC32
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves

Device 1

Device 2

Device 3

Device 4

EN

Figure 9-2. Typical application timing diagram

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Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 9-1.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
9.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to the
0.1 F device

1A 1 14 VCC Unused
1B 2 13 4B inputs tied to
VCC
1Y 3 12 4A
Unused
2A 4 11 4Y output left
floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 9-1. Example layout for the SN74HC32

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
10.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8404501VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8404501VC Samples
& Green A
SNV54HC32J
5962-8404501VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8404501VD Samples
& Green A
SNV54HC32W
84045012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84045012A Samples
& Green SNJ54HC
32FK
8404501CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8404501CA Samples
& Green SNJ54HC32J
8404501DA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8404501DA Samples
& Green SNJ54HC32W
JM38510/65201B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201B2A
JM38510/65201BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201BCA
JM38510/65201BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201BDA
M38510/65201B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201B2A
M38510/65201BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201BCA
M38510/65201BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65201BDA
SN54HC32J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC32J Samples
& Green
SN74HC32D OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC32
SN74HC32DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32DT OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC32

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC32N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N Samples

SN74HC32NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N Samples

SN74HC32NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32PW OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC32

SN74HC32PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC32 Samples

SN74HC32PWT OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC32

SNJ54HC32FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84045012A Samples
& Green SNJ54HC
32FK
SNJ54HC32J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8404501CA Samples
& Green SNJ54HC32J
SNJ54HC32W ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8404501DA Samples
& Green SNJ54HC32W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC32, SN54HC32-SP, SN74HC32 :

• Catalog : SN74HC32, SN54HC32

• Military : SN54HC32
• Space : SN54HC32-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC32DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC32PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC32PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC32DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74HC32DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC32DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HC32NSR SO NS 14 2000 356.0 356.0 35.0
SN74HC32PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC32PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8404501VDA W CFP 14 25 506.98 26.16 6220 NA
84045012A FK LCCC 20 55 506.98 12.06 2030 NA
8404501DA W CFP 14 25 506.98 26.16 6220 NA
JM38510/65201B2A FK LCCC 20 55 506.98 12.06 2030 NA
JM38510/65201BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/65201B2A FK LCCC 20 55 506.98 12.06 2030 NA
M38510/65201BDA W CFP 14 25 506.98 26.16 6220 NA
SN74HC32N N PDIP 14 25 506 13.97 11230 4.32
SN74HC32N N PDIP 14 25 506 13.97 11230 4.32
SN74HC32NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC32NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC32FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54HC32W W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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