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    Chapter 3 - Ex-FF-D

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    Minh Phú
    This document discusses flip-flops and related devices. It describes the operation of an FF-D latch created from NAND gates where the output Q tracks the input D when the clock is high. It also shows examples of a D flip-flop with both positive and negative edge clock pulses where the output Q changes state according to the input D at the rising or falling edge of the clock. Finally, it demonstrates using a D flip-flop for switch debouncing where the output only changes at the negative clock edge.

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    Chapter 3 - Ex-FF-D

    Uploaded by

    Minh Phú
    31 views7 pages
    This document discusses flip-flops and related devices. It describes the operation of an FF-D latch created from NAND gates where the output Q tracks the input D when the clock is high. It also shows examples of a D flip-flop with both positive and negative edge clock pulses where the output Q changes state according to the input D at the rising or falling edge of the clock. Finally, it demonstrates using a D flip-flop for switch debouncing where the output only changes at the negative clock edge.

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    Digital system

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    Chapter 3_Ex-FF-D

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    This document discusses flip-flops and related devices. It describes the operation of an FF-D latch created from NAND gates where the output Q tracks the input D when the clock is high. It also shows examples of a D flip-flop with both positive and negative edge clock pulses where the output Q changes state according to the input D at the rising or falling edge of the clock. Finally, it demonstrates using a D flip-flop for switch debouncing where the output only changes at the negative clock edge.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    31 views7 pages

    Chapter 3 - Ex-FF-D

    Uploaded by

    Minh Phú
    This document discusses flip-flops and related devices. It describes the operation of an FF-D latch created from NAND gates where the output Q tracks the input D when the clock is high. It also shows examples of a D flip-flop with both positive and negative edge clock pulses where the output Q changes state according to the input D at the rising or falling edge of the clock. Finally, it demonstrates using a D flip-flop for switch debouncing where the output only changes at the negative clock edge.

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    HCMC University of Technology and Education

    Faculty of Electrical & Electronic Engineering

    Lecture:
    DIGITAL SYSTEMS
    Chapter 4:
    Flip_Flops and Related Devices

    Nguyen Thanh Hai, PhD


    1
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    This FF-D Latch is created from


    the NAND latch RS as shown in
    figure, in which 2 inputs are
    connected through one NOT
    gate, called input D and
    CLK=Enable is High, and its
    operation is described as in
    Table, X is 0/1.
    - When D=X=0/1, and EN=0, 2
    inputs of 2 NAND gates are 0
    and their outputs are 1 always,
    SET=CLEAR=1 (FF-RS_Latch)
    of 2 NOR gates, Q no change
    as in Table.
    When EN=1 (High active), the
    output Q=D=0/1 as in Table.

    2
    Assoc. Prof. Nguyen Thanh Hai, PhD
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Clocked D Flip-Flop

    In the example using FF-D with positive edge clock pulse, we


    need to consider at times from a to g as shown in figure, at these
    position, we will draw the output waveform Q following the
    change of the input waveform D. For example, at a, positive edge
    CLK, D=0, make Q=0; at d, positive edge CLK, D=1, make from
    Q=0 converting into Q=1, and similar to other cases.

    3
    Assoc. Prof. Nguyen Thanh Hai, PhD
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Clocked D Flip-Flop

    Similarly, FF-D is used in this example has the negative edge


    clock pulse. It means that we just care at times (down-arrow of
    CLK), at this time the output waveform Q will change following the
    state (High/Low) of the input D.

    4
    Assoc. Prof. Nguyen Thanh Hai, PhD
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    FF-D with the high level CLK (Enable), called Latch circuit.

    a b c d
    In this example, Enable (CLK) is High, so during time of High
    Enable, the output waveform Q will change following the change
    of the input waveform D. For example, at position a, Enable
    (High), the input D from High converting into Low, so Q from High
    converting into Low, similar to other positions 5
    Assoc. Prof. Nguyen Thanh Hai, PhD
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    FF-D Synchronization
    A
    Debounced X
    switch

    CLOCK

    In this example, CLK is negative


    CLOCK
    edge, so Q just changes
    following D when CLK is at time
    A
    of the down-arrow. At T1, Q no
    change; at T2, Q changes Q
    following D, and similarly for at
    other positions. X will change X
    through AND gate with 2 inputs  T
    
    T1 T2 4
    and finally we have the final Complete
    Pulses
    T3
    waveform as figure 6
    Assoc. Prof. Nguyen Thanh Hai, PhD
    University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    The End

    7
    Assoc. Prof. Nguyen Thanh Hai, PhD

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