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    Chapter 4 - Asynchronous Up Counters

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    Minh Phú
    This document discusses asynchronous counters. Asynchronous counters have clock inputs that are applied asynchronously to flip-flops (FFs), with the output of one FF connected to the clock input of the next FF. This generates a single clock pulse that propagates through the FFs. In contrast, synchronous counters apply a common clock signal to all FFs simultaneously. The document provides an example of a 4-bit asynchronous counter and explains that it generates all possible binary states from 0000 to 1111 as the clock pulses pass through the FFs. Finally, it notes that an n-bit asynchronous counter can count through 2^n states.

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    Chapter 4 - Asynchronous Up Counters

    Uploaded by

    Minh Phú
    41 views5 pages
    This document discusses asynchronous counters. Asynchronous counters have clock inputs that are applied asynchronously to flip-flops (FFs), with the output of one FF connected to the clock input of the next FF. This generates a single clock pulse that propagates through the FFs. In contrast, synchronous counters apply a common clock signal to all FFs simultaneously. The document provides an example of a 4-bit asynchronous counter and explains that it generates all possible binary states from 0000 to 1111 as the clock pulses pass through the FFs. Finally, it notes that an n-bit asynchronous counter can count through 2^n states.

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    Digital system

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    Chapter 4_Asynchronous Up Counters

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    This document discusses asynchronous counters. Asynchronous counters have clock inputs that are applied asynchronously to flip-flops (FFs), with the output of one FF connected to the clock input of the next FF. This generates a single clock pulse that propagates through the FFs. In contrast, synchronous counters apply a common clock signal to all FFs simultaneously. The document provides an example of a 4-bit asynchronous counter and explains that it generates all possible binary states from 0000 to 1111 as the clock pulses pass through the FFs. Finally, it notes that an n-bit asynchronous counter can count through 2^n states.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    41 views5 pages

    Chapter 4 - Asynchronous Up Counters

    Uploaded by

    Minh Phú
    This document discusses asynchronous counters. Asynchronous counters have clock inputs that are applied asynchronously to flip-flops (FFs), with the output of one FF connected to the clock input of the next FF. This generates a single clock pulse that propagates through the FFs. In contrast, synchronous counters apply a common clock signal to all FFs simultaneously. The document provides an example of a 4-bit asynchronous counter and explains that it generates all possible binary states from 0000 to 1111 as the clock pulses pass through the FFs. Finally, it notes that an n-bit asynchronous counter can count through 2^n states.

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    HCMC University of Technology and Education

    Faculty of Electrical & Electronic Engineering

    Lecture:
    DIGITAL SYSTEMS
    Chapter 4:
    Asynchronous Counters

    Assoc. Prof. Nguyen Thanh Hai, PhD


    1
    HCMC University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Asynchronous Counters
    Asynchronous Counter: CK1 inputs to 1 FF and its output Q1 is CK2 of
    st

    2nd FF, etc. 1

    J PRE
    Q1 J PRE
    Q2 J PRE Q3 J PRE
    Q4
    CLK CLK CLK CLK
    CLK
    K CLR Q1 K CLR Q2 K CLR Q3 K CLR Q4

    1
    Synchronous Counter: CK is connected to all FFs at same time
    Q1
    Q1Q 2 Q 3
    Q2
    Q1
    1
    Q2 Q3

    1
    J 1 PRE Q J 2 PRE Q J 3 PRE Q J 4 PRE Q 4
    1 2 3

    CLK CLK CLK CLK


    K 1 CLR Q 1 K 2 CLR Q 2 K 3 CLR Q 3 K 4 CLR Q 4

    2
    Assoc. Prof. Nguyen Thanh Hai,1PhD
    HCMC University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Asynchronous Counters
    In Counter above, J=K=1; 1 means that connected to +5 Volt, PRE  1 , CLR  1
    - Initial state of all FFs (Q) is level 0; all FFs-JK operate at toggle state. It means that
    the previous state is 0, current state is 1 and inversely.
    - From Figure bellow, 1st clock (CK1), all Qs are 0, only when at time of down-arrow of
    CK1, Q1 goes from Low to High and no change until the down-arrow of CK2 appears,
    Q1 change from High to Low and creates one clock connected to the input CK2 of Q2,
    etc. Finally with 2 CKs, 1 CK of Q1 is obtained or with 2 CKs of Q1, 1 CK of Q2 is
    obtained. Thus after 16 CKs, we obtain 1 CK of Q4
    1 2 16
    Clock

    Q1

    Q2

    Q3

    Q4

    00000001 11110000
    0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 3
    Assoc. Prof. Nguyen Thanh Hai, PhD
    HCMC University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Asynchronous Counters
    Asynchronous Counter is supplied clock pulses asynchronously to
    all FFs.
    1 FF has 1 output Q, so there are two state 0 and 1
    2 FFs have 4 states (22) from Q1Q2=00 to 11
    3 FFs have 8 states (23) from Q1Q2Q3=000 to 111
    n FFs have m states (m= 2n) from Q1Q2…Qn
    Ex: Design 3 FFs

    4
    Assoc. Prof. Nguyen Thanh Hai, PhD
    HCMC University of Technology and Education
    Faculty of Electrical & Electronic Engineering

    Asynchronous Counters

    The End

    5
    Assoc. Prof. Nguyen Thanh Hai, PhD

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