AN1179

DGD05473 DGD0507A Application Note

David Toro, Bipolar Business Unit, Diodes Incorporated
TM
The DIODES DGD05473 and DGD0507A High Frequency, High-Side, Low-Side Gate Drivers in DFN3030-10 are used to optimally drive
the gate of MOSFETs. The DGD05473/07A has an integrated bootstrap diode for ease of design and reduced BOM. Below (Figure 1) is an
example application using the DGD05473 with MOSFETs in a wireless charger transmitter. In this discussion, the important parameters
needed to design in the DGD05473/07A are discussed; main sections are bootstrap capacitor selection, Gate Driver component selection,
decoupling capacitor discussion and PCB layout suggestions.

12V
RRG1 DRG1 CHV2
12V VCC VB CB1
CHV1
CV2
CV1 HIN HO Q1
DGD05473 RG1 CG1
PWM LIN VS
RRG2 DRG2
Control A
EN
LO Q2

COM RG2
CG2

CSA

RRG3 DRG3
VCC VB CB2
Q3
CV3 CHV3
HIN HO
DGD05473 RG3 CG3
PWM LIN VS
RRG4 DRG4
Control B
EN
LO Q4

COM RG4 CG4

CSB

Figure 1. Wireless charger transmitter example application using the DGD05473

AN1179 – Rev 1 1 of 9 November 2022

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 AN1179
Bootstrap Component Selection
Considering Figure 1, when the Low-Side MOSFET (Q2 or Q4) turns on, V S pulls to GND and the bootstrap capacitor (C B1 and C B2) is
charged. When the High-Side MOSFET (Q1 or Q3) is turned on, V S swings above VCC and the charge on the bootstrap capacitor (C B )
provides current to supply the IC High-Side Gate Driver. The charge on CB is provided by VCC through the integrated bootstrap diode and
bootstrap resistor and often the first charge of C B at power up will be the largest current through the bootstrap circuit as typically C B is not
fully discharged at each cycle during normal operation.

Bootstrap Capacitor Discussion

The initial step in determining the value of the bootstrap capacitor (CB) is to determine the maximum voltage drop (ΔV BS) that can be
guaranteed when the High-Side device is turned on. In other words, V BSmin must be greater than the UVLO of the High-Side circuit,
specifically VBSUV- level. Therefore, if VBSmin is the minimum VBS such that:

VBSmin > VBSUV-

Then:
ΔVBS = VCC - VF - VBSmin - V X

Where

- VCC is the supply voltage to the DGD05473

- VF is the voltage drop across the internal bootstrap diode (D BS )
- VX is the voltage drop across the MOSFET

VX is calculated as the current seen across Low-Side MOSFET multiplied by its RDS(ON).

In addition to the voltage drops across these components, other factors that cause V BS to drop are leakages, charge required to turn on the
power devices and duration of the High-Side on time. The total charge (QT) required by the Gate Driver then equals:

QT = QG + QLS + [ILK_N] * THON

Where
QG = gate charge of power device
QLS = level shift charge required per cycle
THON = High-Side on time
ILK_N = sum of all leakages that include:
- IGSS/IGES: Gate-source leakage of the power device
- ILK_DB: Bootstrap diode leakage
- ILK_IC: Offset supply leakage of HVIC
- IQBS: Quiescent current for High-Side supply
- ILK_CB: Bootstrap capacitor leakage

Bootstrap capacitor leakage (ILK_CB) only applies to electrolytic types. Therefore, it is best not to use electrolytic capacitor. Thus, bootstrap
capacitor leakages will not be included in the calculations.

QLS is not listed in the datasheet; for the lower voltage process technology a Q LS of 5nC will be a good approximation and provide a
sufficient margin.

From the basic equation, then the minimum bootstrap capacitor is calculated as:

CBmin ≥ QT /ΔVBS_max

Example using MOSFET

The follow example uses a power MOSFET as the switching device with the following and desired parameters:
 Power device = DMN6017SK3
 Gate Driver = DGD05473
 VCC = 12V
 QG = 26nC
 IGSS = 100nA
 THON = 5µs
 RDS(ON) = 25mΩ, 125°C
 IOUT = 10A
 IQBS = 100µA
 ILK_IC = 1µA
 QLS = 5nC
 VF = 1.0V
 ILK_DB = 1µA
 VGSmin = 3.3V

AN1179 – Rev 1 2 of 9 November 2022

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 AN1179

From equations above:

ΔVBS_max = 12V- 1.0V-3.3V-0.25V = 7.45V

QT = QG + QLS + [ILK_N]*THON; where ILK_N * T HON = 0.5nC

Thus QT = 26nC + 5nC +0.5nC = 31.5nC

Therefore CBmin = 31.5nC / 7.45V= 4.2nF

The bootstrap capacitor calculated in the above solution is the minimal value required to supply the needed charge. It is recommended that
a margin of 2-3 times the calculated value be used, minimally. Utilizing values lower than this could result in over charging of the bootst rap
capacitor especially during –VS transients. Typically for high-speed applications like power supplies, C B = 0.1µF to 1µF are used; and for
low-speed applications like motor drives, C B = 1.0µF to 2.2µF are used. It is recommended to use low ESR ceramic capacitors as close to
the VB and VS pin as possible (see PCB layout suggestions section).

Integrated Bootstrap Diode

The DGD05473/07A has an integrated bootstrap diode to minimize the system BOM and to ease system design. From a DC perspective,
the data below from the datasheet shows the performance of the integrated bootstrap diode:

The current through the integrated bootstrap diode is typically the largest during the first charge of C B. And the current waveform, as well as
the time to charge CB is determined by the size of the C B, see below Figure 2 and Figure 3.

Figure 2. Bootstrap inrush current (Ch3) and V BS (Ch4) with Figure 3. Bootstrap inrush current (Ch3) and V BS (Ch4) with
CB = 0.1µF CB = 10µF

AN1179 – Rev 1 3 of 9 November 2022

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 AN1179

Gate Component Selection

The most crucial time in the gate drive is the turn on and turn off of the MOSFET, and performing this function quickly, but with minimal
noise and ringing is key. Too fast a rise/fall time can cause unnecessary ringing and poor EMI, and too slow a rise/fall time will increase
switching losses in the MOSFET.

Figure 4. Gate Driver High-Side and Low-Side components for DGD05473

Considering the Gate Driver components for DGD05473/07A in Figure 4, with the careful selection of RG1 and RRG1, it is possible to
selectively control the rise time and fall time of the gate drive to the MOSFET. For turn on, all current will go from the IC through RG1 and
charge the MOSFET gate capacitance, hence increasing or decreasing R G1 will increase or decrease rise time in the application. With the
addition of DRG1, the fall time can be separately controlled as the turn off current flows from the MOSFET gate capacitance, through R RG1
and DRG1 to the driver in the IC to V S for High-Side and COM for Low-Side. So, increasing or decreasing R RG1 will increase or decrease the
fall time. Sometimes finer control is not needed and only R G1 and RG2 is used.

Increasing turn on and turn off has the effect of limiting ringing and noise due to parasitic inductances, hence with a noisy environment, it
may be necessary to increase the gate resistors. Gate component selection is a compromise of faster rise time with more ringing, and a
poorer EMI but better efficiency, contrasted with a slower rise time with better EMI, better noise performance but poorer eff iciency. The
exact value depends on the parameters of the application and system requirements. RG1 and RG2 values are typically between 10Ω and
50Ω, optimal value decided by MOSFET gate capacitance and drive current of Gate Driver. Gate resistor values are increased to decrease
system noise, minimize ringing, and hence lower EMI. RRG1 and RRG2 values are typically between 5Ω and 20Ω, optimal value decided by
MOSFET gate capacitance and drive current of Gate Driver. Also, sink current gate resistor values are increased to decrease system noise,
minimize ringing, and hence lower EMI.

To have equal switching times for High-Side and Low-Side, it is recommended that the Gate Driver components for High-Side and Low-
Side are mirrored. For example, RRG1=RRG2, DRG1=DRG2 and RG1=RG2.

The gate to source capacitors, C G1 and CG2, are used to minimize unexpected shoot-through in the Half-Bridge and to improve system
stability. The shoot-through can decrease efficiency or even damage the MOSFETs; this phenomenon is discussed further on page 6. If the
Ciss of the MOSFET is small and there is instability in the system performance, add C G1 and CG2 to improve stability. To begin,
CG1=CG2=1nF should improve system performance.

VCC Decoupling Capacitors

For optimal operation, V CC decoupling is crucial for all Gate Driver ICs. With poor decoupling, larger VCC transients will occur at the IC when
switching, and for greater and longer V CC drop the IC can go into UVLO.

VCC

HIN

LIN

Figure 5. Suggested VCC decoupling

AN1179 – Rev 1 4 of 9 November 2022

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 AN1179

As shown in Figure 5, two decoupling capacitors are recommended CV1 and CV2. CV1 can be a larger electrolytic, for example 47µF, 50V,
used to dampen low frequency drains on supply; C V1 does not need to be right next to the IC. But C V2 is used to decouple faster edge
changes to VCC and should be a low ESR ceramic capacitor placed close to the V CC pin. This component provides stability when V CC is
quickly pulled down with load from the IC; typical values are 0.1µF to 1µF.

For applications with multiple Gate Driver ICs (for example, a BLDC motor drive with 3 x Gate Drivers), one larger electrolytic (C V1) can be
used and the three ceramic caps (C V2, C V3, CV4) should be used close to the V CC pin (see Layout section also).

High Voltage Decoupling Capacitors

Considering the performance of the whole Half-Bridge, it is important to have appropriate high voltage decoupling capacitors (see C HV1,
CHV2, and C HV3 in Figure 1). For best stability (best high frequency performance), C HV2 and C HV3 are smaller ceramic capacitors (say 1µF
100V) placed close to the drain of the MOSFETs at the Half-Bridge (less than 25mm); and then C HV1 is the electrolytic bulk capacitor which
is typically part of the on-board power supply. If the small decoupling capacitors (C HV2 and CHV3) are not used, then for optimal operation,
the bulk capacitor (C HV1) should be close to the drain of the MOSFETs (less than 25mm). For even further high frequency decoupling,
many parallel ceramic capacitors can be used; for example, 1.0µF in parallel with 3 x 0.1µF capacitors.

Input resistors
The IC PWM inputs, HIN, LIN, and EN, are very high impedance inputs with pull-down resistors. The pull-down resistors on HIN, LIN, and
EN have an approximate value of 100kΩ.
HIN

EN

LIN

Figure 6. Input logic for the DGD05473

Differences between DGD05473 and DGD0507A

The minimum allowed V CC operating condition is the main difference between the DGD05473 and the DGD0507A. Hence the V CC
Recommended Operating Voltage and UVLO (both VCC and VBS ) are the main specifications where the two devices differ.

Figure 7. Recommended operating voltages for the DGD05473

Figure 8. VCC UVLO for the DGD05473 (V BS UVLO is the same)

Figure 9. Recommended operating voltages for the DGD0507A

Figure 10. VCC UVLO for the DGD0507A (V BS UVLO is the same)

AN1179 – Rev 1 5 of 9 November 2022

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 AN1179

Suggestions for VCC = 5V operation using the DGD05473

Due to the performance of the Gate Driver outputs at low voltages, the minimal operating voltage level on V B = 4.3V. For VCC = 5V operation,
this is not a concern for Low-Side operation as it is operating at V CC, but the High-Side output driver is operating at a diode drop from
internal bootstrap diode; hence when V CC=5V, VBS=4.3V, which would be ok. But for a system with operating V CC=5V, it is typical to require
VCC=4.5V to 5.5V, and when V CC=4.5V, VB will be below the Recommended Operating Condition. Hence when wanting to use V CC = 4.5V to
4.9V operation it is required to use an external Schottky diode (see Figure 11).

VCC VCC
CC V
VB

HIN HIN
HIN HO
HO
TF05473
DGD05473
LIN LIN
LIN V
VS

EN EN
EN LO
LO

R4 COM
COM

Figure 11. Typical application necessary for V CC=4.5V to 4.9V, an external bootstrap Schottky will turn on before internal D BS

Matching Gate Driver with MOSFET

IC drive current and MOSFET gate charge

Gate Driver ICs are defined by their output drive current, its ability to source current to the gate of the MOSFET at turn on and to sink
current from the gate of the MOSFET at turn off. For the DGD05473 the drive current is IO+ = 1.5A typical and IO- = 2.5A typical.

For a given MOSFET, with the known drive current of the DGD05473, you can estimate how long it will take to turn on/off the MOSFET with
the equation:
t = Qg/ I

Qg = total charge of the MOSFET as provided by the datasheet

I = sink/source capability of the Gate Driver IC
t = calculated rise/fall time with the given charge and drive current

For example, with the Diodes’ DMN6017SK3, 60V 43A, Q g = 55nC; and with the DGD05473 IO+/IO, tr = 37ns and tf = 22ns. These are
estimates as the total charge given in the datasheet may not be the same conditions in the application. An addition of a gate resistor will
increase the tr and tf.

Unexpected shoot-through with dVDS/dt

Unwanted MOSFET turn-on, caused by CGD x dVDS/dt (see Figure 12) is often the cause of unexplained shoot through in the Half-Bridge
circuit. Depending on the ratio of the C GS/CGD , when the dVDS/dt across Low-Side MOSFET (Q2) occurs (i.e when High-Side MOSFET turns
on), there can be a voltage applied to the gate of the Q2 MOSFET, turning on Q2 and causing shoot through. In effect a gate bouncing
occurs causing a ringing on the V S line and the power ground.

VS
IGD CGD
Q2

CGS

Figure 12. Unexpected shoot through with dVDS/dt

AN1179 – Rev 1 6 of 9 November 2022

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 AN1179

Considering Figure 12:

IGD = CGD x dVDS/dt

IGD will flow towards the resistive load (and small inductive due to parasitics) of the Gate Driver and the CGS of the MOSFET. Hence this
unwanted condition may be minimized by looking at the Ciss/Cres in the MOSFET datasheet (Ciss/Cres gives an indication of C GS/ CGD);
having a Ciss/Cres as large as possible will minimize this phenomenon. An external capacitor can be added to the gate-source of the
MOSFET (for example 1nF) which will increase C GS/CGD.

Minimum Pulse Operation

The DGD05473 has an RC filter on the input lines to be more resilient in noisy environments. During typical operation, the DGD05473 will
respond to an input pulse greater than about 40ns. Hence for an input pulse greater than 40ns approximately, the IC will follow the pulse as
expected; and for an input pulse less than 40ns, there will be no response from the IC.

PCB layout suggestions

Layout also plays a considerable role since unwanted noise coupling, unpredicted glitches and abnormal operation could arise due to poor
layout of the associated components. Figure 13 shows the schematic with parasitic inductances in the high current path (LP1, LP2, LP3, LP4)
which would be caused by inductance in the metal of the trace. Considering Figure 13, the length of the tracks in red should be minimized
and the bootstrap capacitor (CB) and decoupling capacitor (CD) should be placed as close to the IC as possible as well as using low ESR
ceramic capacitors. Finally, the gate resistors (R GH and RGL) and the sense resistor (R S ) should be surface mount devices. These
suggestions will reduce the parasitics due to the PCB traces.
VBUS

CBUS
RGH
HO
VBB
V

CB LP1
Minimize area Keep high voltage and
VS high current line away
from logic and analog
VCC
VCC LP2 lines
CD
RGL

LO
LO

LP3
COM
COM
RS

LP4

Figure 13. Layout suggestions for DGD05473/07A in a Half-Bridge, lines in red should be as short as possible.

VCC VI N+

C4
C2
V
VCC
CC VVBB C1

HIN
EN HO
HO
DGD05473
DGD05473 R2
LIN
HIN VVSS

EN
LIN LO
LO

COM
COM
R4

Figure 14. Schematic for layout example shown in Figure 15

AN1179 – Rev 1 7 of 9 November 2022

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 AN1179

Figure 15. Suggested layout of the schematic shown in Figure 14, DGD05473 in DFN3030-10.

AN1179 – Rev 1 8 of 9 November 2022

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 AN1179

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AN1179 – Rev 1 9 of 9 November 2022

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