Power Supply Design Seminar

Common Mistakes in Flyback Power

Supplies and How to Fix Them

Reproduced from
2020 Texas Instruments Power Supply Design Seminar SEM2400
TI Literature Number: SLUP398
© 2020 Texas Instruments Incorporated

Power Seminar topics and online power training modules are available at: ti.com/psds
Common Mistakes in Flyback Power
Supplies and How to Fix Them

Brian King
Michael O’Loughlin
Agenda
• Introduction to low power AC/DC flyback converters
• 10 common design/performance issues
– Examine scenario and symptoms
– Group debug discussion
– Problem resolution
– Troubleshooting, tips and guidance
– References provided for deeper study
• Summary

“Experience is simply the name we give our mistakes.” – Oscar Wilde

2
Introduction
AC to DC Flyback Converter
1 LA
DG
1. Bridge rectifier T1

470 µH NP NS
2. EMI filter DA DC
CA CB DZ RS DF VOUT
COUT
3. Flyback power stage
DD
VIN DB
2 RT
4. PWM controller CS
3
RG2 QA
5. Feedback VOUT
DE RF1
a) Primary-side regulation
6 RG2 RCS
R1 R2 5b
b) Secondary-side regulation VS
CDD UCC28704
Opto
6. AUX supply with startup RS1 R3
T1 2 VDD DRV 3
R4
NA 6 VS CS 4
C1
5 GND
RS1

5a 4 R5

3
 1A) Why does the power supply not start?

85 - 265 VAC 50/60 Hz

+ Ch 2: Q1 VDS 100 V/div
24V/1A
- Ch 3: VDD 10 V/div

+ Ch 1: 24 VOUT 10 V/div
15V/3mA
- 20 ms/div

15 V / 3 mA loading prevents
VDD from reaching UVLO
turn-on threshold

4
 1B) Why does the power supply not start?
Ch 2: Q1 VDS 100 V/div 20 ms/div

85 - 265 VAC 50/60 Hz

+
24V/1A
- Ch 3: VDD 10 V/div

Ch 1: 24 VOUT 10 V/div

+
15V/3mA
-
Ch 2: Q1 VDS 100 V/div 10 ms/div

D6 separates Ch 3: VDD 10 V/div

15V/3mA from VDD

Ch 1: 24 VOUT 10 V/div
Not enough capacitance to prevent VDD
C3 increased to 6.8 µF
from dropping to UVLO turn-off threshold
5
Startup tips and tricks
• Properly size CDD
• Types of startup circuits:
– Resistive
– Active
• Controllers that minimize CDD
– Wide UVLO hysteresis
– Low operating current
• Watch out for: *+,-.,/0
– Properly set number of AUX turns 𝐶"" = 𝐼%&'( ×123456 71234588
– Extra loading on VDD
– Capacitance vs. DC bias of ceramic caps
– Long startup times
• Charging excessive output capacitance

6
 2A) Why is your power supply shutting down?
+ Ch 1: VCC 10 V/div Ch 2: VSW 100 V/div
5V/5A
-
120 VAC
60 Hz

Ch 3: VCS 500 mV/div

VOVP(min)= 2.85 V

Ch 4: VQR 2 V/div 2 µs/div

Triggering OVP

7
Adjusted and filtered AUX voltage sense
+
5V/5A
-
120 VAC
Ch 2: VSW 100 V/div
60 Hz

VOVP(min) = 2.85 V

Ch 4: VQR 2 V/div 2 µs/div

8
2B) Why is your power supply shutting down?
• 12 V output was regulating and just shut down
• OVP trip point set at 24 V on AUX winding
LEB = 255 ns

Ch 1: VOUT 2 V/div
Ch 1: VOUT 2 V/div
VOCP(min) = 1.35 V
VOVP = 24 V
Ch 4: AUX Winding 10 V/div
Ch 4: VRCS 500 mV/div

1 µs/div
4 µs/div

OCP triggered by trailing-edge spike,

caused by dv/dt on switch node capacitor

9
Peak current mode control, OCP and OVP review
• Use an RC to filter spikes on the current sense pin
• Know your controller – study the data sheet!
• For the example shown below:
1
– Peak current is controlled by FB voltage (0.75 Vpeak) 𝑓: ≥ 10×𝑓(> =
2𝜋𝑅B 𝐶B
– OVP sensed on AUX winding, after TLK_RESET during tdmag
– OCP sensed on CS pin, > 1.5 V, all the time
• Common protection mechanisms:
– Cycle-by-cycle OCP VBULK = 70 V to 375 V VOUT
– Shutdown OCP NP COUT
NS
– OTP RT Partial Schematic and Block Diagram

OSC
– VDD S Q
DRV IP
Q Feedback
– UVLO
R
AUX VREF
VDD Network
+

– Line UV NA –

CDD 0.75V
RS1 22V/7.7V

– OPP VS
RESET UVLO
on OVP/OCP
+
–

FB
+

4.65V Q1
–

RS2 OVP CS
+

–
1.5 V RCS
GND OCP

10
3) Why are some units losing regulation?
+
• OVP issue resolved on QR pin
5V/5A
- • Now 2% return rate from field
120 VAC
60 Hz
• Returned units shut down under
heavy load for extended time

Current-starved optocoupler

11
Properly biasing optocoupler feedback
FGG HI Design Procedure
𝐶𝑇𝑅D&E = = 0.33 for R11=5 kΩ
JGG HI
FGG HI
1. Find max collector current needed
= UVG HI = 0.13 for R11=2 kΩ
2. Find max forward current available
5V
3. Calculate min CTR needed
300 µA max 100 µA
Tips and Tricks
+
1V • Reduce R11 or choose higher
-
CTR to improve situation
+
2.5 V minimum
• Consider CTR initial tolerance +
- forward current + temperature +
life
• Study the internal block diagram
P/N suffix CTR min CTR max from data sheet!
A 80% 160%
B 130% 260% • Watch out for loop gain increase
C 200% 400%
D 300% 600% • TLV431 provides extra 1.25 V
None 80% 600% across R11

12
4) Why is the SR getting hot?
+
5V/5A
-
120 VAC
60 Hz
~10 ARMS in Q1

Q1 not fully
enhanced at 5 V
Ch 1: Q1 Drain 5 V/div

Ch 2: Q1 Gate 5 V/div
2 µs/div

13
A more appropriate synchronous rectifier

CSD18532NQ5B CSD17559Q5

14
Gate drive tips
• Pay attention to turn-on threshold of FET
• Size VCC capacitor to hold 10 • Qg
Driver
• Use a gate driver resistor to:
– Limit drive current, older PWMs not I limited
– Damp gate ringing
– Soften dv/dt slew rate for EMI
– Reduce turn-on current spike
Driver
• Discharging CSW
• Reverse recovery of output diode
• Shoot-through of synchronous rectifiers
• Fast turn-off with slow turn-on Driver
• Minimize turn-off switching loss
• Less susceptible to bounce back from D-G charge

15
5) Why is the clamp getting so hot?
Pri:Sec = 4:1
Leakage = 4 µH
Efficiency = 88.8%

115 VAC / 60 Hz; 1.5 A Load

Ch 1: Q1 Drain 100 V/div

Ch 3: I Primary 1 A/div

1 µs/div
Clamping voltage too low

16
Reset leakage faster to reduce clamp loss
Clamping Tips
Minimize leakage reset time*
• Some magnetizing energy is lost in clamp
• Clamp voltage as high as possible
TVS = SMCJ150A
• Minimize leakage inductance
Efficiency = 89.7%
TVS clamp
• Predictable and repeatable
• Good efficiency at very light loads
115 VAC / 60 Hz; 1.5 A Load
Resistor-capacitor clamp
Ch 1: Q1 Drain 100 V/div
• Cheap
• Resistor package sized for power loss
• Burns more power at very light loads
Active clamp
• Best efficiency – recycles leakage energy
Ch 3: I Primary 1 A/div
• Lower noise
1 µs/div • Requires specialized controller
* See reference [3]

17
6) How can we reduce standby power loss?
EU Code of Conduct Tier 2
75 mW maximum

Fixed 100 kHz FSW

18
A better answer for low standby power
Low Standby Checklist
Controller features
• Low startup power
‒ Low startup current
‒ Active startup circuit
(depletion mode FET)
• Light load modes
‒ Low FSW
‒ Burst mode
• PSR
FET features
• Low COSS
• Low gate charge
Input Voltage (VRMS) Rectifier features
• Low junction capacitance

19
7) What’s causing the negative spike on CS?
Current Sense TOP VIEW
Return Path
PG
N
D

U1 PGND Connection

PGND BOTTOM VIEW

LEB = 225 ns Ch 2: VCS 500 mV/div
PGND

High inductance in current

sense return path Absolute Min.
PGND
V CS = -0.5 V
Current Sense
Return Path 500 ns/div

20
An improved layout
TOP VIEW Layout Tips
Parasitic inductance
• Minimize area of switching current loops
• Use ground planes where possible
• Place capacitors directly between VCC pins and ground
Parasitic capacitance
• Minimize cross-sectional area of switch node
• Cross traces orthogonally
• Ground heat sinks
Parasitic resistance
BOTTOM VIEW
• Place power components near each other
• Know the high current paths
• Estimate etch resistance – count the squares
• Use wide, short etch for high current paths
Noise mitigation
• Avoid high currents through signal ground
• Minimize traces between resistor dividers
• Don’t place ICs or traces under magnetics

21
8) How can we increase the phase margin?

6.2 kHz bandwidth

44º phase margin

22
TL431 integrating capacitor effects

23
Optocoupler pull-up resistor effects

24
Compensating isolated supplies with a TL431
R4=0

𝑅]
20 Z log Z 𝐶𝑇𝑅
𝑅F

1
𝑓^ = 𝑓: (X :*X )
2 Z 𝜋 Z 𝐶F Z 𝑅J

2ab (() ef Z ghe Fj( Zgi Z eo jep

= k ×
25cd (() ei Z (Fj ) ( Z gi Zeo
l Z m Za0(n0,n)

𝑅] 𝑅J + 𝑅`
20 Z log Z 𝐶𝑇𝑅 Z
𝑅F 𝑅J

• Scaling R6/R1 is the only way to attenuate gain!

• Eliminating inner loop also an option 𝑓^ =
1
𝑓: (X :*X )
2 Z 𝜋 Z 𝐶F Z 𝑅J Z 𝑅`

25
9) Where is that buzzing sound coming from?

26
9) Where is that buzzing sound coming from?

Drum core inductor acts

like a speaker

27
A quiet inductor

28
Avoiding audible noise transducers
• Secure through-hole components with high energy
• Transformers
‒ Core halves glued
‒ Assembly varnished
• Inductors
‒ Avoid constructions with loose parts
• Ceramic capacitors
‒ Place at edge of PCB
‒ Mount symmetrically on opposite sides of PCB
‒ Add slit in PCB under MLCC

29
10) Why is there excessive low frequency ripple?

95 VAC Input; 4 A Load

Ch 1: VOUT (AC-Coupled 200
mV/div)

Ch 2: VBULK 50 V/div
Not enough bulk input capacitance
and limited max duty-cycle 5 ms/div

30
Bulk input capacitor considerations
90 VAC Input; 4 A Load – 2 x 68 µF Bulk Cap Needed to Maintain 80 V
Valley at 90 VAC / 50 Hz
Ch 1: VOUT (AC-Coupled 200 mV/div) 100 1400

100 Hz Ripple Current (mARMS)

90
1200
Bulk Capacitance (µF)

80
70 1000
60 800
50
40 600
— Cin
CIN
30 400
Ch 2: VBULK 50 V/div
20 — IIrms
RMS
200
10
0 0
5 ms/div 0 20 40 60 80
Input Power (W)

• 1.5 µF/W is a good rule of thumb for 90 VAC minimum input

• Watch RMS current; consider both 100 Hz & 100 kHz content
• Bulk cap is usually the least reliable component in power supply – determines product life
• Arrhenius’ law: capacitor life doubles for every 10ºC decrease in temperature
• ESR increases significantly at low temperatures

31
Summary: Low power AC/DC troubleshooting
• Startup issues – start by monitoring VDD , VOUT and VSW
• Shutdown issues – understand all possible shutdown mechanisms of the controller
(read the data sheet!)
• Regulation issues – check operation of TL431 & optocoupler
• Efficiency/thermal issues – use thermal camera to identify problem spots; understand
core/copper loss in transformer
• Standby power issues – use a controller with light load mode and active startup
• Layout issues – understand how parasitic inductance and capacitance are manifested
and how to mitigate
• Stability issues – understand the frequency response of TL431 circuit
• Audible noise issues – know what components act as transducers
• Bulk capacitor issues – check operation and life at min input, max load

32
References and further reading
• “Control Challenges for Low Power AC/DC Converters,” Brian King, Rich Valley, TI Power Supply Design Seminar 2014
SEM2100, slup325. http://www.ti.com/lit/slup325

• “Power Tips #81: Make sure your optocoupler is properly biased,” Brian King, EDN Network, October 2017.
https://www.edn.com/electronics-blogs/power-tips-/4459005/Make-sure-your-optocoupler-is-properly-biased

• “Flyback transformer design considerations for efficiency and EMI,” Isaac Cohen, Bernard Keogh, TI Power Supply Design
Seminar 2016 SEM2200, slup338. http://www.ti.com/lit/slup338

• “The Magnetics Design Handbook For Switching Power Supplies,” Lloyd H. Dixon, slup132 (slup123/4/5/6/7/8).
http://www.ti.com/lit/slup132

• “Designing Magnetic Components for Optimum Performance in Low Cost AC/DC Converter Applications,” Seamus
O’Driscoll, Peter Meaney, John Flannery, George Young, TI Power Supply Design Seminar 2010 SEM1900, slup265.
http://www.ti.com/lit/slup265

• “Constructing Your Power Supply – Layout Considerations,” Robert Kollman, TI Power Supply Design Seminar 2004
SEM1600, slup230.
http://www.ti.com/lit/slup230

• “Power Tips: Compensating Isolated Power Supplies,” Brian King, EE Times, February 2015.
https://www.eetimes.com/author.asp?section_id=36&doc_id=1325778#

Further references listed in full paper

33
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