CSE413 Microprocessor-Based Systems

General Purpose IO (GPIO)

 Peripheral Modules
▪ Embedded systems typically:
▪ Collects/Displays data from System Sensors
1. The underlying system by suitable sensors under
control
2. The operator requirement
▪ Control the underlying system in
response to sensors measurements and MCU
Actuators
operator requirement by suitable actuators

▪ Collecting sensory data and acting in response are done through peripheral modules integrated with
the MCU. It could be in one of two forms:
1. Digital:
▪ Parallel: One bit (from switch/button) or a collection of bits forming one entity (a byte/word)
▪ Serial: A collection of bits transmitted or received on a serial link (wired/wireless)
2. Analog:
▪ Input from an analog sensor e.g., temperature sensor, or output to control a motor.
Analog inputs need ATD converter, and analog outputs need DTA converter to interface to the MCU.

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➢ A peripheral module is viewed by the application code as a group of locations (registers) categorized as
CONTROL, STATUS, and DATA registers:

Peripheral modules must be The current status of the

CONTROL STATUS
configured before being used by peripheral module is read
REGISTERS REGISTERS
the application for IO operations. from status registers within
the module.
To configure a peripheral module
is to agree upon the protocol of
doing future IO operations. DATA
REGISTERS
Configuration is done by writing
bits in specific fields in the control
registers within the module. Input data are read from, and
output data are written to
Configuration is done by the registers within the module.
startup code before passing
control to the application.
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 Memory Mapped IO

Control Registers
Status Registers
4G Address space

Data Registers
Peripheral module registers

Memory Map for the KL25Z128VLK4 implementation

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 ▪ Let’s start with the basics of the simplest form of digital input/output:

General-purpose IO (GPIO)

▪ A general-purpose input/output (GPIO) in a MCU is

◦ A digital IO peripheral module, with bits connected to MCU pins.

Suitable to:
▪ Read switches/buttons state, hex keypad, …

▪ Write to LEDs, relays, LCD, …

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 Several points must be clear before using GPIO ports:

◦ The number of available ports in the MCU and their size (number of bits in each)

SOFTWARE ◦ Configuration:
‒ Connection between port bits to MCU pins
‒ Defining data direction: input or output:
• Is direction configurable?
• Is it defined for the port as a whole or on a port-bit basis?
• What can we do to output port bits: send data, set, clear, or toggle port bits

HARDWARE ◦ Circuit interfacing to port pins:

‒ Acceptable voltage levels for logical 1 and 0
‒ Current sourcing and sinking capabilities
‒ Need for pull-up or pull-down resistors
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 KL25Z GPIO: Capabilities
▪ The KL25Z GPIO peripheral module has
five 32-bit ports,:
1. PORTA To optimize functionality in small
2. PORTB packages, pins have several functions
3. PORTC available via signal multiplexing.
4. PORTD
5. PORTE

▪ Although each port could be up to 32 bits

wide, there are not enough pins on the
MCU package to support all these bits.
MKL25Z128VLK4 80-pin package
Hence,
Not all port bits are implemented.
The MCU’s data sheet pin-out section
describes which port bits are implemented.
Quantity depends on package pin count,
which differ from one MCU to another.

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 ➢ Configuration:
1. Enable clock to the selected GPIO port (Done on a port basis)

1. Connect the selected port pin to the GPIO module via the multiplexer(Done on a bit basis)

2. Select port bit direction (input or output) (Done on a bit basis)

➢ Operation:
▪ To read a port bit that is configured for input:
Read PORT INPUT DATA REGISTER
▪ To change port bit(s) configured for output by:
A write to PORT OUTPUT DATA REGISTER, or
Set/Clear/Toggle bits by writing ONE(s) to respective bits is the corresponding PORT
SET/CLEAR/TOGGLR REGISTER
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KL25Z GPIO: Clock Gating
➢ By default, peripheral modules are disabled (no clock connected) to save power.

Clock should be gated to only those modules needed in the application.

Writing to an un-clocked module triggers a hardware fault!

➢ System Integration Module (SIM) is used to provide clock to only the active modules.

SIM is controlled through a group of registers named SIM_ . . .

➢ To do digital IO, we need to enable clock to a GPIO module.

To enable clock to a GPIO port, PORTA…PORTE, set its corresponding bit in the control register SIM_SCGC5.

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▪ A port bit is connected to a MCU pin:
Example: (MKL25Z128VLK4 80-pin package)
PORTA bit 1 is connected to pin PTA1 (pin 27) Peripheral Modules
PORTE bit 30 is connected to pin PTA30 (pin 22)

▪ The Port Control Block controls:

• which signal is present on the external pin
• interrupt enable on each pin
• signal characteristic on each pin
..
.
▪ A port bit can be connected to a signal from
one peripheral module via the bit multiplexer.
• The multiplexer is controlled by a 3-bit
A port bit can be configured to connect to ONE of several peripheral modules:
MUX field in a pin control register (PCR).
• The 3-bit MUX field can theoretically GPIO, UART, Timer, … via a multiplexer
select 1 out of 8 alternative signals.

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 KL25Z GPIO Port Bits Direction (input or output)
▪ Each GPIO bit Qi can be
QDi
configured individually to
work as:
• Input bit or
• Output bit Qi

▪ An input bit allows the

program to read a single bit
value on an MCU pin.

▪ An output bit enables the

program to set an MCU pin
to either 1 or 0.
Configuring one port bit, Qi , for input or output is done by clearing or setting the
corresponding bit, QDi , in the Port Data Direction Register:
‒ To configure Qi for input, set QDi to ZERO.
‒ To configure Qi for output, set QDi to ONE.

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 1. Enabling Clock to GPIO Port
▪ The register SIM_SCGC5 is 32-bit.
Only 16 bits are shown below.
▪ Bits 9 through 13 are five separate bits
labeled PORTA through PORTE. Each bit
enables clock to the corresponding port.
For example, if we need to enable clocking of
PORTA and PORTE before accessing each of
them, we should set bits 9 and 13 in
SIM_CGC5 to 1.

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Lower 16 bits of register SIM_SCGC5
2. Connecting a Port Pin to GPIO Module

Port Control Register (PCR) fields, one register per bit

MUX (bits 10-8) Configuration

000 Alt 0 Pin disabled (analog)
001 Alternative 1 – GPIO
010 Alternative 2
011 Alternative 3
100 Alternative 4
101 Alternative 5
110 Alternative 6
111 Alternative 7
MUX-field alternatives
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3. Configuring Port Data Bit Direction (Input or Output)
Data Bus Address
bit n Bus

Each bit can be configured individually for either Address

Decoder
input or output:
PDDR select

▪ Input direction (Red arrow), Port Data Output Enable

D Direction Q
Port Data Direction Register bit should be 0 Register

▪ Output direction (Blue arrow),

PDOR select

PSOR select
Port Data Direction Register bit should be 1 PCOR select
Set
Output
Rst Port Data
PTOR select Direction Pin or
Tgl Output
Pad on
D Register Q package
When the MCU is reset, the port data direction Input Enable
bit is set to 0. (Why?)
I/O Clock
PDIR select
Port Data Pin Control
D Input Q Register
Register MUX field
Input Direction

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 KL25Z GPIO: Port Bit Circuitry
Data Bus
bit n
Address
Bus
Control
▪ Control (At startup)
Address
▪ Direction (input or output) Decoder

▪ MUX (GPIO or other peripheral) PDDR select Direction

Then the program can read from input pins or D

Port Data
Direction Q
write to output pins. Register

PDOR select

▪ Data (Application code) PSOR select

Set
Pin Connection
PCOR select
▪ Input data
Rst Port Data
PTOR select Pin or
Tgl Output
Pad on
D Register
▪ Output (different ways to access it) Q package

‒ Data
‒ Set PDIR select
I/O Clock

‒ Clear Port Data Pin Control

D Input Q Register
‒ Toggle Register MUX field

Data
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GPIO Control and Data Registers in Memory

Six registers

▪ One set of control registers per port

▪ Each bit in a control register corresponds to a port bit

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Port Data and Control Registers
Data Bus Address
Bus
▪ PDDR:
bit n

Writ Data Bus bit n to PDDR bit n to select Address

port bit direction. Decoder

PDDR select
▪ PDOR:
Writ Data Bus bit n to PDOR bit n. Port Data
D Direction Q
Register
▪ PSOR:
PDOR select
Set selected bits in PDOR
PSOR select
Set
▪ PCOR:
PCOR select
Rst Port Data
PTOR select Pin or
Tgl Output
Clear selected bits in PDOR D Register Q
Pad on
package

▪ PTOR
Toggle selected bits in PDOR PDIR select
I/O Clock

Port Data Pin Control

▪ PDIR D Input
Register
Q Register
MUX field

Read Port Data bit n to Data Bus bit n.

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GPIO Module Operations
➢ Input:
Values are read from the GPIOx_PDIR register.

➢ Output:
Values are written to the GPIOx_PDOR register.

➢ Set bits:
Writing an integer N to GPIOx_PSOR will set all the port bits that correspond to all
bits that are ones in N.
Example: To set the least significant byte of PTA, write 0x000000ff to GPIOA_PSOR
(PTA->PSOR).

➢ Clear bits:
Writing an integer N to GPIOx_PCOR will clear all port bits that correspond to all
bits that are ones in N.
Example: To clear the least significant byte of PTA, write 0x000000ff to
GPIOA_PCOR (PTA->PCOR).

➢ Toggle bits:
Writing an integer N to GPIOx_PTOR will invert all port bits that correspond to all
bits that are ones in N.
Example: To invert the least significant byte of PTA, write 0x000000ff to
19 GPIOA_PTOR (PTA->PTOR).
 INTERFACING
Software

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 Let’s consider a simple problem:
Basic GPIO Example Light up a LED in response to a switch

Input to MCU pin

Output from MCU pins

One input from a switch Two outputs to LEDs

▪ Goal: light either LED1 or LED2 based on switch SW1 position.

▪ SW1 pressed → Red led (LED1) ON, Blue led (LED2) OFF
▪ SW1 not pressed → Red led (LED1) OFF, Blue led (LED2) ON
▪ GPIO
▪ Input: Determine if switch SW1 is OPEN or CLOSED
▪ Output: Set outputs LED1Out / LED2Out to 1 or 0

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Basic GPIO Example
We can easily recognize two phases for this basic GPIO program:

1. Configuration:

• Enable the GPIO module by gating the clock to the module

• Configure each selected port bit for input or output (one input and two output bits)

• Connect the selected pins to selected port bits

2. Operation:

• Loop reading the switch state and updating the LEDs accordingly

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I- Configuration: Pseudocode
Configuration is done by setting fields in control registers.

// Enable clock to PTA1 by setting PORTA field in SIM_CGC5

set bit 9 of SIM_SCGC5

// Set MUX field in PCR of PTA1, PTA2, and PTA5 to 001 to connect pins to GPIO
set MUX field (bits 8-10 in PORTA_PCR1) to 001
set MUX field (bits 8-10 in PORTA_PCR2) to 001
set MUX field (bits 8-10 in PORTA_PCR5) to 001

// Make PTA1 and PTA2 outputs Need to know the addresses of registers:
set bits 1 and 2 of GPIOA_PDDR 1. SIM_SCGC5
2. PCR of pins PTA1, PTA2, and PTA5
3. GPIOA_PDDR,
// Make PTA5 input and the positions of the fields:
clear bit 5 of GPIOA_PDDR 1. PORTA in SIM_SCGC5
2. MUX field in PCR
Hard to remember!
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2- Operation: Program Loop Pseudocode

// Initialize the output data values: LED 1 off, LED 2 on

clear bit 1, set bit 2 of GPIOA_PDOR
do forever {
if bit 5 of GPIOA_PDIR is 1 {
// switch is not pressed, then light LED 2
set bit 2 of GPIOA_PDOR
clear bit 1 of GPIOA_PDOR
} else {
// switch is pressed, so light LED 1
set bit 1 of GPIOA_PDOR Need to know the addresses of:
clear bit 2 of GPIOA_PDOR • GPIOA_PDOR
} • GPIOA_PDIR
}

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Need to Reference Control & Data Registers
In our application, we need to reference
the control registers:
▪ SCGC5 in the SIM module
▪ PCRs of the pins used for input and output
▪ The port data direction register

and the data registers:

▪ The port input data register
▪ The port output data register

So, it is helpful if we define meaningful names for all the above

registers’ addresses.

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Definitions of Pointers to Control & Data Registers
/* System Integration Module System Clock Gating Control Register 5*/
#define SIM_SCGC5 (*((volatile unsigned int*)0x40048038))

/* PortA PCR 1, PCR 2, and PCR 5 */

All these
#define PORTA_PCR1 (*((volatile unsigned int*)0x40049004))
addresses are
#define PORTA_PCR2 (*((volatile unsigned int*)0x40049008)) defined in the
#define PORTA_PCR5 (*((volatile unsigned int*)0x40049014)) KL25Z
manual.
/* PortA PDDR, PDOR, and PDIR */

#define PORTA_PDDR (*((volatile unsigned int*)0x400FF014))

#define PORTA_PDOR (*((volatile unsigned int*)0x400FF000))

#define PORTA_PDIR (*((volatile unsigned int*)0x400FF010))

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Accessing Hardware Registers in C
It would be tedious to have to look up and remember the addresses for all hardware control registers,
and the field positions.

Instead, we use special C-language support:

The Common Microcontroller Software Interface Standard (CMSIS).

➢ The CMSIS is a hardware abstraction layer for Cortex-M processors, developed and distributed by
ARM.

➢ The CMSIS-CORE component provides a C-language interface to the processor core and peripherals.
It simplifies software reuse, reduces the learning curve for developers, and reduces the time to market.

➢ It consists of:
▪ Macros and functions to perform various operations, and
▪ C data structures that map directly to registers.
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CMSIS - Accessing Hardware Registers in C
The SIM peripheral’s control registers, for example, can be accessed in the C program by CMSIS-CORE.

➢ CMSIS-CORE lets us access the SIM control registers using a C-language data structure with a useful name (SIM).
For example, to access the SIM_SCGC5 register, we simply write SIM->SCGC5.
Note that SIM is defined as a pointer to a data structure, which is why we use the “->” to select the control
register within.

➢ There are similar data structures for all the MCU’s peripherals and their control registers.

The file MKL25Z4.h defines the access layer for CMSIS-CORE and peripherals for KL25Z4-type MCUs.
We need to be sure that all our C source files contain the directive
#include <MKL25Z4.h>

before we try to use these features.

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CMSIS – Defining GPIO As a New Data Type
▪ Header file MKL25Z4.h defines C data structure types to represent hardware registers in MCU with
CMSIS-Core and peripherals hardware abstraction layer:

/** GPIO - Register Layout Typedef, six registers */

typedef struct {
__IO uint32_t PDOR; /* Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /* Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /* Port Clear Output Register, offset: 0x8 */ 0x400FF000 PDOR
__O uint32_t PTOR; /* Port Toggle Output Register, offset: 0xC */ 0x400FF004 PSOR
0x400FF008 PCOR
__I uint32_t PDIR; /* Port Data Input Register, offset: 0x10*/
0x400FF00C PTOR
__IO uint32_t PDDR; /* Port Data Direction Register,offset:0x14 */
0x400FF010 PDIR
} GPIO_Type; 0x400FF014 PDDR
GPIO structure for PTA
in memory map
Excerpt from the MKL25Z4.h header file.
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CMSIS – Defining a Pointer to The New Data Type
▪ Header file MKL25Z4.h declares pointers to the registers in the data structures:

/* GPIO - Peripheral instance base addresses */

/** Define peripheral PTA base address (value in reference manual) */

#define PTA_BASE (0x400FF000u)

/** Define peripheral PTA base pointer */

#define PTA ((GPIO_Type *)PTA_BASE) Pointer PTA → 0x400FF000 PDOR

0x400FF004 PSOR
0x400FF008 PCOR
▪ Accessing members in the data structure using the pointer to the structure:
0x400FF00C PTOR
PTA->PDDR = … 0x400FF010 PDIR
0x400FF014 PDDR
PTA->PDOR = …
GPIO structure for PTA
in memory map

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Coding Style for Accessing Bits
▪ Easy to make mistakes dealing with literal binary and hexadecimal values.
▪ For example, we need to set bits 15 and 19 in PORTA_PDIR for output.
We need to define a 32-bit literal n with bits 15 and 9 only set, you may use:
◦ n = 0000 0000 0000 0000 1000 0010 0000 0000 or
◦ n = 0x00008200
◦ n = 8704
▪ Easier to define n by any of the following three equivalent ways:
1. Make the literal value from shifted bit positions:
n = (1UL << 9) | (1UL << 15);

2. Define names for bit positions:

#define GREEN_LED_POS (9)
#define YELLOW_LED_POS (15)
n = (1UL << GREEN_LED_POS) | (1UL << YELLOW_LED_POS);
3. Create macro to do shifting to create mask:
#define MASK(x) (1UL << (x))
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n = MASK(GREEN_LED_POS) | MASK(YELLOW_LED_POS);
Using Masks

▪ Overwrite existing value in n with mask

n = MASK(foo);

▪ Set in n all the bits which are one in mask, leaving others unchanged
n |= MASK(foo);

▪ Complement the bit value of the mask

~MASK(foo);

▪ Clear in n all the bits which are zero in mask, leaving others unchanged
n &= ~MASK(foo);

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Accessing Fields in Control Registers Using Masks
How can we read and modify fields in control registers?

Example: SIM_SCGC5 register:

#define SIM_SCGC5_LPTMR_MASK 0x1u

#define SIM_SCGC5_TSI_MASK 0x20u
#define SIM_SCGC5_PORTA_MASK 0x200u
#define SIM_SCGC5_PORTB_MASK 0x400u
#define SIM_SCGC5_PORTC_MASK 0x800u
#define SIM_SCGC5_PORTD_MASK 0x1000u
#define SIM_SCGC5_PORTE_MASK 0x2000u

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Accessing Fields in Control Registers Using Masks (continued)
To find the current value of PORTE field:
n = (SIM->SCGC5 & SIM_SCGC5_PORTE_MASK) >> 13

To set fields PORTA and PORTE and clearing all other fields:
SIM->SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTE_MASK

To set fields PORTA and PORTE and keeping all other fields unchanged:
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTE_MASK

To clear field PORTA and keeping all other fields unchanged:

SIM->SCGC5 &= ~SIM_SCGC5_PORTA_MASK

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C Code
#define LED1_POS (1)
#define LED2_POS (2)
#define SW1_POS (5)
#define MASK(x) (1UL << (x))

PTA->PDDR |= MASK(LED1_POS) | MASK (LED2_POS); // set LED bits to outputs

PTA->PDDR &= ~MASK(SW1_POS); // clear Switch bit to input

PTA->PDOR = MASK(LED2_POS); // turn on LED1, turn off LED2

while (1) {
if (PTA->PDIR & MASK(SW1_POS)) {
// switch is not pressed, then light LED 2
PTA->PDOR = MASK(LED2_POS);
} else {
// switch is pressed, so light LED 1
PTA->PDOR = MASK(LED1_POS);
}
}

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Clocking Logic

Control register SIM_SCGC5 gates clocks to GPIO ports through bits 9-13.

To enable clock to Port A we need to set bit 9 in SIM_SCGC5 control register:

SIM->SCGC5 |= (1UL << 9);
Bit Port
13 PORTE
Header file MKL25Z4.h has definitions 12 PORTD
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
11 PORTC
10 PORTB
9 PORTA

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 Port Data

Connecting a GPIO Signal to a Pin

D Direction Q
Register
Freescale: is the pin
mux location in this
PDOR select diagram accurate?

PSOR select
Set
PCOR select
Rst Port Data
PTOR select Pin or
Tgl Output
Pad on
D Register Q package

I/O Clock
PDIR select
Port Data Pin Control
D Input Q Register
Register MUX field

▪ Multiplexer used to increase configurability - what should a pin be connected with internally?

▪ Each configurable pin has a Pin Control Register (PCR)

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CMSIS C Support for PCR

▪ MKL25Z4.h defines PORT_Type structure with a PCR field (array of 32 integers)

/** PORT - Register Layout Typedef */
typedef struct {
__IO uint32_t PCR[32]; /** PCR n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /** Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /** Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
__IO uint32_t ISFR; /** Interrupt Status Flag Register, offset: 0xA0 */
} PORT_Type;

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CMSIS C Support for PCR
▪ Header file defines pointers to PORT_Type registers
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)

▪ Also defines macros and constants

#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8
#define PORT_PCR_MUX(x)
(((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT)) &PORT_PCR_MUX_MASK)

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Resulting C Code for Clock Control and Mux

// Enable Clock to Port A

SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;

// Make 3 pins GPIO

PORTA->PCR[LED1_POS] &= ~PORT_PCR_MUX_MASK;
PORTA->PCR[LED1_POS] |= PORT_PCR_MUX(1);
PORTA->PCR[LED2_POS] &= ~PORT_PCR_MUX_MASK;
PORTA->PCR[LED2_POS] |= PORT_PCR_MUX(1);
PORTA->PCR[SW1_POS] &= ~PORT_PCR_MUX_MASK;
PORTA->PCR[SW1_POS] |= PORT_PCR_MUX(1);

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 INTERFACING
Hardware

41
Inputs: What’s a One? A Zero?

▪ Input signal’s value is determined by

voltage

▪ Input threshold voltages depend on

supply voltage VDD

▪ Exceeding VDD or GND may damage

chip

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Outputs: What’s a One? A Zero?

▪ Nominal output voltages

▪ 1: VDD − 0.5 V to VDD
▪ 0: 0 to 0.5 V

▪ Note: Output voltage depends on current Logic 1 out

drawn by load on pin
▪ Need to consider source-to-drain resistance in the

Vout
transistor
▪ Above values only specified when current < 5 mA
Logic 0 out
(18 mA for high-drive pads) and VDD > 2.7 V

Iout
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Output Example: Driving LEDs
▪ Need to limit current to a value which is safe for both LED
and MCU port driver
▪ Use current-limiting resistor
R = (VDD – VLED)/ILED
ILED = 4 mA

▪ VLED depends on type of LED (mainly color)

Red: ~1.8V
Blue: ~2.7 V

▪ Solve for R given VDD = ~3.0 V

▪ Red: 300 W
▪ Blue: 75 W

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Output Example: Driving a Speaker
▪ Create a square wave with a GPIO output

▪ Use capacitor to block DC value

▪ Use resistor to reduce volume if needed

▪ Write to port toggle output register (PTOR) to simplify code

void Beep(void) {
unsigned int period=20000;
while (1) {
PTC->PTOR = MASK(SPKR_POS);
Delay(period/2);
}
}

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Electrical Characteristic Consideration for Digital I/O Interfacing
Electrical compatibility:

1. Voltage-level compatibility:
The high output level of the driving circuit should be high enough to be considered as a high for the input of the
driven circuit.
The low output level of the driving circuit should be considered as a low for the input of driven circuit.

2. Current drive capability:

The output of the driving circuit should have enough current as required by the driven circuit.
The output of the driving circuit should be able to sink the currents of its load.

3. Signal timing:
Signal timing is also an important factor for making sure that the digital circuit functions correctly.
The main concern about timing is whether the signal from one chip becomes valid early enough to be used by
other chips. This is a timing compatibility issue.
When the operating frequency becomes very high, the transmission line effect and ground bounce effect will need to
be considered too.

46
 Additional Configuration in PCR

▪ Pull-up and pull-down resistors

▪ Used to ensure input signal voltage is pulled to
correct value when high-impedance
▪ Control bits in PCR:
‒ PE: Pull Enable. 1 enables the pull resistor
‒ PS: Pull Select. 1 pulls up, 0 pulls down.
▪ High current drive strength
▪ DSE: Set to 1 to drive more current e.g.,
8 mA vs. 5 mA @ > 2.7 V, or
6 mA vs. 1.5 mA @ <2.7 V
▪ Available on some pins - MCU dependent
47
Example
Read a switch on PTA1 and display it on the LED on PTB19:

1. CLOCK GATING
▪ Enable the clock to PORTA and PORTB.

2. CONFIGURE PTA1 and PTB19

▪ Configure PTA1 as GPIO (in MUX field) and enable the pull-up resistor (PE & PS fields) in PORTA_PCR1.
▪ Make PTA1 input in data direction register PDDRA.
▪ Configure PTB19 as GPIO (in MUX field) in PORTB_PCR19.
▪ Make PTB19 output in data direction register PORTB.

3. LOOP
▪ Read switch from PORTA.
▪ If PTA1 is high, set PTB19
else clear PTB19.
▪ Repeat.

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