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TPD4E001
SLLS682O – JULY 2006 – REVISED JULY 2019

TPD4E001 Low-Capacitance 4-Channel ESD-Protection for High-Speed Data Interfaces

1 Features 3 Description
1• IEC 61000-4-2 ESD Protection (Level 4) The TPD4E001 is a four-channel Transient Voltage
Suppressor (TVS) based Electrostatic Discharge
– ±8-kV Contact Discharge (ESD) protection diode array. The TPD4E001 is rated
– ±15-kV Air-Gap Discharge to dissipate ESD strikes at the maximum level
• 5.5-A Peak Pulse Current (8/20-µs Pulse) specified in the IEC 61000-4-2 international standard
(Level 4). This device has a 1.5-pF IO capacitance
• IO Capacitance: 1.5 pF (Typical)
per channel, making it ideal for use in high-speed
• Low Leakage Current: 1 nA (Maximum) data IO interfaces. The ultra low leakage current (< 1
• Low Supply Current: 1 nA nA maximum) is suitable for precision analog
• 0.9-V to 5.5-V Supply-Voltage Range measurements in applications like glucose meters
and heart rate monitors.
• Space-Saving DRL, DBV, DCK, DPK, and DRS
Package Options The TPD4E001 is available in DRL(SOT), DBV (SOT-
23), DCK (SC-70), DRS (QFN), and DPK (PUSON)
• Alternate 2, 3, 6-Channel options Available:
packages and is specified for –40°C to +85°C
TPD2E001, TPD3E001, TPD6E001 operation. See also the TPD4E1U06DCKR and
TPD4E1U06DBVR which are p2p compatible with the
2 Applications TPD4E001DCKR and TPD4E001DBVR. These
• USB 2.0 devices offer higher IEC protection, lower
capacitance, lower clamping voltage, and eliminate
• Ethernet
the input capacitor requirement.
• FireWire™ Serial Bus
• LVDS Device Information(1)
• SVGA Video Connections PART NUMBER PACKAGE BODY SIZE (NOM)

• Glucose Meters 1.60 mm × 1.20 mm

SOT (6)
2.90 mm × 1.60 mm
TPD4E001 SC70 (6) 2.00 mm × 1.25 mm
USON (6) 1.60 mm × 1.60 mm
SON (6) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Application Schematic
VBUS
0.1 µF D+
VCC
D–
RT GND

IO4 IO1

USB
Controller D1

IO3
IO2
VBUS

D+
GND
D–

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4E001
SLLS682O – JULY 2006 – REVISED JULY 2019 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes.......................................... 8
2 Applications ........................................................... 1 8 Application and Implementation .......................... 9
3 Description ............................................................. 1 8.1 Application Information.............................................. 9
4 Revision History..................................................... 2 8.2 Typical Application ................................................... 9
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 11
6 Specifications......................................................... 5 10 Layout................................................................... 11
6.1 Absolute Maximum Ratings ..................................... 5 10.1 Layout Guidelines ................................................. 11
6.2 ESD Ratings—JEDEC Specification......................... 5 10.2 Layout Example .................................................... 11
6.3 ESD Ratings—IEC Specification .............................. 5 11 Device and Documentation Support ................. 12
6.4 Recommended Operating Conditions....................... 5 11.1 Documentation Support ........................................ 12
6.5 Thermal Information .................................................. 6 11.2 Related Links ........................................................ 12
6.6 Electrical Characteristics........................................... 6 11.3 Receiving Notification of Documentation Updates 12
6.7 Typical Characteristics .............................................. 7 11.4 Community Resources.......................................... 12
7 Detailed Description .............................................. 8 11.5 Trademarks ........................................................... 12
7.1 Overview ................................................................... 8 11.6 Electrostatic Discharge Caution ............................ 12
7.2 Functional Block Diagram ......................................... 8 11.7 Glossary ................................................................ 12
7.3 Feature Description................................................... 8 12 Mechanical, Packaging, and Orderable
Information ........................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (March 2018) to Revision O Page

• Added TPD4E001R DBV Package image and updated Pin Funtions table........................................................................... 4

Changes from Revision M (May 2017) to Revision N Page

• TPD4E001DBVR Device Marking changed from NFY to NFYF ......................................................................................... 12

Changes from Revision L (May 2016) to Revision M Page

• Updated Pin Functions table and DCK2 Package image....................................................................................................... 4

• Updated 'Surge Protection" to "IEC Specification" in ESD Ratings—IEC Specification table................................................ 5

Changes from Revision K (January 2015) to Revision L Page

• Added frequency test condition to Channel input capacitance in the Electrical Characteristics table ................................... 6
• Added Community Resources ............................................................................................................................................. 12

Changes from Revision J (December 2013) to Revision K Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision I (September 2012) to Revision J Page

• Updated Description. .............................................................................................................................................................. 1

• Removed Ordering Information table. .................................................................................................................................... 4

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Changes from Revision H (August 2012) to Revision I Page

• Added DCK2 package to Pin Out drawings. .......................................................................................................................... 4

• Updated Electrical Characteristics table................................................................................................................................. 6

Changes from Revision G (December 2011) to Revision H Page

• Updated TOP-SIDE MARKING column in ORDERING INFORMATION table. ..................................................................... 4

Changes from Revision F (May 2011) to Revision G Page

• Updated document formatting. ............................................................................................................................................... 1

• Added DPK (PUSON) package and package information. .................................................................................................... 4

Changes from Revision E (April 2011) to Revision F Page

• Added Peak Pulse Waveform Graph to Typical Operating Characteristics. .......................................................................... 7

Changes from Revision C (April 2007) to Revision D Page

• Added DBV (SOT-23) package and package information...................................................................................................... 4

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5 Pin Configuration and Functions

DRL Package
6-Pin SOT DRS Package
Top View 6-Pin SON
Top View
IO1 1 6 VCC

IO2 2 5 IO4 IO1 1 6 VCC

GND 3 4 IO3
IO2 2 5 IO4

GND
GND 3 4 IO3
DCK2 Package
6-Pin SC70
Top View

IO1 1 6 VCC DPK Package

6-Pin USON
IO2 2 5 IO4 Top View

GND 3 4 IO3
IO1 1 6 VCC

IO2 2 5 IO4
DBV or DCK Package
6-Pin SOT or SC70 GND 3 4 IO3
Top View

IO1 1 6 IO4

GND 2 5 VCC
TPD4E001R DBV Package
6-Pin SOT
IO2 3 4 IO3
Top View

IO1 1 6 IO3

VCC 2 5 GND

IO2 3 4 IO4

Pin Functions
PIN
I/O DESCRIPTION
NAME DRS, DRL, DPK DBV, DCK TPD4E001R
GND 3 2 5 — Ground
1 1 1
2 3 3
IOx I ESD-protected channel
4 4 4
5 6 6
Power-supply input. Bypass VCC to GND with a 0.1-μF
VCC 6 5 2 I
ceramic capacitor
Exposed thermal
— Exposed thermal pad. Connect to GND or leave floating
pad (DRS package only)

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC –0.3 7 V
VI/O IO voltage tolerance –0.3 VCC + 0.3 V
I(Surge) IEC 61000-4-5 peak pulse current (TP = 8/20 µs), IOx pins 5.5 A
P(Surge) IEC 61000-4-5 peak pulse power (TP = 8/20 µs), IOx pins 100 W
TJ Junction temperature 150 °C
Infrared (15 s) 220
Bump temperature (soldering) °C
Vapor phase (60 s) 215
Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC Specification

VALUE UNIT
TPD4E001 in DRS, DRL, and DPK Packages
Human-body model (HBM), per All pins except 1, 2, 4, and ±2000
ANSI/ESDA/JEDEC JS-001 (1) 5
V(ESD) Electrostatic discharge Pins 1, 2, 4, and 5 ±15000 V
Charged-device model (CDM), per JEDEC All pins ±1000
specification JESD22-C101 (2)
TPD4E001 in DBV and DCK Packages
All pins except 1, 3, 4, and ±2000
Human-body model (HBM), per 6
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD) Electrostatic discharge Pins 1, 3, 4, and 6 ±15000 V
Charged-device model (CDM), per JEDEC All pins ±1000
specification JESD22-C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
TPD4E001 in DRS, DRL, and DPK Packages
IEC 61000-4-2 contact discharge All pins ±8000
V(ESD) Electrostatic discharge V
IEC 61000-4-2 air-gap discharge All pins ±15000
TPD4E001 in DBV and DCK Packages
IEC 61000-4-2 contact discharge All pins ±8000
V(ESD) Electrostatic discharge V
IEC 61000-4-2 air-gap discharge All pins ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
TA Operating free-air temperature –40 85 °C
VCC pin 0.9 5.5
Operating voltage V
IO1, IO2 pins 0 VCC

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6.5 Thermal Information

TPD4E001
(1) DRL DBV DCK DPK DRS (SON)
THERMAL METRIC UNIT
(SOT) (SOT) (SC70) (USON)
6 PINS 6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 226.4 259.7 251.1 247.6 91.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 90.3 186.5 88.1 124.8 106.9 °C/W
RθJB Junction-to-board thermal resistance 61.2 107.6 54.8 204.2 64.8 °C/W
ψJT Junction-to-top characterization parameter 6.7 71.4 1.7 19.2 10.2 °C/W
ψJB Junction-to-board characterization parameter 61 107.1 54.1 209.3 64.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 29.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), VCC = 5 V ± 10%
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VCC Supply voltage 0.9 5.5 V
ICC Supply current 1 100 nA
VF Diode forward voltage IF = 10 mA 0.65 0.95 V
VBR Breakdown Voltage IBR = 10 mA 11 V
TA = 25°C, ±15-kV HBM, Positive transients VCC + 25
IF = 10 A Negative transients –25
TA = 25°C, Positive transients VCC + 60
±8-kV contact discharge
(IEC 61000-4-2), IF = 24 A Negative transients –60
VC Channel clamp voltage V
TA = 25°C, Positive transients VCC + 100
±15-kV air-gap discharge
(IEC 61000-4-2), IF = 45 A Negative transients –100
Surge strike on IO pin,
GND pin grounded, Positive transients 17
IPP = 5 A, 8/20 µs (2)
VRWM Reverse stand-off voltage IO pin to GND pin 5.5 V
II/O Channel leakage current Vi/o = GND to VCC ±1 nA
CI/O Channel input capacitance VCC = 5 V, bias of VCC/2; ƒ = 10 MHz 1.5 pF

(1) Typical values are at VCC = 5 V and TA = 25°C.

(2) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to ICE61000-4-5.

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6.7 Typical Characteristics

2.20 1000

2.00

IO Leakage Current (pA)

IO Capacitance (pF)

1.80 100

1.60

1.40 10

1.20

1.00 1
0.00 1.00 2.00 2.50 3.00 4.00 5.00 –40 25 45 65 85

IO Voltage (V) Temperature (°C)

Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V) Figure 2. IO Leakage Current vs Temperature (VCC = 5.5 V)

6.0 100
5.5 90
5.0 80
4.5
70
4.0
Current (A)
60

PPK (W)
3.5
IPK (A)

3.0 50
2.5 40
2.0 30
Power (W)
1.5
20
1.0
0.5 10
0.0 0
0 5 10 15 20 25 30 35 40 45 50
Time (μs)
Figure 3. Peak Pulse Waveform, VCC = 5.5 V

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7 Detailed Description

7.1 Overview
The TPD4E001 is a four-channel transient voltage suppressor (TVS) based ESD protection diode array. The
TPD4E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international
standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed
data IO interfaces. The ultra-low leakage current (<1 nA maximum) is suitable for precision analog
measurements in applications like glucose meters and heart rate monitors.

7.2 Functional Block Diagram

VCC

IO1 IO2 IO3 IO4

GND

7.3 Feature Description

The TPD4E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a
central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD
clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD
strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD4E001's
low loading capacitance makes it ideal for protection high-speed signal terminals.

7.4 Device Functional Modes

The TPD4E001 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower
diodes Vforward (–0.6 V) are present upon the circuit being protected. During ESD events, voltages as high as ±15
kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines
fall below the trigger voltage of the TPD4E001 (usually within 10s of nano-seconds) the device reverts back to a
high-impedance state.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD4E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a
path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a
system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode.
This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP,
to a tolerable level to the protected IC.

8.2 Typical Application

VBUS
0.1 µF D+
VCC
D–
RT GND

IO4 IO1

USB
Controller D1

IO3
IO2
VBUS

D+
GND
D–

GND

Figure 4. Typical Application Schematic

8.2.1 Design Requirements

For this design example, a single TPD4E001 is used to protect all the pins of two USB2.0 connectors.
Given the USB application, the following parameters in Table 1 are known.

Table 1. Design Parameters

DESIGN PARAMETER VALUE
Signal range on IO1, IO2, IO3, and IO4 0 V to 3.6 V
Signal voltage range on VCC 0 V to 5.25 V
Operating Frequency 240 MHz

8.2.2 Detailed Design Procedure

When placed near the USB connectors, the TPD4E001 ESD solution offers little or no signal distortion during
normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures
that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For
proper operation, the following layout/ design guidelines must be followed:
1. Place the TPD4E001 solution close to the connectors. This allows the TPD4E001 to take away the energy
associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.

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3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001
consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to
30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy
associated with the ESD strike.
4. Leave the unused IO pins floating. In this example of protecting two USB ports, none of the IO pins are left
unused.
5. The VCC pin can be connected in two different ways:
a. If the VCC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor
for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD
bypass.
b. If the VCC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal
swing in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the VCC pin for
ESD bypass.

8.2.3 Application Curve

Figure 5 is a capture of the voltage clamping waveform of TPD4E001DRL on IO3 during an 8-kV Contact
IEC61000-4-2 ESD strike.

Figure 5. TPD4E001DRL IEC61000-4-2 Voltage Clamp Waveform 8-kV Contact

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9 Power Supply Recommendations

This device is a passive ESD protection device so there is no need to power it. Take care to make sure that the
maximum voltage specifications for each pin are not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

The following is a layout example for protecting two interface ports with the TPD4E001. One example is two USB
2.0 ports, as was discussed in the Application and Implementation section. For the USB 2.0 example, IO1 and
IO2 is D+ and D–, respectively, of USB port 1. IO3 and IO4 is D– and D+, respectively, of USB port 2.

GND

0.1µF

IO1 VCC

IO2 IO4

GND IO3

= VIA to GND

Figure 6. Routing With DRL Package

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPD4E001 Click here Click here Click here Click here Click here
TPD4E1U06 Click here Click here Click here Click here Click here

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
E2E is a trademark of Texas Instruments.
FireWire is a trademark of Apple Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPD4E001DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (NFY5, NFYF) Samples
(NFYP, NFYS)
TPD4E001DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (2CF, 2CR) Samples
(2CP, 2CP)
2CH
TPD4E001DPKR ACTIVE USON DPK 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 Samples

TPD4E001DPKT ACTIVE USON DPK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 Samples

TPD4E001DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) Samples
(2CG, 2CH)
TPD4E001DRLRG4 ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) Samples
(2CG, 2CH)
TPD4E001DRSR ACTIVE SON DRS 6 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM Samples

TPD4E001RDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 NRYF Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF TPD4E001 :

• Automotive : TPD4E001-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4E001DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPD4E001DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
TPD4E001DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TPD4E001DPKR USON DPK 6 5000 180.0 9.5 1.75 1.75 0.7 4.0 8.0 Q2
TPD4E001DPKT USON DPK 6 250 180.0 9.5 1.75 1.75 0.7 4.0 8.0 Q2
TPD4E001DRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
TPD4E001DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
TPD4E001DRSR SON DRS 6 1000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPD4E001RDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPD4E001DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
TPD4E001DCKR SC70 DCK 6 3000 183.0 183.0 20.0
TPD4E001DCKR SC70 DCK 6 3000 180.0 180.0 18.0
TPD4E001DPKR USON DPK 6 5000 184.0 184.0 19.0
TPD4E001DPKT USON DPK 6 250 184.0 184.0 19.0
TPD4E001DRLR SOT-5X3 DRL 6 4000 183.0 183.0 20.0
TPD4E001DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
TPD4E001DRSR SON DRS 6 1000 356.0 356.0 35.0
TPD4E001RDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
6

4X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM

SYMM

0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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