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    Lecture 9 - CMOS Delay I

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    Wambi Danielcollins
    This document discusses CMOS delay in VLSI system design. It defines propagation delay and contamination delay as the time it takes for an output to change after an input changes. It then explains how to calculate propagation delay based on parasitic capacitances. The document discusses CMOS inverter logic and propagation delay, showing how an inverter's high-to-low and low-to-high delays are calculated based on transistor resistance and output capacitance. It introduces a RC delay model for estimating propagation delay and shows an example of calculating delay for a 3-input NAND gate.

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    Lecture 9 - CMOS Delay I

    Uploaded by

    Wambi Danielcollins
    92 views28 pages
    This document discusses CMOS delay in VLSI system design. It defines propagation delay and contamination delay as the time it takes for an output to change after an input changes. It then explains how to calculate propagation delay based on parasitic capacitances. The document discusses CMOS inverter logic and propagation delay, showing how an inverter's high-to-low and low-to-high delays are calculated based on transistor resistance and output capacitance. It introduces a RC delay model for estimating propagation delay and shows an example of calculating delay for a 3-input NAND gate.

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    This document discusses CMOS delay in VLSI system design. It defines propagation delay and contamination delay as the time it takes for an output to change after an input changes. It then explains how to calculate propagation delay based on parasitic capacitances. The document discusses CMOS inverter logic and propagation delay, showing how an inverter's high-to-low and low-to-high delays are calculated based on transistor resistance and output capacitance. It introduces a RC delay model for estimating propagation delay and shows an example of calculating delay for a 3-input NAND gate.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    92 views28 pages

    Lecture 9 - CMOS Delay I

    Uploaded by

    Wambi Danielcollins
    This document discusses CMOS delay in VLSI system design. It defines propagation delay and contamination delay as the time it takes for an output to change after an input changes. It then explains how to calculate propagation delay based on parasitic capacitances. The document discusses CMOS inverter logic and propagation delay, showing how an inverter's high-to-low and low-to-high delays are calculated based on transistor resistance and output capacitance. It introduces a RC delay model for estimating propagation delay and shows an example of calculating delay for a 3-input NAND gate.

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    VLSI SYSTEM DESIGN

    CMOS DELAY I
    Video Link from UCSD:
    https://www.youtube.com/watch?v=EOY_CwqMgoI
    Definitions

    When the input changes, the output retains its old value
    for at least the contamination delay and takes on the
    new value in at most the propagation delay.
    Definitions (cont’d)
    ➢tpdr: rising propagation delay
    ➢From input to rising output crossing VDD/2
    ➢tpdf: falling propagation delay
    ➢From input to falling output crossing VDD/2
    ➢tpd: average propagation delay
    ➢ -- maximum time from input crossing 50%
    to output crossing 50% = (tpdr +tpdf)/2
    ➢tcdr: rising contamination delay
    ➢From input to rising output crossing VDD/2
    ➢tcdf: falling contamination delay
    ➢From input to falling output crossing VDD/2
    Propagation Delay and Rise/fall times
    How to calculate delay?
    • Delay depends on the numerous parasitic
    capacitances between terminals – need to be simplified
    • Not very useful for designers in evaluating different
    options and optimizing different parameters
    2.0

    1.5

    1.0
    (V)
    tpdf = 66ps tpdr = 83ps
    Vin
    Vout
    0.5

    0.0

    0.0 200p 400p 600p 800p 1n


    t(s)
    CMOS Inverter Logic
    CMOS Inverter Logic (cont’d)
    CMOS Inverter Propagation Delay
    Inverter Propagation Delay High-to-Low

    During early phases of discharge, NMOS is saturated and


    PMOS is cut-off. Time to discharge half of charge stored in CL:.
    Inverter Propagation Delay Low-to-High

    During early phases of discharge, PMOS is saturated and


    NMOS is cut-off. Time to charge half of charge stored in CL:.
    Transistor Resistance

    In the linear region

    • Not accurate, but at least shows that the resistance is


    proportional to L/W and decreases with increasingVgs
    • If R, C are for a unit size transistor then a transistor of
    K width has KC capacitance and R/K resistance

    • The resistance of a PMOS transistor ≈ 2× resistance


    of NMOS transistor of the same size
    Transistor Capacitances: Fan-out of 1
    Inverter

    Driver: gate that charges or discharges a node


    Load: gates and wire being driven
    Inverter Diffusion/Gate Capacitances
    Include gate capacitance of load and diffusion
    capacitances of the driver’s transistors

    Gate capacitance of X1 and diffusion


    capacitances of X2 don’t matter. Why?
    Lumping Capacitances in FO1 Inverter

    What is the output capacitor voltage analysis?


    FO1 Inverter Voltage response to Step Input
    • Before step, A=0; N1 off & P1 on; B=VDD
    • After step, A=1; N1 turns on and B drops to 0.
    • Rate of change of VB depends on Cout & current

    • Current depends on whether N1 is in the linear or


    saturation region.
    FO1 Inverter Voltage (cont’d)
    • Gate is at VDD, source at 0 and drain at VB
    • Therefore, Vgs = VDD, Vds = VB
    • Initially, Vds = VDD > Vgs – Vt, so N1 → saturation
    • As VB falls, N1 enters linear region.
    RC Delay Model
    • Transistor treated as a switch in series with a resistor.
    • Effective resistance is ratio Vds to Ids
    • Equivalent circuits for MOS transistors used
    • Unit nMOS has resistance R, capacitance C
    • Unit pMOS has resistance 2R, capacitance C
    • Capacitance proportional to width
    • Resistance inversely proportional to width
    • nMOS transistor of width k has resistance R/k. Why?
    Transistor Equivalent Circuits
    Inverter RC Delay Estimate

    tpd = 6RC
    Example 1: 3-input NAND gate
    • Sketch a 3-input NAND with transistor widths chosen
    to achieve effective rise and fall resistances equal to a
    unit inverter (R). Annotate the gate with its gate and
    diffusion capacitances. Sketch equivalent circuits for
    the falling output transition and worst case rising
    output transition.
    Solution: Determine widths
    Determine Capacitances
    Lump Capacitances
    Equivalent Rise/Fall Circuits

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