Chapter 16

MOSFET Digital Circuits

In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology of choice. Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.

Chapter 16.1

NMOS Inverter

NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

MOSFET Digital Circuits

n-channel MOSFET

n-channel MOSFET

Chap.3

n-Channel MOSFET Formulas

Transition points

NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

Saturation region

Nonsaturation region

NMOS Inverter
If VI <VTN , the transistor is in cutoff and iD = 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS If VI >VTN , the transistor is on and initially is biased in saturation region, since VDS < VGS -VTN . VI <VNT VI >VNT
Transistor on Transistor off

NMOS Inverter with Resister Load

+

+
=VDD=VDS VGS= +

=VDD=VDS

Cut-off
If VI <VTN , the transistor is in cutoff and iD = 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS

VGS=

As the input voltage increases (VGS ), the drain to source voltage (VDS) decreases and the transistor inter into the nonsaturation region.

NMOS Inverter with Resister Load

Saturation region
+

NMOS Inverter with Resister Load

Saturation region
+

=VDS VGS= + VGS= +

=VDS

Saturation Region
As the input is increased slightly above the VTN , the transistor turns on and is in the saturation region.

Transition Region
As the input voltage is further increases and voltage drop across the RD become sufficient to reduce the VDS such that V V V
DS GS TN

The Q-point of the transistor moves up the load line.

At the transition point,

NMOS Inverter with Resister Load

Nonsaturation region
+

NMOS Inverter with Resister Load

Input-Output Relationship
VGS=

Saturation region

=VDS

=VDS VGS= +

Nonsaturation Region
As the input voltage becomes greater than VIt , the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region.
VGS= vI VDS= vO

The sharpness of the transition region increases with increasing load resistance.

The minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance.

Summary of NMOS inverter with Resister Load

Current-Voltage Relationship Saturation Region

Example
For the NMOS inverter shown in Fig. VDD = 3V. Assume transistor parameters of Kn = 60 A/v2, W/L = 5, and VTN = 0.5 V. (a) Find the value of RD such that vo = 0.1 V when vI = 3 V. (b) Using the results of part (a) determine the transition point for the driver transistor

Transition Region

Nonsaturation Region

n-Channel MOSFET connected as saturated load device

An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter. Since the gate and drain of the transistor are connected, we have VGS=VDS When VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied. VDS>(VGS-VTN) VDS (sat)= (VDS-VTN) because VGS=VDS or VDS (sat)= (VGS-VTN) In the saturation region the drain current is iD=Kn(VGS-VTN)2 = Kn(VDS-VTN)2

The iD versus vDS characteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.

NMOS Inverter with Enhancement Load

This basic inverter consist of two enhancement-only NMOS transistors Much more practical than the resister loaded inverter, because the resistors are thousand of times larger size than a MOSFET.

NMOS Inverter with Enhancement Load

An n-channel enhancement-mode MOSFET with gate connected to the drain can be used as a load device.
Device acts as a Nonlinear resistor !!!

Nonlinear resistor !!!

NMOS Inverter with Enhancement Load

When vI < VTND

NMOS Inverter with Enhancement Load

When vI > VTND
Just greater than

NMOS Inverter with Enhancement Load

NMOS Inverter with Enhancement Load

When vI > VIt

NMOS Inverter with Enhancement Load

c.f.

NMOS Inverter with Resister Load

Input-Output Relationship
VGS=

=VDS

The sharpness of the transition region increases with increasing load resistance.

The minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance.

NMOS Inverter with Enhancement Load

P1014

Example

Limitation of Enhancement Load inverter

Example 16.3
Limitation of Enhancement Load inverter

P1014

Example
The enhancement-load NMOS inverter shown in Fig. is biased at VDD = 3 V. The transistor parameters are VTND = VTNL = 0.4 V, kn = 60 mA/V2, (W/L)D = 16 and (W/L)L = 2. (a) Find vo when (i) vI = 0, (ii) vI = 2.6, (b) Calculate the power dissipated in the inverter when vI = 2.6 V.

NMOS Inverter with Depletion Load

Depletion mode : Channel exists even with zero gate voltage.
A negative voltage must be applied to the gate to turn the device off. Threshold voltage is always negative.

N-Channel Depletion-Mode MOSFET

In n- channel depletion mode MOSFET, an nchannel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode. A negative voltage must be applied to the gate to turn the device off. The threshold voltage is always

This is an alternate form of the NMOS inverter that uses an depletion-mode MOSFET load device with gate and source terminal connected. This inverter has the advantage of VO= VDD , as well as more abrupt transition region even though the W/L ratio for the output MOSFET is small.

negative for this

kind of device.

NMOS Inverter with Depletion Load

Gate and source are connected, Since the threshold voltage of load transistor is negative.

NMOS Inverter with Depletion Load

Load

NMOS Inverter with Depletion Load (cont.)

Case I: when VI<VTND (drive is cutoff): No drain current conduct in either transistor. That means the load transistor must be in the linear region of the operation and the output current can be expressed as fellows iDL(linear)=KL[2(VGSL - VTNL)VDSL VDSL2] Since VGSL=0, and iDL=0 0=-KL[2VTNLVDSL + VDSL2] Which gives VDSL=0 thus VO= VDD This is the advantage of the depletion load inverter over the enhancement load inverter.

NMOS Inverter with Depletion Load

When vI > VTND
Just greater than

NMOS Inverter with Depletion Load

NMOS Inverter with Depletion Load

This implies that input and output voltages are not linear in this region.

This implies that input voltage is constant as the Q-point passes this region.

NMOS Inverter with Depletion Load

NMOS Inverter with Depletion Load

Q2

(Nonsaturation)

Q1

More abrupt transition region can be achieved even though the W/L ratio for the output MOSFET is small.

Example 16.4

P1014

Example 16.4

P1014

See slide 34

See next slide

vGS=0

Example 16.4

P1014

Summary of NMOS inverter with Resister Load

Current-Voltage Relationship Saturation Region

Transition Region

Nonsaturation Region
See next slide

vGS=0

Example 16.4

P1014

Design 16.5

P1018

Design 16.5

P1018

Design 16.5

P1018

short

Load transistor is in Saturation mode

Example 16.14

P1098

(i) (ii)

Example 16.14

P1098

Example 16.14

P1098

(i) (ii)

(i) (ii)

Example 16.14

P1098

NMOS Inverter

Chapter 16

Chapter 16.2

NMOS Logic Circuit

1160W
Resister Load

825W
Enhancement Load

200W
Depletion Load

NMOS Logic Circuit

In 0 1 In 0 1 In 0 1 In

Logic Gates

NMOS logic circuits are constructed by connecting driver transistor in parallel, series or series-parallel combinations to produce required output logic function

Out

AND Gate

Out

OR Gate

Out

XOR Gate

Out

NOT Gate

Logic Gates

NMOS NOR Gate

NMOS NOR gate can be constructed by connecting an additional driver transistor in parallel with a depletion load inverter.

NMOS NOR Gate

NMOS NOR Gate

When all Inputs are at logic 1
When A = B = logic 1 Both driver transistors are switched into nonsaturation region and load transistor is biased in saturation region.

Suppose two driver transistors are identical,

higher the aspect ratio lower the output.

Example 16.7

p1030

NMOS NAND Gate

Additional driver transistor connected in Series

NMOS Logic Circuit

Concept of Effective Width-to-Length Ratios Parallel combination Series combination

Design 16.20

p1099

For the NOR gate the effective width of the drivers transistors doubles. The effective aspect ratio is increased.

For the NAND gate the effective length of the driver transistors doubles. The effective aspect ratio is decreased.

Design 16.20

p1099

(b)

(a) (c)

Fan-In and Fan-Out

The Fan-in of a gate is the number of its inputs. Thus a four input NOR gate has a fan-in of 4. Similarly, Fan-Out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications.

Transient Analysis of NMOS Inverters

The source of capacitance CT2 and CT3 are the transistor input capacitances and parasitic capacitances due to interconnect lines between the inverter stages. The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter configurations.

The rate at

Transient Analysis of NMOS Inverters

Chapter 16

The raise time is longer because the load capacitor is charged by the current through the smaller load transistor.
(W/L)L= 1 (W/L)D= 4 0.5pF

The fall time relatively short, because the load capacitor discharges through the large driver transistor.

Chapter 16.3

CMOS Inverter

p-Channel MOSFET
p

p-Channel MOSFET
In p-channel enhancement device. A negative gate-to-source voltage must be applied to create the inversion layer, or channel region, of holes that, connect the source and drain regions.
p n

The threshold voltage VTP for p-channel enhancement-mode device is always negative and positive for depletion-mode PMOS.

Cross-section of p-channel enhancement mode MOSFET

CMOS

Complementary MOS
The most abundant devices on earth
Although the processing is more complicated for CMOS circuits than for NMOS circuits, CMOS has replaced NMOS at all level of integration, in both analog and

digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits.

CMOS Properties
Full rail-to-rail swing high noise margins

CMOS Inverter
In the fabrication process, a separate p-well region is formed within the starting n-substrate. The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n-substrate.

Logic levels not dependent upon the relative device sizes transistors can be minimum size ratio less

Always a path to VDD or GND in steady state low output impedance (output resistance in k range) large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors

CMOS Inverter Steady State Response

VDD VDD

Rp

PMOS

PMOS

VOL = 0 VOH = V DD

VOut = VDD
NMOS

VOut = 0 Rn
NMOS

VIn = 0

VIn = V DD

Voltage Transfer Curve

HW solution

16.4

CMOS Inverter Load Lines

2.5 2
Vin = 0.5V
X10
-4

PMOS

NMOS
Vin = 2.5V

Vin = 0V

I (A) DN IDP (A)

1.5 1
Vin = 1.0V

Vin = 2.0V
NMOS off PMOS in non sat

NMOS in sat PMOS in non sat

Vin = 1.5V Vin=1.0V

NMOS in sat PMOS in sat

0.5 Vin = 1.5V Vin=1.5V

Vin = 2.0V

Vin = 1.0V Vin = 0.5V

Vin=0.5V
NMOS in non sat PMOS in sat NMOS in nonsat PMOS off

0
Vin=2.5V

0
Vin=2.0V

0.5

1.5

2.5

Vin=0V

Vout (V)

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

from below graph or

vSDP is small

vOPt

vI and vO relationship as long as NMOS: saturation, PMOS: nonsaturation

B
vONt vIt

from above graph

Example 16.9

p1041

vIt vOPt vONt

NMOS: off PMOS: nonsaturation NMOS: saturation PMOS: nonsaturation

For VDD=5V

NMOS: saturation PMOS: saturation

NMOS: nonsaturation PMOS: saturation NMOS: nonsaturation PMOS: off

Example 16.9

p1041

vOPt VDD=10V vONt vOPt VDD=5V vONt vIt vIt

CMOS inverter: series combination of PMOS and NMOS To form the input, gates of the two MOSFET are connected. To form the output, the drains are connected together.
The transistor KN is also known as pull down device because it is pulling the output voltage down towards ground. The transistor KP is known as the pull up device because it is pulling the output voltage up towards VDD. This property speed up the operation considerably.

CMOS Inverter in either High or Low State

(ideal case)

VIn
1 0

VOut
0 1
Ideally, the power dissipation of the CMOS inverter is zero. Practical device CMOS inverter ( nW) NMOS inverter (mW)

The static power dissipation during both extreme cases (logic 1 or 0) is almost zero because iDP= iDN= 0.

CMOS Inverter Design Consideration

The CMOS inverter usually design to have, (1)

VTN = VTP
' W ' W kN = kP L L
' ' But k N > k P (because N>P)

(2)

How equation (2) can be satisfied ?

This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical transition, results in wide noise margin.

Symmetrical Properties of the CMOS Inverter

NMOS: off PMOS: nonsaturation NMOS: saturation PMOS: nonsaturation

vOPt

NMOS: saturation PMOS: saturation

vONt
NMOS: nonsaturation PMOS: saturation NMOS: nonsaturation PMOS: off

V It =

V DD 2

p1101

(a) vIt vOPt vONt

(i)

KN

k' W = n 2 L
Transition points

VOPt VONt

(ii)

Example 16.29

p1101

CMOS Inverter VTC

Increase W of PMOS kP increases VIt moves to right Increase W of NMOS kN increases VIt moves to left
kp=kn kp=5kn

(b)

KP =

' kP 2

W L

(i)

VDD

Transition points

kp=0.2kn
VOPt VONt

VOut

for V It =
VDD

(ii)
VIt

V DD 2 kN = kP , WN WP

VIn

CMOS Inverter VTC

Effects of VIt adjustment

Problem 16.31

p1101

Result from changing kP/kN ratio:

Inverter threshold VIt VDD/2 Rise and fall delays unequal Noise margins not equal

(a)

Reasons for changing inverter threshold:

Want a faster delay for one type of transition (rise/fall) Remove noise from input signal: increase one noise margin at expense of the other

Problem 16.31

p1101

Example 16.31

p1101

(b)

vIt

CMOS inverter currents

When the output of a CMOS inverter is either at a logic 1 or 0, the current in the circuit is zero. When the input voltage is in the range transistors are conducting and a current exists in the inverter. both

CMOS inverter currents

When NMOS transistor is biased in the saturation region
The current in the inverter is controlled by vGSN and the PMOS vSDP adjusts such that iDP = iDN .

As long as NMOS transistor is biased in the saturation region the square root of the inverter current is linear function of the input voltage.

CMOS inverter currents

When PMOS transistor is biased in the saturation region
The current in the inverter is controlled by vSGP and the NMOS vDSN adjusts such that iDP = iDN .

CMOS inverter currents

As long as PMOS transistor is biased in the saturation region the square root of the inverter current is linear function of the input voltage.

NMOS: off PMOS: nonsaturation NMOS: saturation PMOS: nonsaturation

NMOS: saturation PMOS: saturation NMOS: nonsaturation PMOS: saturation NMOS: nonsaturation PMOS: off

Problem 16.33

p1102

Power Dissipation
There is no power dissipation in the CMOS inverter when the output is either at logic 0 or 1. However, during switching of the CMOS inverter from low logic 0 to logic 1, current flows and power is dissipated. Usually CMOS inverter and logic circuit are used to drive other MOS devices by connecting a capacitor across the output of a CMOS inverter. This capacitor must be charged and discharged during the switching cycle.

(a)

(b)

NMOS Transistor Capacitances

NMOS Transistor Capacitances

Triode Region

Saturation Region

Cox = Gate-Channel capacitance per unit area(F/m2) CGC = Total gate channel capacitance CGS = Gate-Source capacitance CGD = Gate-Drain capacitance CGSO and CGDO = overlap capacitances (F/m)
Drain is no longer connected to channel.

NMOS Transistor Capacitances

CMOS Inverter

Cutoff Region

Switch Model of Dynamic Behavior

VDD VDD

Rp CL Vout Rn Vout CL

Conducting channel region is completely gone. CGB = Gate-Bulk capacitance CGBO = Gate-Bulk capacitance per unit width.

VIn = 0

VIn = VDD

Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)

CMOS Inverter Power

Power has three components

CMOS Inverter Power

Static Power Consumption
Static current: in CMOS there is no static current as long as VIn < VTN or VIn > VDD+VTP Leakage current: determined by off transistor Influenced by transistor width, supply voltage, transistor threshold voltages
VDD VDD

Static power: when input isnt switching Dynamic capacitive power: due to charging
and discharging of load capacitance

Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on

Ileak,P
VI<VTN VDD VDD Vo(low)

Ileak,N

CMOS Inverter Power

Dynamic Capacitive Power and Energy stored in the PMOS
Case I: When the input is at logic 0 PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device. Power dissipation in the PMOS transistor; PP=iLVSDp= iL(VDD-VO) The current and output voltages are related by, iL=CLdvO/dt Similarly the energy dissipation in the PMOS device can be written as the output switches from Vlow to V d EP = high, PP = C L (V DD O ) O dt , E P = C LV DD d O C L O d O
DD DD

CMOS Inverter Power

Dynamic Capacitive Power and Energy stored in the PMOS
Case II: when the input is high and out put is low: During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter;
EN = 1 2 C LV DD 2

The total energy dissipated during one switching 1 1 2 2 2 E cycle; T = E P + E N = 2 C LV DD + 2 C LV DD = C LV DD The E = Pdissipated ETterms frequency; fC V 2 power t P = in P = fE T T L DD

dt

E P = C LV DD O EP =

V DD 0

CL

O
2

2 V DD

, E P = (C LV DDV DD
0

V 0) (C L DD 0 ) 2

1 2 C LV DD the energy stored in the capacitor CL when the output is high. 2

This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2

CMOS Inverter Power

Dynamic Capacitive Power
2 Pdyn = C LVDD f
Formula for dynamic power

CMOS Inverter Power

Dynamic Short-Circuit Power
Short-circuit current flows from VDD to GND when both transistors are on saturation mode.
VDD

Does not (directly) depend on device sizes Does not depend on switching delay Applies to general CMOS gate in which:
Switched capacitances are lumped into CL Output swings from GND to VDD Input signal approximated as step function Gate switches with frequency f

Imax Vout

Imax: depends on saturation current of devices

ID

Vin

VDD

Inverter Power Consumption

Power Reduction
Reducing dynamic capacitive power
Lower the voltage!!
Quadratic effect on dynamic power

Total Power Consumption

Ptot = Pdyn + Psc + Pstat tr + t f 2 Ptot = C LV DD f + V DD I max 2 2 Ptot ~ C LV DD f f + V DD I leak

Reduce capacitance!!
Short interconnect lengths Drive small gate load (small gates, small fan-out)

Reduce frequency!!
Lower clock frequency Lower signal activity

2 Pdyn = C LV DD f

Power Reduction
Reducing short-circuit current
Fast rise/fall times on input signal Reduce input capacitance Insert small buffers to clean up slow input signals before sending to large gate

Reducing leakage current

Small transistors (leakage proportional to width) Lower voltage

Chapter 16

Concept of Noise Margins

Chapter 16.3.4

CMOS Inverter Noise Margin

NM L = VIL VOLU Noise Margin for low input NM H = VOHU VIH Noise Margin for high input

CMOS Inverter Noise Margins

CMOS Inverter Noise Margins

of CMOS when

of CMOS when

CMOS Inverter Noise Margins

CMOS Inverter Noise Margins

If CMOS is symmetrical,
of CMOS when

CMOS Inverter Noise Margins

CMOS Inverter Noise Margins

Summary Noise Margin of a Symmetrical CMOS Inverter
NM L = VIL VOLU Noise Margin for low input NM H = VOHU VIH Noise Margin for high input

If CMOS is symmetrical,

Example 16.11

P1047

Chapter 16

Chapter 16.4

CMOS Logic Circuits

CMOS Logic Circuits

Large scale integrated CMOS logic circuits including watches, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits.

CMOS Logic Circuits

CMOS NOR gate can be constructed by using two parallel NMOS devices and two series PMOS transistors.

The output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0.

CMOS Logic Circuits

CMOS Logic Circuits

How can we design CMOS NOR symmetrical gate?
To obtained symmetrical switching times for the high-to-low and low-to-high output transitions, the effective conduction (design) parameters of the composite PMOS and composite NMOS device must be equal. For the CMOS NOR gate,

CMOS NAND gate can be constructed by using two parallel PMOS devices and two series NMOS transistors.

The is at logic 0 when all inputs are high. For all other possible inputs, output is high or at logic 1.

In order to get the symmetrical switching properties, the width to length ratio of PMOS transistor must be approximately eight times that of the NMOS device.

For asymmetrical case, switching time is longer!!

CMOS Logic Circuits

How can we design CMOS NOR symmetrical gate?

Concept of Effective Width to Length Ratios

Parallel combination

Series combination

Two PMOS and two NMOS are working.

Only one PMOS and one NMOS are working.

For the NOR gate the effective width of the drivers transistors doubles. The effective aspect ratio is increased.

For the NAND gate the effective length of the driver transistors doubles. The effective aspect ratio is decreased.

CMOS Logic Circuits

Fan-In and Fan-Out Fan-in
of a gate is the number of its inputs. Thus a four input NOR gate has a fan-In of 4. connected to the output.

Switching Time and Propagation Delay Time

The dynamic performance of a logic circuit family is characterized by propagation delay of its basic inverter. The propagation delay time is define as the average of low-

Fan-Out is the maximum number of load gates that may be

However,
Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates.

The propagation delay time is directly proportional to the switching time and increases as the Fan-out increases. Therefore, the maximum Fanout is limited by the maximum acceptable propagation delay time.

to-high propagation delay time and the high-to-low propagation delay time.

Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates.

CMOS Logic Circuits

Switching Time and Propagation Delay Time
Propagation Delay Time

Propagation Delay Estimate

Switching Time

The two modes of capacitive charging/discharging that contribute to propagation delay

Switch-level model
Delay estimation using switchlevel model (for general RC circuit):
I =C I= V R dV dt
V1

Switch-level model
For fall delay tphl, V0=Vcc, V1=Vcc/2

Rn

CL

dt = RC dV V

dt =

C dV I

RC dV V

V 1V t p = RC ln 1 = RC ln 2 CC V V 0 CC t p = RC ln(0.5) t phl = 0.69 Rn C L t plh = 0.69 R p C L

t1 t0 = t p =

V0

V t p = RC [ln(V1 ) ln(V0 )] = RC ln 1 V 0

Standard RC-delay equations

Chapter 16

Transmission Gates
Use of transistors as switches between driving circuits and load circuits are called transmission gates because switches can transmit information from one circuit to another. NMOS and CMOS transmission gate.

Chapter 16.6

Transmission Gates

The bias applied to the transistor determines which terminal acts as the drain and which terminal acts as the source.

As an Open Switch
When gate voltage =0, the n-channel transistor is cut-off and the transistor acts as an open switch

As an Open Switch
VDD zero

As an Open Switch
VDD zero

@ High input
If =VDD, vI=VDD, and vO is initially (t=0) zero, terminal a acts as the drain since its bias is VDD. terminal b acts as the source since its bias is zero. Current enters the drain from the input charging up the capacitor.
As CL charges up and Vo increases, the gate to source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero. This implies that the VO=VO(max) when VGS=VTN Or VO(max) = VDD-VTN

@ High input

Drain

Source =VDD Gate

Drain

Source =VDD Gate

This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN. This is one of the disadvantage of an NMOS transmission gate when VI=high

Characteristics of NMOS transmission gate (at low input)

When VI=0 and =VDD and VO=VDD-VTN at t=o (initially). It is to be noted that in the present case terminal b acts as the drain and terminal a acts as the source. Under these conditions the gate to source voltage is,

As an Open Switch
zero VDD-VTN

@ Low input
When =VDD, vI=0, and vO =VDD-VTN, at t=0, terminal a acts as the source since its bias is zero. terminal b acts as the drain since its bias is high. Capacitor discharges as current enters the drain. Stop discharging drain current goes zero.

VDD-Vt

Source
G

Drain

VGS=-VI VGS=VDD-o

=VDD Gate

This implies that value of VGS is constant. In this case the capacitor is fully discharge to zero as the drain current goes to zero.

vGS=vDD

source

gate

drain

VDD-VTN
Good logic 0 when VI=low
In this case the capacitor is fully discharge to zero as the drain current goes to zero. VO=0 This implies that the NMOS transistor provide a good logic 0 when VI=low

VO=0
This implies that the NMOS transistor provide a good logic 0 when VI=low

Example 16.13

p1060

Why NMOS transmission gate does not remain in a static condition?

The reverse leakage current due to reverse bias between terminal b and ground begins to discharge the capacitor, and the circuit does not remain in a static condition.

Gate Source Drain VDD-VTN

Example 16.52

p1106

VO(max) = VDD-VTN

(a)

Example 16.52
(b)

p1106

A CMOS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals. The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation.

Case I: Input High condition

Drain Source
NMOS PMOS terminal a acts as the drain terminal b acts as the source terminal c acts as the drain terminal d acts as the source

Case II: Input Low condition

Source Drain
Discharging path

Charging path

NMOS PMOS

terminal a acts as the source terminal b acts as the drain terminal c acts as the source terminal d acts as the drain

In order to charge the load capacitor, current enters the NMOS drain and the PMOS source.

In order to discharge the load capacitor, current enters the NMOS drain and the PMOS source.

Source

Drain

NMOS

NMOS

VGSN continuously change

PMOS

Drain

Source

PMOS

VGSP remains constant

In PMOS, IDP=0, when VSDP=0, which would be possible only, if, VO=VI=5V logic 1 is unattenuated

Finally, VO=0, which is a good logic 0. v SGP = vO = vO 0 = vO

CMOS transmission gate remains in a dynamic condition.

If VO=VDD and =0, then NMOS substrate to terminal b pn junction is reverse biased and capacitor CL can discharge. If VO=0, then the PMOS terminal cto-substrate pn junction is reverse biased and capacitance CL can be charge to a positive voltage. This implies that the output high or low of CMOS transmission gate circuit do not remain constant with time (dynamic behavior).

Test your understanding

p1067

Exercise 16.29 (a)

p10XX

Given that VTN=0.8V, VTP=-1.2V. When = 5V, input vI varies with time as vI =0.5t for 0 t 10 sec. Let VO=0 and CL=1pF. Determine the range of the times that the NMOS and PMOS devices are conducting or cutoff.

NMOS conducting for 0 vI 4.2V NMOS conducting for 0 t 8.4 sec NMOS cutoff for 8.4 t 10 sec

HW solution

Chapter 16

Chapter 16.7

Sequential Logic Circuit

The logic circuits considered thus far are called combinational logic circuits. Their output depend only on the present value of input. This implies that these circuit do not have memory. Another class of the logic circuit that incorporate memory are called sequential logic circuits; that is, their output depend not only the present value of the input, but also on the previous history of inputs. Shift registers and flip-flops are typical examples of such circuits.

Dynamic Shift Registers at Various Time

NMOS A shift register can be constructed by the combination of transmission gates and inverters. If VI=VDD and 1=VDD, then a logic 1=VDD-VTN would exist at VO1. The CL charges through MN1. As VO1 goes high, VO2 goes low. If 2 is high low will transmitted through MN2 and VO4 would be at logic 1. Thus logic 1 shifted from input to output.
Suppose VDD=5V and VTN=1V. At t=t1 , V1=1=5V, vO2 goes low At this time MN2 is still in cutoff (2=0) even though input of MN2 has been changed. This implies that vO3 and vO4 depend on the previous history. Similarly at t=t3, 2 is high, and logic 0 at vO2 is transmitted to vO3, which force vO4 to 5V. Thus the input information is transmitted to output during one clock cycle.

Transparent mode

Hold mode

In shift register the input signal is transmitted, or shifted, from the input to the output during one clock cycle.

Dynamic Shift Registers at Various Time

Consider when t=t4, vI=0, and 1=5V, so VO1=0 and VO2=5V.Vo3 and Vo4 depend on previous history At t=t5, 2=5V, vO3 charges to VDDVTN=4V and VO4 goes low. Thus logic 0 is shifted (transmitted) from input to output. Also note that vO3 and vO4 are depend on previous history of their inputs instead of current inputs (they are having memory).

NMOS shift register is also dynamic (why?)

The output charged capacitor does not remain constant with time because it is discharge through the transmission gate transistor. In order to prevent logic errors, the clock signal period T must be small compared to effective RC discharge time constant.

For example at t = t2, VO1=4V, 1=0 and MN1 is cutoff.VO1 will start to to decay and VO2 will begin to increase.

CMOS Dynamic Shift Registers

The operation of the CMOS shift register is similar to the NMOS register except for the voltage levels. For example, when vI=1=VDD. Then vO1=VDD and vO2=0. when 2 goes high, then vo3 switch to zero, vo4=vDD. Thus input signal is shifted to the output during one clock cycle.

NMOS R-S Flip Flop

Flip- flops are bistable circuits usually formed by cross-coupling two NOR gates. The output of the two NOR circuits are connected back to the inputs of the opposite NOR gates.

When S=logic 1 and R=logic 0 =logic 0 and Q=logic 1=VDD Transistor M2 is then also biased in conducting state.

If S returns to logic 0, nothing in

the circuit can force a change and flip flop stores the previous logic states, although M1 turned off (but M2 remains tuned on).

NMOS R-S Flip Flop (cont.)

When R=logic 1 and S=logic 0 Then M4 turn on so output goes low. With S=Q=Logic 0, both M1 and M2 are cutoff and goes high. The flip-flop is now in reset state. If both S and R inputs go high. Q Then both outputs Q and would go low, which implies that output is not complementary. This condition is forbidden or nonallowed condition.

CMOS R-S Flip-Flop

The operation sequence of CMOS R-S flip flop is same as NMOS. For example: If S = logic 1 and R = logic 0, then MN1, is turned on, Mp1, is Q cut off, and goes low. With = R = logic 0, then both MN3 and MN4 are cut off, both MP3 and Mp4 are biased in a conducting state so that the output Q goes high. With Q = logic 1, MN2 is biased on, Mp2 is biased off, and the flip-flop is in a set condition. When S goes low, MN1, turns off, but MN2 remains conducting, so the state of the flip-flop does not change.
Q

CMOS R-S Flip-Flop (cont.)

When S = logic 0 and R = logic 1, then output Q is forced low, output Q goes high, and the flipflop is in a reset condition. Again, a logic 1 at both S and R is considered to be a forbidden or a nonallowed condition, since the resulting outputs are not complementary.

Static vs Dynamic Storage

Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power

Static D-type Flip-Flop

A D-type flip-flop is used to provide a delay. The logic bit on the D input is transferred to the output at the next clock pulse.

When the CMOS transmission gate turn off (=0), the pn junction in the MN1 transmission gate transistor is reverse biased.