1534 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO.

7, JULY 2011

A 1.8 W 60 nV Hz Capacitively-Coupled
Chopper Instrumentation Amplifier in 65 nm CMOS
for Wireless Sensor Nodes
Qinwen Fan, Student Member, IEEE, Fabio Sebastiano, Student Member, IEEE, Johan H. Huijsing, Life Fellow, IEEE,
and Kofi A. A. Makinwa, Fellow, IEEE

Abstract—This paper presents a low-power precision instrumen- are often quite small (millivolt level), the readout electronics
tation amplifier intended for use in wireless sensor nodes. It em- often consists of an instrumentation amplifier (IA) that precedes
ploys a capacitively-coupled chopper topology to achieve a rail-to- an ADC [1]. Since the RF front-end is usually the most power-
rail input common-mode range as well as high power efficiency. A
positive feedback loop is employed to boost its input impedance, hungry block in a node, its efficient implementation drives the
while a ripple reduction loop suppresses the chopping ripple. To choice of the technology in which the entire node is realized.
facilitate bio-potential sensing, an optional DC servo loop may be In practice, this means the use of deep submicron CMOS pro-
employed to suppress electrode offset. The IA achieves 1 V offset, cesses, as this results in RF front-ends with smaller area and
0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise greater power efficiency [4]–[6], while also being favorable for
efficiency factor of 3.3. The instrumentation amplifier was imple-
mented in a 65 nm CMOS technology. It occupies only 0.1 mm the implementation of ADCs and digital circuitry [7]–[9]. For
chip area (0.2 mm with the DC servo loop) and consumes 1.8 A full integration, the IA must then be realized in the same tech-
current (2.1 A with the DC servo loop) from a 1 V supply. nology.
Index Terms—Bio-signal sensing, chopping, high power effi- However, most recent IAs have been implemented in rel-
ciency, low offset, low power, precision amplifier, wireless sensor atively mature technologies [10]–[18]. Moreover, the power
nodes. consumption of the IAs in [10]–[13] is in excess of 100 W,
which is too high for use in wireless sensor nodes. Although the
IAs in [14]–[18] have sufficiently low power consumption, they
I. INTRODUCTION are optimized for bio-potential (electrocardiology (ECG) and
electroencephalography (EEG)) sensing and have band-pass

N OWADAYS, the use of wireless sensors is opening up

new applications in medical diagnostics, infrastructure
monitoring, and environmental sensing [1]–[3]. In medical di-
characteristics to reject the relatively large electrode offsets that
may arise in such applications. As a result, these IAs cannot
sense the DC outputs of sensors such as resistive bridges, strain
agnostics, wireless sensors can be implanted to monitor bio-po- gauges and thermocouples. To satisfy a variety of wireless
tentials, body temperature and other clinically relevant data; sensors applications with minimum hardware and cost, a low
while in heating, ventilation and air conditioning (HVAC) sys- power multi-purpose precision IA is needed. A promising IA
tems, wireless sensors can be used to optimize energy distribu- topology has been reported in [14], [18], which consists of a
tion by, for instance, establishing patterns of building occupancy chopped inverting opamp whose gain is set by a capacitive
[2]. Individual wireless sensor nodes should be designed for low feedback network. This capacitively-coupled chopper topology
power consumption, small size and low cost [1], [2]. Low power offers rail-to-rail sensing capability, high power efficiency and
consumption (in the order of tens to hundreds of microwatt) is high gain accuracy. However, its input impedance is defined
required, since wireless sensors are typically powered by en- by a switched-capacitor (SC) resistance and is limited to a
ergy harvesters or by batteries, which cannot be easily replaced few Mega ohms at typical chopping frequencies. Furthermore,
or recharged. Small size and low cost facilitate the use of tens the chopping ripple at its output must be filtered out by an
or even hundreds of nodes in a wireless sensor network. Both additional low-pass filter, thus increasing the required chip area
of these requirements can be achieved by integrating the entire significantly. The amplifier can also be used for bio-potential
node on a single chip. sensing by employing a DC-servo loop; however, the imple-
A wireless sensor node consists of a number of sensors, their mentation described in [14] requires large capacitors, which
readout electronics, and an RF front-end. Since sensor signals significantly increase its chip area. Disabling chopping also
enables the use of the IA for bio-potential sensing [18]; how-
ever, this is at the expense of reduced CMRR due to capacitor
Manuscript received November 22, 2010; revised January 28, 2011; accepted
mismatch.
February 24, 2011. Date of publication May 16, 2011; date of current version
June 24, 2011. This paper was approved by Guest Editor Angel Rodriguez- This paper describes a precision IA with high power effi-
Vazquez. ciency which can be used for accurate DC readout as well as
Q. Fan, J. H. Huijsing, and K. A. A. Makinwa are with the Delft University
for bio-potential sensing. Implemented in a 65 nm CMOS tech-
of Technology, Delft, The Netherlands (e-mail: q.fan@tudelft.nl).
F. Sebastiano is with NXP Semiconductors, Eindhoven, The Netherlands. nology, it can be easily integrated in a wireless sensor node [19],
Digital Object Identifier 10.1109/JSSC.2011.2143610 [20]. Instead of employing traditional IA topologies such as the

0018-9200/$26.00 © 2011 IEEE

FAN et al.: A 1.8 W 60 nV Hz CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER IN 65 nm CMOS FOR WIRELESS SENSOR NODES 1535

three-opamp, current feedback or resistive feedback topologies,

it employs the capacitively-coupled chopper topology recently
introduced in [14], [18]. In this work, a positive feedback loop
(PFL) is employed to boost the amplifier’s input impedance,
while the chopping ripple is suppressed by a ripple reduction
loop (RRL). For bio-potential sensing, a DC servo loop (DSL)
establishes a high-pass characteristic [20]. In contrast with [14],
the DSL employs an area-efficient very-large time constant
(VLT) SC integrator [21] to define the amplifier’s high-pass
Fig. 1. A simplified block diagram of a capacitively-coupled chopper instru-
corner. mentation amplifier.
The paper is organized as follows. In Section II, the advan-
tages and disadvantages of the traditional IA topologies are dis-
cussed. The capacitively-coupled chopper topology is then pre- the baseband. Compared to IAs based on the three traditional
sented in Section III. The working principle and the implemen- topologies, a CCIA has four main advantages.
tations of the PFL, the RRL and the DSL will be described in 1) Rail-to-rail sensing capability: with employing com-
Section IV. In Section V, experimental results will be shown plementary switches, a CCIA has a rail-to-rail DC CM
and the paper ends with conclusions. input range without requiring a rail-to-rail input stage for
the opamp.
II. TRADITIONAL TOPOLOGIES 2) High power efficiency: the noise of a CCIA is dominated
Three topologies have been traditionally used to realize by that of the opamp [14], [18], thus it is more power effi-
IAs: the three-opamp, current feedback and resistive feedback cient than the three-opamp and current-feedback IAs.
topologies. The classic three-opamp topology [22]–[26] has 3) High gain accuracy: The accurate lithography of deep sub-
high input impedance and excellent linearity. However, its micron technology results in good matching between
power efficiency is reduced by the need for the two low-noise and , which in turn ensures high gain accuracy without
input amplifiers. Furthermore, the three-opamp IAs can not the need for trimming.
sense the rail since their input CM voltage must also fall 4) Suitability for low power design. The capacitive feedback
within the input amplifiers’ output voltage range. Current feed- network can be designed to have relatively large imped-
back IAs (CFIAs) [10]–[13] also have high input impedance. ances, which minimizes the current consumption of the
However, their gain accuracy is limited by the mismatch be- feedback network, especially for large output signals.
tween their input and feedback transconductances. CFIAs can B) Design Considerations: A block diagram of the proposed
have rail-sensing capability by employing either an NMOS CCIA is shown in Fig. 2. It is based on a two-stage Miller-com-
or PMOS-based input differential pairs. However, achieving pensated opamp, which consists of an input transconductance
rail-to-rail input capability as well as high gain accuracy is quite and an integrator built around . A capacitive bridge
challenging, as the mismatch between their input and feedback comprising of input capacitors and feedback capacitors
transconductors is usually also a function of the input CM is built around the opamp. Taking into account the finite
voltage [13]. The power efficiency of CFIAs is also limited by open-loop gain of the opamp, the gain G of the CCIA is given
the need for the two input and feedback transconductances. The by
resistive feedback topology [27] is a third option. However, the
value of its input resistors is a compromise between noise and (1)
input impedance. Last but not least, the closed-loop gain of the
all three topologies is defined by a resistive network that loads
where is the open-loop gain of the opamp. To ensure a
the IA’s output stage. For a 1 V output voltage and a 100 k
gain inaccuracy better than 0.1%, for example, should be
feedback network, the current required to drive the network is
larger than 100 dB. This is not easily achieved by a single
10 A, which is already larger than the total supply current of
stage opamp, which is why a two-stage Miller-compensated
the IAs in [14]–[20]. Increasing the resistance of the network
opamp was chosen. The combination of and
is not a very attractive option as it leads to larger chip area and
can be seen as an equivalent input resistor with a resistance
more noise.
of , where is the chopping frequency. This
resistor then defines the input impedance of the CCIA. The
III. CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION combination of and can be seen as an equivalent
AMPLIFIER (CCIA) feedback resistor with a resistance of that loads
A) Basic Topology: The capacitively-coupled chopper the CCIA’s output stage. The offset and noise of are
topology has recently been employed in bio-potential sensing up-modulated by and then filtered by the integrator built
IAs [14], [18]. As shown in Fig. 1, it comprises an opamp (A) around . The up-modulated offset and noise generate
and a capacitive feedback network ( and ), an input a ripple, which will be suppressed by the ripple-reduction loop
chopper , a feed back chopper and a third chopper (RRL) introduced in Section IV. The offset and noise of
. To first-order, the gain of the IA is defined by is suppressed by the gain of . The DC level at the
and the offset and noise of the opamp are removed from opamp’s input is properly biased to a reference voltage
1536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011

Fig. 2. A schematic of the proposed capacitively-coupled chopper instrumen-

tation amplifier.

Fig. 3. A schematic of the capacitively-coupled instrumentation amplifier

by high-resistance resistors implemented as MOS transistors opamp.
operated in their sub-threshold region [14].
The action of the choppers will produce spikes since the
bridge capacitors and are constantly being the final gain inaccuracy will be determined by the process
charged and discharged by the input and output signal voltages. spread and variation of , which is expected to be
Due to the opamp’s finite output impedance, the output spikes around 0.1%. The CCIA’s noise is dominated by the noise of
associated with will be fed to a succeeding ADC and the input stage of . To achieve high power efficiency, the
could cause error. To reduce the duration of these spikes, the input PMOS differential pair is biased in weak inversion. It
CCIA opamp’s output stage must be able to provide currents consumes 61% of the total supply current and consequently, a
much larger than the average DC current required to drive 55 nV Hz simulated noise voltage density of the
the capacitive bridge. To reduce the amplitude of the spikes, input stage is obtained. With , the CCIA’s
smaller feedback capacitors can be chosen at the expense of input-referred noise is essentially equal to [14]. The
lower capacitance matching. A low-pass filter can be used after Miller capacitor (fringe capacitor) are chosen to be
the CCIA to suppress the spikes; however, this is at the expense 30 pF, and so the unity-gain frequency of the CCIA is 70 kHz.
of extra power consumption and chip area. A better solution is The bias current of the class-A output stage is chosen to be
to ensure that the succeeding ADC only samples the CCIA’s 2 50 nA which is sufficient to drive the capacitive bridge with
output after it has fully settled. This can be readily implemented a 1 Vpp output signal.
in fully integrated systems. The bias resistors are implemented as NMOS transis-
C) Implementation: In this implementation, the gain of the tors biased in the sub-threshold region. Their resistance is set to
CCIA is fixed to 100. is chosen to be 5 kHz, which is approximately 10 to obtain an input noise density of about
higher than the noise corner of . Increasing will 10 nV Hz [14], which is negligible compared to that of the
result in more charge injection and clock feed-through, leading whole CCIA.
to higher residual offset [28]. With pF and
fF, the equivalent input and feedback resistances are around
IV. POSITIVE FEEDBACK LOOP (PFL), RIPPLE REDUCTION
8 M and 800 M respectively without considering parasitic
LOOP (RRL), AND THE DC SERVO LOOP (DSL)
effects. Fringe capacitors (metal-oxide-metal) were employed
to implement the capacitive bridge. The CCIA has two main drawbacks: 1) limited input
The schematic of the opamp is shown in Fig. 3. For high DC impedance mainly determined by the equivalent resistance
gain, is implemented as a folded-cascode OTA, while for determined by and , and 2) chopping ripple due to
large output swing, is implemented as a class-A output the up-modulated offset and noise of .
stage. All transistors used in the CCIA are thick-oxide transis- To boost the input impedance of the CCIA, a positive feed-
tors despite their relatively high threshold voltages (0.6 V). This back loop (PFL) is employed. It consists of a positive feedback
is because such transistors have low gate leakage currents and path connected between the input and the output of the CCIA. It
also offer higher intrinsic gain. In a low power design, leakage converts the output voltage into a current which is injected back
currents can cause significant errors, especially at the opamp’s into the signal source. This current partially compensates for the
virtual ground node . Due to noise considerations, the current drawn from the signal source by the switched capacitor
resistance of the bias resistors is about 10 , and so 50 pA of resistor formed by and , thus increasing the CCIA’s
gate leakage from the two PMOS input transistors is more than input impedance.
enough to cause the input voltage to clip. The simulated DC gain The chopping ripple is mainly due to the up-modulated offset
of the two-stage Miller-compensated CCIA opamp is 130 dB, and noise of . To suppress it, a ripple-reduction loop
which according to (1) corresponds to a gain errors 0.01% for (RRL) is employed [10], [13]. This senses the ripple at the
. Since the gain is mainly determined by , CCIA’s output and generates a current which compensates for
FAN et al.: A 1.8 W 60 nV Hz CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER IN 65 nm CMOS FOR WIRELESS SENSOR NODES 1537

Fig. 5. A simplified block diagram of the ripple reduction loop.

Fig. 4. A schematic of the capacitively-coupled instrumentation amplifier with
the positive feedback loop.
where is the original input impedance and is the
boosted input impedance, is the net current drawn from
’s offset current. When this current is fully compensated, the signal source.
no output ripple will be present. 3) Parasitic Effects: In practice, the parasitic capacitance
For bio-sensing applications, where large DC electrode off- located between ’s bottom-plate and ground shown
sets are expected, a DC servo loop (DSL) can be optionally em- in Fig. 4 will further limit the input impedance. and
ployed. The DSL is essentially an integrating negative feedback act as an equivalent parasitic resistor with a resistance
path. The CCIA’s output is integrated and the resulting signal is of . The current drawn by this resistor will
fed back to its virtual ground in such a way as to cancel any DC not be compensated by a PFL dimensioned according to (2).
component at the CCIA’s output. The DSL acts as a high-pass As a result, this parasitic resistor limits the maximum input
filter that effectively rejects electrode offset, which could oth- impedance. In a standard CMOS process, ranges between
erwise saturate the CCIA. The working principles and design 10% to 40% of . This means that a PFL dimensioned
considerations of the PFL, RRL and the DSL will be explained according to (2) will only boost the input impedance by a factor
in more detail in the following sections. of 2.5 to 10 . To overcome this, the PFL can be designed
to also compensate for the extra current flowing through the
A. Positive Feedback Loop (PFL) parasitic resistor . Equation (2) can then be modified as
follows:
1) Working Principle: A block diagram of the CCIA with a
PFL is shown in Fig. 4. The loop comprises a chopper and
two feedback capacitors which provide positive feedback
to the CCIA’s input. In the ideal situation, the PFL generates
currents equal to , so that no input current is drawn (4)
from the signal source and the input impedance of the CCIA is
infinite. The value of for infinite input impedance can be where is the modified compensating current pro-
calculated by making and equal: vided by the PFL, and is the optimal value for
. In practice, however, the exact value of will be
uncertain, and so can be made adjustable in order to
obtain maximum input impedance.

(2) B. Ripple Reduction Loop

1) Working Principle: The up-modulated ’s offset and
The PFL loads the CCIA since the current flowing through it has noise create a ripple at the output of the CCIA. With 10 mV
to be supplied by the CCIA. The equivalent loading resistance offset, , and pF,
is around M . This loading is equal to the ripple at the output is approximately
that of the negative feedback path .
2) Implementation: With , pF and
fF, has to be 121.21 fF to reach an infinite
(5)
input impedance according to (2). This can be challenging in
This would take excessive headroom for a 1 V supply and must
layout and thus in this work, are chosen to be equal to
be suppressed. Decreasing leads to more noise, while in-
. The compromised boosted input impedance of the CCIA
creasing and results in larger residual offset and
is then given by
more chip area respectively. There are several effective tech-
niques to reduce the ripple. In [29], a switched-capacitor notch
(3)
filter is employed to notch out the chopping ripple. This method
1538 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011

Fig. 6. A schematic of the ripple reduction loop with the proposed switched-capacitor integrator.

is very power efficient. However, including a notch filter in the , convert the ripple voltage into an AC current, which
signal path complicates the frequency compensation. In [30], an is then demodulated by and integrated on . The
auto-correction loop is used to reduce the ripple. This method voltages on are then converted into a current by
simplifies the required frequency compensation. However, the to compensate for ’s offset current. During , are
loop senses the ripple at a virtual ground node, where it is quite shorted to ground so that no ripple current is integrated. is
small, and so requires a relatively high gain. In this work, an configured in unity-gain configuration so that its offset is sam-
AC coupled continuous-time ripple reduction loop (RRL) is em- pled and stored on . During this time, are discon-
ployed [10], [13]. A block diagram of the RRL is shown in nected from the output of , holding the voltage set at the end
Fig. 5. It consists of sensing capacitors , a demodulating of last ; and connected to the input of . In this way, the
chopper , an integrator and a compensation transcon- correct compensating current is injected into during both
ductor . Instead of sensing at the virtual ground node of phases. In the ideal case, the compensating current fully com-
[30], sense and convert the large ripple voltage at pensates for ’s offset current, leaving no output ripple at the
the amplifier’s output into an AC current; the AC current is then steady state.
integrated by the integrator into a voltage; this voltage is then 2) Implementation: The values of , and the
converted by into a current, which compensates for ’s transconductance of determine the RRL’s unity-gain
offset current. The RRL creates a notch at with a width de- frequency which is given by [13]
termined by flexible design parameters such as , and
[13]. Compared to [30], the main drawback of this method is (6)
that loads the amplifier’s output, and thus should be kept
small. The notch width of the RRL equals to . With the CCIA’s
In [10] and [13], a passive integrator comprising a current bandwidth equal to 700 Hz and equal to 5 kHz,
buffer and an integration capacitor is used in the RRL. The offset should be smaller than 4.3 kHz to maintain CCIA’s signal band-
of the current buffer, however, generates second harmonic ripple width. Moreover, the value of usually has to be smaller
which could require large integration capacitor to filter [10], than to suppress the noise of the RRL , which is
[13]. This is more problematic for low . To overcome this calculated by the following equation when referred to the input
problem, an auto-zeroed SC integrator can be employed. How- of the CCIA
ever, a standard auto-zeroed SC integrator is reset during one
phase so that its offset can be stored on an auto-zero capacitor.
During that phase, the output of the integrator can not be con-
nected to , otherwise, an error compensating current will (7)
be injected into the CCIA. To solve this problem, an auto-ze- where is the output voltage noise of the RRL integrator;
roed SC integrator with valid output voltage during all phases is the input voltage noise of . To make neg-
is proposed. A block diagram of the RRL with such an inte- ligible compared to ’s noise, is designed to be 0.65
grator is shown in Fig. 6. The SC integrator comprises sensing which is 20 smaller than . Together with fF,
capacitors ; a demodulation chopper ; integration pF and pF, is calculate by
capacitors ; auto-zero capacitors and a single stage (6) to be around 330 Hz which is much smaller than 4.3 kHz.
opamp . is synchronized to . The rest of the With fF, this RRL hardly loads the output of the
switches are driven at switching frequency which CCIA. are chosen to be 1.4 pF with the considerations of
is chosen to be half of . contains an integration phase suppressing charge injection errors from switch and saving
and an auto-zero phase and each phase incorporates a com- chip area.
plete cycle of , thus during , a full cycle ripple can be de- employs a telescopic topology to obtain large DC open
tected by the RRL. A timing diagram is shown in Fig. 6. During loop gain and its schematic is shown in Fig. 7. ’s open loop
FAN et al.: A 1.8 W 60 nV Hz CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER IN 65 nm CMOS FOR WIRELESS SENSOR NODES 1539

Fig. 7. A schematic of the ripple reduction loop switched-capacitor integrator Fig. 8. A block diagram of the capacitively-coupled instrumentation amplifier
opamp. with the optional DC servo loop.

gain determines the RRL’s loop gain which is given signals [15], [16]. The values of is determined by the
by [13] following equation

(8) (10)

Ideally, the ripple should be suppressed by a factor equal to L(0). where is the maximum expected electrode offset and
To suppress the output ripple by 1000 times so that the input- is the maximum output voltage of the DSL integrator
referred ripple is in the order of a few microvolts, should and in this case equals to the supply voltage 1 V.
be at least 48 dB. The open loop gain of the telescopic is For wet electrodes, a maximum of 50 mV can be expected
simulated to be 76. consumes 50 nA supply current, which [14], [15]. Thus, are chosen to be 600 fF. And
is negligible compared to the total current consumption of the is calculated to be 0.1 Hz by (9). An SC integrator with such
CCIA. a low unity-gain frequency can occupy large chip area [14]
which is not suitable for wireless sensor nodes. In this work, a
C. DC Servo Loop (DSL) very-large time constant (VLT) SC integrator [21] is employed
to save the chip area significantly.
1) Working Principle and Implementation: The DSL can be
2) Very-Large Time Constant SC Integrator (VLT SC Inte-
optionally employed for bio-sensing when large electrode offset
grator): A block diagram of the VLT SC integrator is shown in
is present. Although a high-pass transfer function can be easily
Fig. 9. The integrator comprises an opamp and a capacitor net-
obtained by disabling the choppers around the CCIA [16]–[18],
work around it ( , , and ). All switches in
the degraded CMRR due to feedback capacitors mismatch how-
the capacitor network are driven at a switching frequency
ever, is undesirable. To obtain a high CMRR, chopping is main-
equal to in order to sample at the zero-crossing point of
tained, and a high-pass transfer function is realized by imple-
the CCIA’s output ripple. A timing diagram is shown in Fig. 9.
menting a DSL as also in [14]. The low-pass characteristic is
The transfer function of a VLT SC integrator is given by the fol-
automatically granted by the limited bandwidth of the CCIA,
lowing equation [21] when :
which is larger than the maximum ECG/EEG signal bandwidth
(around 100 Hz). A block diagram of the CCIA with such a
DSL is shown in Fig. 8. The DSL comprises an integrator which (11)
amplifies the DC signal at the output of the CCIA; a chopper
which up-modulates the amplified DC signal; and capac- By making equal to unity, the unity-gain frequency
itors which feed the up-modulated signal to the CCIA of the VLT-SC integrator can be computed as
virtual ground . The integrator will keep integrating until
the signal at the output of the CCIA is DC free. The DSL creates (12)
a high-pass corner which is given by [14]

(9) The unity-gain frequency of a standard fully differential

SC integrator (shown in Fig. 10) is given by
where is the unity-gain frequency of the integrator in the
(13)
DSL. is set to 0.5 Hz for bio-signals such as ECG/EEG
1540 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011

Fig. 9. A block diagram of the very-large time constant switched-capacitor in-

tegrator.

Fig. 11. Chip microphoto.

Fig. 10. A block diagram of a standard switched-capacitor integrator.

where is the switching frequency for switches . In Fig. 12. Histogram of the residual offset.
this work, to achieve the 0.1 Hz unity-gain frequency calculated
by (9), when switching at 2.5 kHz, the VLT SC integrator uses
fF and pF, while to achieve noise floor is flat until 100 mHz which proves that the noise
the same unity-gain frequency with the same sampling capac- is effectively removed by chopping. After activating the PFL,
itor, a standard integrator has to use pF ac- the measured input-impedance increases from 6 M to 30 M .
cording to (13)! This proves that the VLT SC integrator is much The original input-impedance and the boost factor is lower
more area efficient. than expected (8 M and 100) due to the presence of parasitic
input capacitors, as has been explained in Section IV. The RRL
V. EXPERIMENTAL RESULTS reduces the amplitude of the output ripple to less than 300 V
The circuit was implemented in a 65 nm CMOS technology. at all the harmonics. This output ripple is relatively large
The CCIA operates from a 1 V supply, from which it draws compared to those reported in [10], [13], [29], [30]. The limited
1.8 A without the DSL and 2.1 A with the DSL. The active power consumption (50 nW) restricted the DC gain of ,
chip area is 0.1 mm without the DSL and 0.2 mm with the which in turn leads to a RRL with relatively low loop gain.
DSL. A chip photo is shown in Fig. 11, which includes the DSL. However, at a gain of 100, the input-referred ripple (3 V) is
With the DSL off, the measured DC CMRR is greater than of the same order as the residual offset, and is thus low enough
134 dB, while the DC PSRR is greater than 120 dB for 20 for most applications. The transient response of the CCIA to
samples. The worst-case measured offset is 1 V. A histogram a 500 mV output step is shown in Fig. 15. The spikes due to
of the offset is shown in Fig. 12. Apart from layout issues the various switching events are also shown. It can be seen that
which are very critical, this residual offset is also due to the the output settles well before the end of the clock phase so that
mismatched charge injection and clock feed-through associated an ADC can avoid the spikes by sampling just before the next
with the choppers [28]. The relative DC gain accuracy of the clock transition. Table I summarizes the CCIA’s performance
CCIA is better than 0.16%. A histogram of the gain variation without the DSL and compares it with other state-of-the-art IAs
is shown in Fig. 13. As shown in Fig. 14, the measured output featuring high DC accuracy. This work achieves the highest
noise spectrum density is 6 V Hz, which is equivalent to power efficiency, which is indicated by a low Noise Efficiency
an input-referred noise of 60 nV Hz. This confirms that the Factor ( , where
noise is mostly dominated by the input stage. Furthermore, the is the input-referred rms noise voltage, is the total
FAN et al.: A 1.8 W 60 nV Hz CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER IN 65 nm CMOS FOR WIRELESS SENSOR NODES 1541

Fig. 13. Histogram of the relative gain accuracy.

Fig. 15. Transient step response of the capacitively-coupled instrumentation
amplifier.

TABLE I
PERFORMANCE SUMMARY

Fig. 14. Output noise spectrum of the capacitively-coupled instrumentation

amplifier with a gain of 100 (Y axis: log format; 2 V Hz–20 V Hz;
X axis: log format; 100 mHz-10 Hz).

current consumption and BW is the amplifier’s bandwidth in

Hertz [17]). Although such a low NEF is partly due to the
smaller bandwidth compared to [10]–[13] and the fact that the
CCIA is not designed to be unity-gain stable; the benefit of
the CCIA topology is still evident as its noise is dominated by
a single amplifier: . The CCIA also achieves the lowest
residual offset, as well as the lowest supply voltage and power
consumption, attributes that are critical for wireless sensor
nodes. For bio-potential measurements, the DSL is added,
resulting in the high-pass frequency response shown in Fig. 16.
The high-pass corner frequency is located at 0.5 Hz. At fre-
quencies below 100 Hz, the measured AC CMRR is larger
than 110 dB which is at least 30 dB higher than [16], [17]. The
Fig. 16. The high-pass response of the capacitively-coupled instrumentation
chip area with the DSL is 7 smaller than that of the fully amplifier with the DC servo loop. (Y axis: log format; 10–100; X axis: log
differential version of [14] where a similar DSL is employed format; 100 mHz–500 Hz).
but with a less area-efficient SC integrator. The noise of the
CCIA with the DSL increases to 6.7 in a bandwidth of
0.5–100 Hz for bio-signals. power consumption and occupies a chip area of 0.2 mm . The
deep submicron technology, the low supply voltage, low power
VI. CONCLUSION consumption and low area makes the CCIA suitable for a va-
A precision CCIA has been implemented in a 65 nm CMOS riety of wireless sensor applications.
technology. For DC measurements, it achieves state-of-the-art
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auto-zero offset-stabilized CMOS instrumentation amplifier,” in Symp. search interests include precision analog amplifiers, biomedical interface cir-
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[14] T. Denison, K. Consoer, and W. Santa et al., “A 2 W 100 nV Hz Fabio Sebastiano (S’09) was born in Teramo, Italy,
chopper stabilized instrumentation amplifier for chronic measurement in 1981. He received the B.Sc. (cum laude) and M.Sc.
of neural field potentials,” IEEE J. Solid-State Circuits, vol. 42, no. 12, (cum laude) degrees in electrical engineering from
pp. 2934–2945, Dec. 2007. University of Pisa, Italy, in 2003 and 2005, respec-
[15] R. F. Yazicioglu, P. Merken, and R. Puers et al., “A 200 W tively. In 2006, he received the Diploma di Licenza
eight-channel acquisition ASIC for ambulatory EEG systems,” in from Scuola Superiore Sant’Anna, Pisa, Italy.
IEEE ISSCC Dig. Tech. Papers, 2008, pp. 164–165. In 2006, he joined NXP Semiconductors Research
[16] N. Verma, A. Shoeb, and J. Bohorquez et al., “A micro-power EEG ac- in Eindhoven, The Netherlands, where he is also
quisition SoC with integrated feature extraction processor for a chronic working toward the Ph.D. degree in collaboration
seizure detection system,” IEEE J. Solid-State Circuits, vol. 45, no. 4, with Delft University of Technology. His main
pp. 804–816, Apr. 2010. research interests are ultra-low power radios for
[17] R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier wireless sensor networks, fully integrated crystal-less frequency references and
for neural recording applications,” IEEE J. Solid-State Circuits, vol. sensor interfaces.
38, no. 6, pp. 958–965, Jun. 2003. Mr. Sebastiano was a co-recipient of the 2008 ISCAS Best Student Paper
[18] D. Yeager, F. Zhang, and A. Zarrasvand et al., “A 9 A, addressable Award.
gen2 sensor tag for biosignal acquisition,” IEEE J. Solid-State Circuits,
vol. 45, no. 10, pp. 2198–2209, Oct. 2010.
[19] Q. Fan, J. H. Huijsing, and K. Makinwa, “A 1.8 W 1 V-offset capac-
itively-coupled chopper instrumentation amplifier in 65 nm CMOS,” in Johan H. Huijsing (SM’81–F’97–LF’10) was born
Proc. ESSCIRC, 2010, pp. 170–173. on May 21, 1938. He received the M.Sc. degree in
[20] Q. Fan, J. H. Huijsing, and K. Makinwa, “A 2.1 W area-efficient ca- electrical engineering from the Delft University of
pacitively-coupled chopper instrumentation amplifier for ECG appli- Technology, The Netherlands, in 1969, and the Ph.D.
cations in 65 nm CMOS,” in Proc. ASSCC, 2010, pp. 337–340. degree from the same University in 1981.
[21] K. Nagaraj, “A parasitic-insensitive area-efficient approach to realizing He has been an Assistant and Associate Professor
very large time constants in switched-capacitor circuits,” IEEE Trans. in Electronic Instrumentation at the Faculty of Elec-
Circuits Syst., vol. 36, no. 9, pp. 1210–1216, Sep. 1989. trical Engineering of the Delft University of Tech-
[22] R. P. Areny and J. G. Webster, “AC instrumentation amplifier for nology since 1969. He became a full Professor in the
bioimpedance measurements,” IEEE Trans. Biomed. Eng., vol. 40, no. chair of Electronic Instrumentation since 1990, and
8, pp. 830–833, Aug. 1993. Professor Emeritus since 2003. From 1982 through
[23] M. J. Burke and D. T. Gleeson, “A micropower dry-electrode ECG 1983 he was a senior scientist at Philips Research Labs. in Sunnyvale, CA. From
preamplifier,” IEEE Trans. Biomed. Eng., vol. 47, no. 2, pp. 155–162, 1983 until 2005 he was a consultant for Philips Semiconductors, Sunnyvale, CA,
Feb. 2000. and since 1998 also a consultant for Maxim, Sunnyvale, CA. His research work
[24] E. M. Spinelli, R. Pallas-Areny, and M. A. Mayosky, “AC-coupled is focused on operational amplifiers, analog-to-digital converters and integrated
front-end for biopotential measurements,” IEEE Trans. Biomed. Eng., smart sensors. He has supervised 30 Ph.D. students. He is an author or coauthor
vol. 50, no. 3, pp. 391–395, Mar. 2003. of more than 300 scientific papers, 40 U.S. patents, and 15 books.
[25] E. M. Spinelli, N. Martinez, M. A. Mayosky, and R. Pallas-Areny, “A In 1992 Dr. Huijsing initiated the international Workshop on Advances in
novel fully differential biopotential amplifier with DC suppression,” Analog Circuit Design. He co-organized it yearly until 2003. He has been a
IEEE Trans. Biomed. Eng., vol. 51, no. 8, pp. 1444–1448, Aug. 2004. member of the programme committee of the European Solid-State Circuits Con-
[26] C. J. Yen, W. Y. Chung, and M. C. Chi, “Micro-power low-offset ference from 1992 until 2002. He was chairman of the Dutch STW Platform
instrumentation amplifier for biomedical system applications,” IEEE on Sensor Technology and of the biannual national Workshop on Sensor Tech-
Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 4, pp. 691–699, Apr. nology from 1991 until 2002. He is a Life Fellow of IEEE, and was awarded
2004. the title of Simon Stevin Meester by the Dutch Technology Foundation.
FAN et al.: A 1.8 W 60 nV Hz CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION AMPLIFIER IN 65 nm CMOS FOR WIRELESS SENSOR NODES 1543

Kofi A. A. Makinwa (M’97–SM’05–F’11) received sign of precision analog circuitry, sigma-delta modulators, smart sensors and
the B.Sc. and M.Sc. degrees from Obafemi Awolowo sensor interfaces. This has resulted in one book, 14 patents, and over 120 tech-
University, Nigeria, in 1985 and 1988, respectively. nical papers.
In 1989, he received the M.E.E. degree from the Dr. Makinwa is on the program committees of several international confer-
Philips International Institute, The Netherlands, and ences, including the European Solid-State Circuits Conference (ESSCIRC) and
in 2004, the Ph.D. degree from Delft University of the IEEE International Solid-State Circuits Conference (ISSCC). He has also
Technology, The Netherlands. served as a guest editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC).
From 1989 to 1999, he was a Research Scientist He is the co-recipient of several best paper awards, from the JSSC, ISSCC, and
with Philips Research Laboratories, Eindhoven, The ESSCIRC, among others. In 2005, he received a Veni Award from the Nether-
Netherlands, where he worked on interactive displays lands Organization for Scientific Research and the Simon Stevin Gezel Award
and on front-ends for optical and magnetic recording from the Dutch Technology Foundation. He is a Distinguished Lecturer of the
systems. In 1999, he joined Delft University of Technology, where he is now IEEE Solid-State Circuits Society, a Fellow of the IEEE, and a Fellow of the
an Antoni van Leuwenhoek Professor in the Faculty of Electrical Engineering, Young Academy of the Royal Netherlands Academy of Arts and Sciences.
Computer Science and Mathematics. His main research interests are in the de-