Philips Semiconductors Linear Products Product specification

12-Bit multiplying D/A converter AM6012

DESCRIPTION PIN CONFIGURATION

The AM6012 12-bit multiplying Digital-to-Analog converter provides D1 and F Packages
high-speed and 0.025% differential nonlinearity over its full
commercial temperature range.
D1 1 20 V+
The D/A converter uses a 3-bit segment generator for the MSBs in D2 2 19 I
O
conjunction with a 9-bit R-2R diffused resistor ladder to provide D3 3 18 I
O
12-bit resolution without costly trimming processes. This technique 4 17 V–
D4
guarantees a very uniform step size (up to ± LSB from the ideal), 5 16 COMP
D5
monotonicity to 12 bits and integral nonlinearity to 0.05% at its
D6 6 15 V
differential current outputs. REF(–)
D7 7 14 VREF(+)
The dual complementary outputs of the AM6012 increase its D8 8 13 GND/V
LC
versatility, and effectively double the peak-to-peak output swing. 9 12 D LSB
D9 12
Digital inputs, in addition, can be configured to accept all popular
D10 10 11 D
11
logic families.
TOP VIEW
While the device requires a reference input of 1mA for a 4mA
full-scale current, operation is nearly independent of power supply NOTE:
voltage shifts. The power supply rejection ratio is ±0.001% FS/% ∆V. 1. Available in large SO (SOL) package only.
The devices will work from +5, -12V to ±18V rails, with as low as
230mW power consumption typical.

APPLICATIONS
FEATURES • CRT displays, computer graphics
• 12-bit resolution • Robotics and machine tools
• Accurate to within ±0.05% • Automatic test equipment
• Monotonic over temperature • Programmable power supplies
• Fast settling time, 250ns typical • CAD/CAM systems
• Trimless design for low cost • Data acquisition and control systems
• Differential current outputs • Analog-to-digital converter systems
• High-speed multiplying capability
• Full-scale current, 4mA (with 1mA reference)
• High output compliance voltage, -5 to +10V
• Low power consumption, 230mW

ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
20-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C AM6012F 0584B
20-Pin Plastic Small Outline Large (SOL) Package 0 to +70°C AM6012D 0172D

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Philips Semiconductors Linear Products Product specification

12-Bit multiplying D/A converter AM6012

BLOCK DIAGRAM
GND/MSB LSB
V(+) VLC B1 B2 B3 B4 B5 B6 B7 b8 B9 B10 B11 B12

20 13 1 2 3 4 5 6 7 8 9 10 11 12

DECODER LOGIC SWITCHES

BIAS 18
IO
NETWORK 19
IO
REFERENCE
AMPLIFIER CURRENT
14 SWITCHES
VREF (+)

15 9-BIT R-2R
VREF (–) ISEG
9-SEGMENT
D/A CONVERTER
GENERATOR

16 17

COMP V(–)

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT
TA Operating temperature
AM6012F 0 to +70 °C
TSTG Storage temperature range -65 to +150 °C
TSOLD Lead soldering temperature 10sec max 300 °C
VS Power supply voltage ±18 V
Logic inputs -5V to +18 V
Voltage across current outputs -8V to +12 V
VREF Reference inputs V14, V15 V- to V+
VREF Reference input differential voltage (V14 to V15) ±18 V
IREF Reference input current (I14) 1.25 mA
PD Maximum power dissipation, TA=25°C, (still-air)1
F package 1560 mW
D package 1390 mW
NOTES:
1. Derate above 25°C, at the following rate:
F package at 12.5mW/°C
D package at 11.1mW/°C

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12-Bit multiplying D/A converter AM6012

DC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0°C ≤ TA ≤ 70°C
LIMITS
SYMBOL PARAMETER TEST CONDITIONS UNIT
Min Typ Max
Resolution 12 Bits
Monotonicity 12 Bits
DNL Differential nonlinearity Deviation from ideal step size ±0.025 %FS
12 Bits
NL Nonlinearity Deviation from ideal straight line ±.05 %FS
VREF=10.000V
IFS Full-scale current R14-R15=10.000kΩ 3.935 3.999 4.063 mA
TA=25°C
TCIFS Full-scale tempco ±10 ±40 ppm/°C
±0.001 ±0.004 %FS/°C
DNL Specification guaranteed over
VOC Output voltage compliance compliance range -5 +10 V
ROUT>10MΩ typ.
IFSS Symmetry IFS-IFS ±0.4 ±2.0 µA
IZS Zero-scale current 0.10 µA
Logic
VIL
input Logic “0” 0.8 V
VIH
levels
Logic “1” 2.0
IIN Logic input current VIN=-5 to +18V 40 µA
VIS Logic input swing V-=-15V -5 +18 V
IREF Reference current range 0.2 1.0 1.1 mA
I15 Reference bias current 0 -0.5 -2.0 µA
R14(eq)=800Ω
dl/dt Reference input slew rate 4.0 8.0 mA/µs
CC=0pF
PSSIFS+ Power supply sensitivity V+=+13.5V to +16.5V, V-=-15V ±0.0005 ±0.001 %FS/%
PSSIFS- V-=-13.5V to -16.5V, V+=+15V ±0.00025 ±0.001
V+ Power supply range VOUT=0V 4.5 18 V
V- -18 -10.8
I+ V+=+5V, V-=-15V 5.7 8.5
I- Power supply current -13.7 -18.0 mA
I+ V+=+15V, V-=-15V 5.7 8.5
I- -13.7 -18.0
PD Power dissipation V+=+5V, V-=-15V 234 312 mW
V+=+15V, V-=-15V 291 397

AC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0°C ≤ TA ≤ 70°C
LIMITS
SYMBOL PARAMETER TEST CONDITIONS UNIT
Min Typ Max
tS Settling time To ± 1/2LSB, all bits ON or OFF, TA=25°C 250 500 ns
tPLH Propagation
50% to 50% 25 50 ns
tPHL delay—all bits
COUT Output capacitance 20 pF

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12-Bit multiplying D/A converter AM6012

CIRCUIT DESCRIPTION splitting utilizing scaled emitters. This saves ladder resistors and
The AM6012 is a 12-bit DAC which uses diffused resistors and greatly reduces the range of emitter scaling required in the 9-bit
requires no trimming to guarantee monotonicity over the DAC. All current switches in the step generator are high-speed
temperature range. A segmented DAC design guarantees a more fully-differential switches which are capable of switching low currents
uniform step size over the temperature range than is normally at high speed. This allows the use of a binary scaled network all the
available with trimmed 12-bit converters. The converter features way to the least significant bit which saves power and simplifies the
differential high compliance current outputs, wide supply range, and circuitry.
a multiplying reference input. Diffused resistors have advantages over thin film resistors beyond
In many converter applications, uniform step size is more important simple economy and bipolar process compatibility. The resistors are
than conformance to an ideal straight line. Many 12-bit converters fabricated in single crystal rather than amorphous material which
are used for high resolution rather than high linearity, since few gives them better long term stability and tracking and much higher
transducers are more linear than ±0.1%. All classic binarily weighted moisture resistance. They are diffused at 1000°C and so are
converters require ±1/2LSB (±0.012%) linearity in order to guarantee resistant to changes in value due to thermal and chemical causes.
monotonicity, which requires very tight resistor matching and Also, no burn-in is required for stability. The contact resistance
tracking. The AM6012 uses conventional bipolar processing to between aluminum and silicon is more predictable than between
achieve high differential linearity and monotonicity without requiring aluminum and an amorphous thin film, and no sandwich metals are
correspondingly high linearity, or conformance to an ideal straight required to enhance or protect the contact or limit alloying. The initial
line. match between two diffused resistors is similar to that of thin film
since both are defined by photomasks and chemical etching. Since
One design approach which provides monotonicity without requiring the resistors are not trimmed or altered after fabrication, their
high linearity is the MOS switch-resistor string. This circuit is actually tracking and long-term characteristics are not degraded.
a full complement to a current-switched R-2R DAC since it is slower,
has a voltage output, and, if implemented at the 12-bit level, would
use 4096 low tolerance resistors rather than a minimum number of
DIFFERENTIAL VS INTEGRAL NONLINEARITY
high tolerance resistors as in the R-2R network. Its lack of speed
Integral nonlinearity, for the purposes of the discussion, refers to the
and density for 12 bits are its drawbacks.
“straightness” of the line drawn through the individual response
With the segmented DAC approach, the 4096 required output levels points of a data converter. Differential nonlinearity, on the other
are composed of 8 groups of 512 steps each. Each step group is hand, refers to the deviation of the spacing of the adjacent points
generated by a 9-bit DAC, and each of the segment slopes is from a 1 LSB ideal spacing. Both may be expressed as either a
determined by one of 8 equal current sources. The resistors which percentage of full-scale output or as fractional LSBs or both. The
determine monotonicity are in the 9-bit DAC. The major carry of the graphs in Figure 1 define the manner in which these parameters are
9-bit DAC is repeated in each of the 8 segments, and requires eight specified. The left graph shows a portion of the transfer curve of a
times lower initial resistor accuracy and tracking to maintain a given DAC with 1/2LSB INL and the (implied) DNL spec of 1 LSB. Below
differential nonlinearity over temperature. this is a graphic representation of the way this would appear on a
CRT screen where the AM6012 is used as a display driver. On the
The operation of the segmented DAC may be visualized by
right is a portion of the transfer curve of a DAC specified for 1/2LSB
assuming an input code of all zeroes. The first segment current IO is
INL with LSB DNL specified and the graphic display below it.
divided into 512 levels by the 9-bit multiplying DAC and fed to the
output, IOUT. As the input code increases, a new segment current is One of the characteristics of an R-2R DAC in standard form is that
selected for each 512 counts. The previous segment is fed to output any transition which causes a zero LSB change (i.e., the same
IOUT where the new step group is added to it, thus ensuring output for two different codes) will exhibit the same output each time
monotonicity independent of segment resistor values. All higher that transition occurs. The same holds true for transitions causing a
order segments feed IOUT. 2 LSB change. These two problem transitions are allowable for the
standard definition of monotonicity and also allow the device to be
With the segmented DAC approach, the precision of the 8 main
specified very tightly for INL. The major problem arising from this
resistors determines linearity only. The influence of each of these
error type is in A/D converter implementations. Inputs producing the
resistors on linearity is four times lower than that of the MSB resistor
same output are now represented by ambiguous output codes for an
in an R-2R DAC. Hence, assuming the same resistor tolerances for
identical input. Also, two LSB gaps can cause large errors at those
both, the linearity of the segmented approach would actually be
input levels (assuming 1/2LSB quantizing levels). It can be seen
higher than that of an R-2R design.
from the two figures that the DNL-specified D/A converter will yield
The step generator or 9-bit DAC is composed of a master and a much finer grained data than the INL-specified part, thus improving
slave ladder. The slave ladder generates the four least significant the ability of the A/D to resolve changes in the analog input.
bits from the remainder of the master ladder by active current

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12-Bit multiplying D/A converter AM6012

DIFFERENTIAL LINEARITY COMPARISON

+1/2LSB SEGMENT
LIMIT CHANGE
IDEAL OUTPUTS
IDEAL OUTPUTS
ACUTAL OUTPUTS
ACUTAL OUTPUTS
2LSB CHANGE ON
X011–X100

ANALOG OUT
TRANSITION SEGMENT
ANALOG OUT

CHANGE
SEGMENT
OF 12-BIT
DAC TRANSFER +2LSB –2 LSB
CURVE FOR: LIMIT LIMIT
INL = ±1/2LSB
DNL = ±1LSB
SEGMENT OF 12-BIT DAC
NO CHANGE ON
XX01–XX10 TRANSITION TRANSFER CURVE FOR:
INL = ±2LSB
–1/2LSB LIMIT DNL = ±ℑ√2LSB

0000 0010 0100 0110 1000 1010 1100 1110 0010 0010 0100 0110 1000 1010 1100 1110
0001 0011 0101 0111 1001 1011 1101 1111 0001 0011 0101 0111 1001 1011 1101 1111
DIGITAL INPUT DIGITAL INPUT

±1/2LSB INL, ±1LSB DNL ±2LSB INL, ±1LSB DNL

Figure 1. Differential Linearity Comparison

ANALOG OUTPUT CURRENTS compliance, reference amplifier negative common-mode range,

Both true and complemented output sink currents are provided negative logic input range, and negative logic threshold range;
where IO+IO=IFR. Current appears at the “true” output when a “1” is consult the various figures for guidance. For example, operation at
applied to each logic input. As the binary count increases, the sink -9V with IREF=1mA is not recommended because negative output
current at Pin 18 increases proportionally, in the fashion of a compliance would be reduced to near zero. Operation from lower
“positive logic” D/A converter. When a “0” is applied to any input bit, supplies is possible, however at least 8V total must be applied to
that current is turned off at Pin 18 and turned on at Pin 19. A insure turn-on of the internal bias network.
decreasing logic count increases IO as in a negative or inverted logic Symmetrical supplies are not required, as the AM6012 is quite
D/A converter. Both outputs may be used simultaneously. If one of insensitive to variations in supply voltage. Battery operation is
the outputs is not required, it must still be connected to ground or to feasible as no ground connection is required; however, an artificial
a point capable of sourcing IFR; do not leave an unused output pin ground may be used to insure logic swings, etc., remain between
open. acceptable limits.
Both outputs have an extremely wide voltage compliance enabling
fast direct current-to-voltage conversion through a resistor tied to
ground or other voltage source. Positive compliance is 25V above V- TEMPERATURE PERFORMANCE
and is independent of the positive supply. Negative compliance is The nonlinearity and monotonicity specifications of the AM6012 are
+10V above V-. guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is tight, typically ±10ppm/°C,
The dual outputs enable double the usual peak-to-peak load swing
with zero-scale output current and drift essentially negligible
when driving loads in quasi-differential fashion. This feature is
compared to 1/2LSB.
especially useful in cable driving, CRT deflection and in other
balanced applications such as driving center-tapped coils and The temperature coefficient of the reference resistor R14 should
transformers. match and track that of the output resistor for minimum overall
full-scale drift.

POWER SUPPLIES
The AM6012 operates over a wide range of power supply voltages SETTLING TIME
from a total supply of 20V to 36V. When operating with V- supplies The AM6012 is capable of extremely fast settling times, typically
of -10V or less, IREF≤1mA is recommended. Low reference current 250ns at IREF=1.0mA. Judicious circuit design and careful board
operation decreases power consumption and increases negative layout must be employed to obtain full performance potential during

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12-Bit multiplying D/A converter AM6012

testing and application. The logic switch design enables propagation When a DC reference is used, a reference bypass capacitor is
delays of only 25ns for each of the 12 bits. Settling time to within recommended. A 5.0V TTL logic supply is not recommended as a
LSB of the LSB is therefore 25ns, with each progressively larger bit reference. If a regulated power supply is used as a reference, R14
taking successively longer. The MSB settles in 250ns, thus should be split into two resistors with the junction bypassed to
determining the overall settling time of 250ns. Settling to 10-bit ground with a 0.1µF capacitor.
accuracy requires about 90 to 130ns. The output capacitance of the
For most applications, the tight relationship between IREF and IFS
AM6012 including the package is approximately 20pF; therefore, the
will eliminate the need for trimming IREF. If required, full-scale
output RC time constant dominates settling time if RL>500Ω.
trimming may be accomplished by adjusting the value of R14, or by
Settling time and propagation delay are relatively insensitive to logic using a potentiometer for R14.
input amplitude and rise and fall times, due to the high gain of the
logic switches. Settling time also remains essentially constant for MULTIPLYING OPERATION
IREF values down to 0.5mA, with gradual increases for lower IREF The AM6012 provides excellent multiplying performance with an
values lies in the ability to attain a given output level with lower load extremely linear relationship between IFS and IREF over a range of
resistors, thus reducing the output RC time constant. 1mA to 1µA. Monotonic operation is maintained over a typical range
Measurement of settling time requires the ability to accurately of IREF from 100µA to 1.0mA.
resolve ±2µA, therefore a 2.5kΩ load is needed to provide adequate
drive for most oscilloscopes. At IREF values of less than 0.5mA,
excessive RC damping of the output is difficult to prevent while REFERENCE AMPLIFIER COMPENSATION FOR
maintaining adequate sensitivity. However, the major carry from MULTIPLYING APPLICATIONS
011111111111 to 100000000000 provides an accurate indicator of reference applications will require the reference amplifier to be
settling time. This code change does not require the normal 6.2 time compensated using a capacitor from pin 16 to V-. The value of this
constants to settle to within ±0.1% of the final value, and thus capacitor depends on the impedance presented to Pin 14. For R14
settling times may be observed at lower values of IREF. values of 1.0, 2.5 and 5.0kΩ, minimum values of CC are 5, 12 and
AM6012 switching transients or “glitches” are very low and may be 25pF. Larger values of R14 require proportionately increased values
further reduced by small capacitive loads at the output at a minor of CC for proper phase margin (see Figure 2b).
sacrifice in settling time. For fastest response to a pulse, low values of R14 enabling small CC
Fastest operation can be obtained by using short leads, minimizing values should be used. If Pin 14 is driven by a high impedance such
output capacitance and load resistor values, and by adequate as a transistor current source, none of the above values will suffice
bypassing at the supply, reference, and VLC terminals. Supplies do and the amplifier must be heavily compensated which will decrease
not require large electrolytic bypass capacitors as the supply current overall bandwidth and slew rate. For R14=1kΩ and CC=5pF, the
drain is independent of input logic states; 0.1µF capacitors at the reference amplifier slews at 4mA/ms enabling a transition from
supply pins provide full transient protection. IREF=0 to IREF=1mA in 250ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
APPLICATIONS INFORMATION technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a cutoff
Reference Amplifier Setup (IREF=0) condition. Full-scale transition (0 to 1mA) occurs in 62.5ns
The AM6012 is a multiplying D/A converter in which the output when the equivalent impedance at Pin 14 is 800Ω and CC=0. This
current is the product of a digital number and the input reference yields a reference slew rate of 8mA/µs which is relatively
current. The reference current may be fixed or may vary from nearly independent of RIN and VIN values.
zero to +1.0mA. The full range output current is a linear function of
the reference current and is given by:
4095 LOGIC INPUTS
I FR
x 4 x (I REF)
3.999 I REF The AM6012 design incorporates a unique logic input circuit which
4096
enables direct interface to all popular logic families and provides
where IREF = I14
maximum noise immunity. This feature is made possible by the large
In positive reference applications, an external positive reference input swing capability, 40µA logic input current, and completely
voltage forces current through R14 into the VREF(+) terminal (Pin 14) adjustable logic threshold voltage. For V-=-15V, the logic inputs may
of the reference amplifier. Alternatively, a negative reference may be swing between -5 and +10V. This enables direct interface with +15V
applied to VREF(-) at Pin 15. Reference current flows from ground CMOS logic, even when the AM6012 is powered from a +5V supply.
through R14 into VREF(+) as in the positive reference case. This Minimum input logic swing and minimum logic threshold voltage are
negative reference connection has the advantage of a very high given by:
impedance presented at Pin 15. The voltage at Pin 14 is equal to
V- plus (IREF×3kΩ) plus 1.8V.
and tracks the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) is used to cancel The logic threshold may be adjusted over a wide range by placing
bias current errors (Figure 2a). an appropriate voltage at the logic threshold control pin (Pin 13,
VLC). For TTL interface, simply ground Pin 13. When interfacing
Bipolar references may be accommodated by offsetting VREF or Pin
ECL, an IREF≤1mA is recommended. For general setup of the logic
15. The negative common-mode range of the reference amplifier is
control circuit, it should be noted that Pin 13 will sink 1.1mA typical.
given by: VCM-=V- plus (IREF×3kΩ) plus 1.8V. The positive
External circuitry should be designed to accommodate this current
common-mode range is V+ less 1.23V.
(Figure 3).

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12-Bit multiplying D/A converter AM6012

VR+

AM6012
R14
RIN
14 IREF
VIN
REFERENCE
AMPLIFIER 18
IO
15 I15 IO + IO = IFS
R15 = R14 = RIN FOR ALL INPUT CODES
IO
R15 19
VIN

COMP

CC 0.1 0.1 22µF TANTALUM

20 (NOTE 5)
VR–
V– V+ V–

REFERENCE CONFIGURATION R14 R15 RIN CC IREF

Positive reference VR+ 0V N/C 0.01µF VR+/R14
Negative reference 0V VR– N/C 0.01µF –VR–/R14
Lo impedance bipolar reference VR+ 0V VIN1 (VR+/R14) + (VIN/RIN)2
Hi impedance bipolar reference VR+ VIN N/C1 (VR+ – RIN) / R143
Pulsed reference4 VR+ 0V VIN No Cap (VR+/R14) + (VIN/RIN)
NOTES:
1. The compensation capacitor is a function of the impedance seen at the +VREF input and must be at least 5pF x R14(eq) in kΩ. For R14 < 800Ω no capacitor is necessary.
2. For negative values of VIN, VR+ / R14 must be greater than –VIN max / RIN so that the amplifier is not turned off.
3. For positive values of VIN, VR+ must be greater than –VIN max so the amplifier is not turned off.
4. For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at Pin 14 should be 800Ω or less.
5. For optimum settling time, decouple V– with 20Ω and bypass with 22µF tantalum capacitor.
6. Reference current and reference resistor — there is a 1-to-4 scale factor between the reference current (IREF) and the full-scale output current (IFS).
If VREF = +10V and IFS = 4mA, the value of the R14 is:

4 x 10V
R 14

10k
R 14
R 15
4mA

a. Reference Amplifier Biasing

Reference Amplifier
Frequency Response

Minimum Size 6
Compensation Capacitor
R14 (EQ) = 2kΩ
(IFS = 4mA, IREF = 1.0mA) 4
CC = 10pF
RELATIVE OUTPUT, dB

R14(EQ) (kΩ) CC (pF) 2

10 50
5 25 0
2 10 LARGE SIGNAL = 50%
–2 MODULATION OF 4mA
1 5 FULL SCALE CURRENT
.5 0
–4
NOTE: SMALL SIGNAL = 1%
A 0.01µF capacitor is recommended for fixed –6 MODULATION OF 2mA
reference operation. FULL SCALE CURRENT
–8
.01 0.1 1.0 10
FREQUENCY MHz

b.

Figure 2.

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12-Bit multiplying D/A converter AM6012

ECL
CMOS, HTL
V+

13kΩ
20kΩ

“A” 2N3904
“A” 2N3904

2N3904
2N3904
3kΩ TO PIN 13
3kΩ TO PIN 13 39kΩ
20kΩ VLC
VLC
6.2kΩ
R 400µA

–5.2V

NOTE:
1. Set the voltage ‘A’ to the desired logic input switching threshold.
2. Allowable range of logic threshold is typically –5V to +13.5V when operating the DAC on ±15V supplies.

Figure 3. Interfacing Circuits for ECL, CMOS, HTL Logic Inputs

ACCOMMODATING BIPOLAR REFERENCE BASIC NEGATIVE REFERENCE OPERATION

VREF(+) RREF 18 IO
14
AM6012
IREF R15 IO
RREF 15
IIN VREF(–)
18 19
IO
VIN 14
RIN AM6012 NOTE:
IO V REF(*
15 )
19 I [ x 4
FS R REF

RREF sets IFS; R15 is for a bias current cancellation.

IREF > PEAK NEGATIVE SWING OF IIN

NOTE:
IREF > Peak negative swing of IIN. RECOMMENDED FULL-SCALE ADJUSTMENT
CIRCUIT
VREF(+) RREF 18 IO
14
RREF = R15
R15 VREF(+) RREF 18 IO
AM6012 14
(OPTIONAL) IO RREF = R15
VIN 15 R15
(OPTIONAL) AM6012
19 IO
VIN 15
HIGH INPUT
IMPEDANCE 19
HIGH INPUT
VREF MUST BE ABOVE PEAK POSITIVE SWING OF V IN IMPEDANCE

VREF+ MUST BE ABOVE PEAK POSITIVE SWING OF V IN

NOTE:
VREF(+) Must be above peak positive swing of VIN.

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12-Bit multiplying D/A converter AM6012

APPLICATION CIRCUITS
5,000kΩ 2.000mA

ROFF
R3 R1

R14 e c –
+10V 10kΩ NE535 VOUT
VREF(+) IO a
REF
d +
AM6012

VREF(–) IO b
R15
10kΩ B12 g
B1 R2

OPTIONAL
(SEE CODE TABLE)
V REF
R 14

1.0mA
V REF MSB LSB
R

OFF 2.0mA

MSB LSB IO IO
CODE FORMAT CONNECTIONS OUTPUT SCALE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 VOUT
(mA) (mA)
Straight binary; one a–c Positive full-scale 1 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 9.9976
polarity with true input b–g Positive full-scale – LSB 1 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9951
code, true zero output. R1 = R2 = 2.5k Zero-scale 0 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 0.0000
Unipolar
Complementary binary; a–g Positive full-scale 0 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 9.9976
one polarity with b–c Positive full-scale – LSB 0 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 9.9951
complementary input R1 = R2 = 2.5k Zero-scale 1 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 0.0000
code, true zero output.
Straight offset binary; a–c Positive full-scale 1 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 9.9976
offset half-scale, b–d Positive full-scale – LSB 1 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9927
symmetrical about zero, f–g (+) Zero-scale 1 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.0024
no true zero output. R1 = R3 = 2.5k (–) Zero-scale 0 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 –0.0024
R2 = 1.25k Negative full-scale – LSB 0 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 –9.9927
Negative full-scale 0 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 –9.9976
Symmetrical
Offset 1’s complement; offset a–c Positive full-scale 0 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 9.9976
half-scale, symmetrical b–d Positive full-scale – LSB 0 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9927
about zero, no true zero f–g (+) Zero-scale 0 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.0024
output, MSB complemented R1 = R3 = 2.5k (–) Zero-scale 1 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 –0.0024
(need inverter at B1). R2 = 1.25k Negative full-scale – LSB 1 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 –9.9927
Negative full-scale 1 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 –9.9976
Offset binary; offset half- e–a–c Positive full-scale 1 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 9.9951
scale, true zero output. b–g Positive full-scale – LSB 1 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9902
R1 = R2 = 5k + LSB 1 0 0 0 0 0 0 0 0 0 0 1 2.001 1.998 0.0049
Zero-scale 1 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.000
– LSB 0 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 –0.0049
Negative full-scale + LSB 0 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 –9.9951
Offset with Negative full-scale 0 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 –10.000
True Zero
2’s complement; offset e–a–c Positive full-scale 0 1 1 1 1 1 1 1 1 1 1 1
half-scale, true zero b–g Positive full-scale – LSB 0 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9902
output, MSB complemented R1 = R2 = 5k + 1 LSB 0 0 0 0 0 0 0 0 0 0 0 1 2.001 1.998 0.0049
(need inverter at B1). Zero-scale 0 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.000
– 1 LSB 1 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 –0.049
Negative full-scale + LSB 1 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 –9.9951
Negative full-scale 1 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 –10.000

Figure 4. AM6012 Logic Inputs

ADDITIONAL CODE MODIFICATIONS

1. Any of the offset binary codes may be complemented by
reversing the output terminal pair.

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Philips Semiconductors Linear Products Product specification

12-Bit multiplying D/A converter AM6012

APPLICATION CIRCUITS
+120VDC

60V COMMON
MODE LEVEL

CRT

“X” INPUT “Y” INPUT

IO IO

AM6012 –15V AM6012

–15V

IO
IO

NOTES:
1. Full differential drive lowers power supply voltage.
2. Eliminates inverting amplifiers and transformers.
3. Independent beam centering controls.

Figure 5. CRT Display Driver

CONVERSION TIME vs ACCURACY

1.25

SERIAL 1.00
DATA OUT (WORST CASE)
ACCURACY, LSB

AM6012
WITH
E S CC DO 0.75 NE529
2504 SAR D
CLOCK CP Q11 (NAT’L, AMD) AM6012
O0
0.50 WITH
LSB NE529
(TYP)

0.25
+15V

ANALOG IN
(0–10V) 0.00
VREF
100 200 300 400 500 600 700 800
CONVERSION TIME PER TRIAL, ns
10.000kΩ 2.5kΩ
+10V 5.000k MSB
REF 5.000k
MSB LSB
IO
AM6012 NE529
IO
COMP CONVERSION WORST
TIME (ns) TYP CASE
0.001 0.001
0.1µF µF µF
10.000kΩ SAR 33 55
0.01
µF 1µF 1µF NE529 100 150

TOTAL 383ns 705ns

X 13 5.0µs 9.1µs
V(–0 V(+)

Figure 6. 12-Bit High-Speed A/D Converter

August 31, 1994 785

Philips Semiconductors Linear Products Product specification

12-Bit multiplying D/A converter AM6012

APPLICATION CIRCUITS

OE
7 MSB

4
µP LS373
BUS 3

1 6012

E2

E1

EB LSB
D3A Q3A D3B Q3B

D2A Q2A D2B Q2B

1/2LS100 1/2LS100
D1A Q1A D1B Q1B

D0A Q0A D0B Q0B

EA

a. Interface With 8-Bit Microprocessor Bus

E1

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
E2

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ DB0–3 DB4–11

a. Timing Sequence
NOTE:
Data remains on inputs of DAC until updated by E2 pulse. Timing will depend on processor used.

Figure 7.

August 31, 1994 786