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Jameco Part Number 52708INTEL

 8254
PROGRAMMABLE INTERVAL TIMER
Y Compatible with All Intel and Most Y Six Programmable Counter Modes
Other Microprocessors Y Three Independent 16-Bit Counters
Y Handles Inputs from DC to 10 MHz Y Binary or BCD Counting
Ð 8 MHz 8254
Ð 10 MHz 8254-2 Y Single a 5V Supply
Y Status Read-Back Command Y Available in EXPRESS
Ð Standard Temperature Range

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcom-
puter system design. It provides three independent 16-bit counters, each capable of handling clock inputs up
to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.

The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

231164 – 2
Figure 2. Pin Configuration

231164 – 1
Figure 1. 8254 Block Diagram

September 1993 Order Number: 231164-005

8254

Table 1. Pin Description

Pin
Symbol Type Name and Function
No.
D7 –D0 1–8 I/O DATA: Bi-directional three state data bus lines, connected to system
data bus.
CLK 0 9 I CLOCK 0: Clock input of Counter 0.
OUT 0 10 O OUTPUT 0: Output of Counter 0.
GATE 0 11 I GATE 0: Gate input of Counter 0.
GND 12 GROUND: Power supply connection.
VCC 24 POWER: a 5V power supply connection.
WR 23 I WRITE CONTROL: This input is low during CPU write operations.
RD 22 I READ CONTROL: This input is low during CPU read operations.
CS 21 I CHIP SELECT: A low on this input enables the 8254 to respond to
RD and WR signals. RD and WR are ignored otherwise.
A1, A0 20–19 I ADDRESS: Used to select one of the three Counters or the Control
Word Register for read or write operations. Normally connected to
the system address bus.
A1 A0 Selects
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
CLK 2 18 I CLOCK 2: Clock input of Counter 2.
OUT 2 17 O OUT 2: Output of Counter 2.
GATE 2 16 I GATE 2: Gate input of Counter 2.
CLK 1 15 I CLOCK 1: Clock input of Counter 1.
GATE 1 14 I GATE 1: Gate input of Counter 1.
OUT 1 13 O OUT 1: Output of Counter 1.

FUNCTIONAL DESCRIPTION Some of the other counter/timer functions common

to microcomputers which can be implemented with
the 8254 are:
General # Real time clock
The 8254 is a programmable interval timer/counter # Event-counter
designed for use with Intel microcomputer systems. # Digital one-shot
It is a general purpose, multi-timing element that can # Programmable rate generator
be treated as an array of I/O ports in the system
software. # Square wave generator
# Binary rate multiplier
The 8254 solves one of the most common problems # Complex waveform generator
in any microcomputer system, the generation of ac-
curate time delays under software control. Instead of # Complex motor controller
setting up timing loops in software, the programmer
configures the 8254 to match his requirements and
programs one of the counters for the desired delay. Block Diagram
After the desired delay, the 8254 will interrupt the
CPU. Software overhead is minimal and variable DATA BUS BUFFER
length delays can easily be accommodated.
This 3-state, bi-directional, 8-bit buffer is used to in-
terface the 8254 to the system bus (see Figure 3).

2
 8254

231164 – 3

Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions

READ/WRITE LOGIC COUNTER 0, COUNTER 1, COUNTER 2

The Read/Write Logic accepts inputs from the sys- These three functional blocks are identical in opera-
tem bus and generates control signals for the other tion, so only a single Counter will be described. The
functional blocks of the 8254. A1 and A0 select one internal block diagram of a single counter is shown
of the three counters or the Control Word Register in Figure 5.
to be read from/written into. A ‘‘low’’ on the RD in-
put tells the 8254 that the CPU is reading one of the The Counters are fully independent. Each Counter
counters. A ‘‘low’’ on the WR input tells the 8254 may operate in a different Mode.
that the CPU is writing either a Control Word or an
initial count. Both RD and WR are qualified by CS; The Control Word Register is shown in the figure; it
RD and WR are ignored unless the 8254 has been is not part of the Counter itself, but its contents de-
selected by holding CS low. termine how the Counter operates.

The status register, shown in Figure 5, when

CONTROL WORD REGISTER latched, contains the current contents of the Control
The Control Word Register (see Figure 4) is selected Word Register and status of the output and null
by the Read/Write Logic when A1,A0 e 11. If the count flag. (See detailed explanation of the Read-
Back command.)
CPU then does a write operation to the 8254, the
data is stored in the Control Word Register and is
The actual counter is labelled CE (for ‘‘Counting Ele-
interpreted as a Control Word used to define the
operation of the Counters. ment’’). It is a 16-bit presettable synchronous down
counter.
The Control Word Register can only be written to;
OLM and OLL are two 8-bit latches. OL stands for
status information is available with the Read-Back
Command. ‘‘Output Latch’’; the subscripts M and L stand for
‘‘Most significant byte’’ and ‘‘Least significant byte’’

3
8254

231164 – 4

Figure 4. Block Diagram Showing Control Word Register and Counter Functions

231164 – 5

Figure 5. Internal Block Diagram of a Counter

4
 8254

respectively. Both are normally referred to as one other peripherals of the family. It is treated by the
unit and called just OL. These latches normally ‘‘fol- system’s software as an array of peripheral I/O
low’’ the CE, but if a suitable Counter Latch Com- ports; three are counters and the fourth is a control
mand is sent to the 8254, the latches ‘‘latch’’ the register for MODE programming.
present count until read by the CPU and then return
to ‘‘following’’ the CE. One latch at a time is enabled Basically, the select inputs A0,A1 connect to the A0,
by the counter’s Control Logic to drive the internal A1 address bus signals of the CPU. The CS can be
bus. This is how the 16-bit Counter communicates derived directly from the address bus using a linear
over the 8-bit internal bus. Note that the CE itself select method. Or it can be connected to the output
cannot be read; whenever you read the count, it is of a decoder, such as an Intel 8205 for larger sys-
the OL that is being read. tems.

Similarly, there are two 8-bit registers called CRM

and CRL (for ‘‘Count Register’’). Both are normally OPERATIONAL DESCRIPTION
referred to as one unit and called just CR. When a
new count is written to the Counter, the count is
stored in the CR and later transferred to the CE. The General
Control Logic allows one register at a time to be
loaded from the internal bus. Both bytes are trans- After power-up, the state of the 8254 is undefined.
ferred to the CE simultaneously. CRM and CRL are The Mode, count value, and output of all Counters
cleared when the Counter is programmed. In this are undefined.
way, if the Counter has been programmed for one
byte counts (either most significant byte only or least How each Counter operates is determined when it is
significant byte only) the other byte will be zero. programmed. Each Counter must be programmed
Note that the CE cannot be written into; whenever a before it can be used. Unused counters need not be
count is written, it is written into the CR. programmed.

The Control Logic is also shown in the diagram.

CLK n, GATE n, and OUT n are all connected to the Programming the 8254
outside world through the Control Logic.
Counters are programmed by writing a Control Word
and then an initial count.
8254 SYSTEM INTERFACE The Control Words are written into the Control Word
The 8254 is a component of the Intel Microcomputer Register, which is selected when A1,A0 e 11. The
Systems and interfaces in the same manner as all Control Word itself specifies which Counter is being
programmed.

231164 – 6

Figure 6. 8254 System Interface

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8254

Control Word Format

A1,A0 e 11 CS e 0 RD e 1 WR e 0

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

SCÐSelect Counter MÐMode

SC1 SC0 M2 M1 M0
0 0 Select Counter 0 0 0 0 Mode 0
0 1 Select Counter 1 0 0 1 Mode 1
1 0 Select Counter 2 X 1 0 Mode 2
1 1 Read-Back Command X 1 1 Mode 3
(see Read Operations)
1 0 0 Mode 4
1 0 1 Mode 5
RWÐRead/Write
RW1 RW0
BCD
0 0 Counter Latch Command (see Read
Operations) 0 Binary Counter 16-bits
0 1 Read/Write least significant byte only 1 Binary Coded Decimal (BCD) Counter
(4 Decades)
1 0 Read/Write most significant byte only
1 1 Read/Write least significant byte first,
then most significant byte
NOTE:
Don’t care bits (X) should be 0 to insure compatibility with future Intel products.

Figure 7. Control Word Format

By contrast, initial counts are written into the Coun- Since the Control Word Register and the three
ters, not the Control Word Register. The A1,A0 in- Counters have separate addresses (selected by the
puts are used to select the Counter to be written A1,A0 inputs), and each Control Word specifies the
into. The format of the initial count is determined by Counter it applies to (SC0,SC1 bits), no special in-
the Control Word used. struction sequence is required. Any programming
sequence that follows the conventions in Figure 7 is
acceptable.
Write Operations
A new initial count may be written to a Counter at
The programming procedure for the 8254 is very any time without affecting the Counter’s pro-
flexible. Only two conventions need to be remem- grammed Mode in any way. Counting will be affected
bered: as described in the Mode definitions. The new count
1) For each Counter, the Control Word must be writ- must follow the programmed count format.
ten before the initial count is written.
If a Counter is programmed to read/write two-byte
2) The initial count must follow the count format counts, the following precaution applies: A program
specified in the Control Word (least significant must not transfer control between writing the first
byte only, most significant byte only, or least sig- and second byte to another routine which also writes
nificant byte and then most significant byte). into that same Counter. Otherwise, the Counter will
be loaded with an incorrect count.

6
 8254

A1 A0 A1 A0
Control WordÐCounter 0 1 1 Control WordÐCounter 2 1 1
LSB of countÐCounter 0 0 0 Control WordÐCounter 1 1 1
MSB of countÐCounter 0 0 0 Control WordÐCounter 0 1 1
Control WordÐCounter 1 1 1 LSB of countÐCounter 2 1 0
LSB of countÐCounter 1 0 1 MSB of countÐCounter 2 1 0
MSB of countÐCounter 1 0 1 LSB of countÐCounter 1 0 1
Control WordÐCounter 2 1 1 MSB of countÐCounter 1 0 1
LSB of countÐCounter 2 1 0 LSB of countÐCounter 0 0 0
MSB of countÐCounter 2 1 0 MSB of countÐCounter 0 0 0

A1 A0 A1 A0
Control WordÐCounter 0 1 1 Control WordÐCounter 1 1 1
Control WordÐCounter 1 1 1 Control WordÐCounter 0 1 1
Control WordÐCounter 2 1 1 LSB of countÐCounter 1 0 1
LSB of countÐCounter 2 1 0 Control WordÐCounter 2 1 1
LSB of countÐCounter 1 0 1 LSB of countÐCounter 0 0 0
LSB of countÐCounter 0 0 0 MSB of countÐCounter 1 0 1
MSB of countÐCounter 0 0 0 LSB of countÐCounter 2 1 0
MSB of countÐCounter 1 0 1 MSB of countÐCounter 0 0 0
MSB of countÐCounter 2 1 0 MSB of countÐCounter 2 1 0
NOTE:
In all four examples, all Counters are programmed to read/write two-byte counts. These are only four of many possible
programming sequences.

Figure 8. A Few Possible Programming Sequences

Read Operations A1,A0 e 11; CS e 0; RD e 1; WR e 0

It is often desirable to read the value of a Counter D7 D6 D5 D4 D3 D2 D1 D0
without disturbing the count in progress. This is easi-
ly done in the 8254. SC1 SC0 0 0 X X X X

There are three possible methods for reading the

counters: a simple read operation, the Counter SC1,SC0Ðspecify counter to be latched
Latch Command, and the Read-Back Command. SC1 SC0 Counter
Each is explained below. The first method is to per-
form a simple read operation. To read the Counter, 0 0 0
which is selected with the A1, A0 inputs, the CLK 0 1 1
input of the selected Counter must be inhibited by 1 0 2
using either the GATE input or external logic. Other- 1 1 Read-Back Command
wise, the count may be in the process of changing
when it is read, giving an undefined result.
D5,D4Ð00 designates Counter Latch Command

COUNTER LATCH COMMAND XÐdon’t care

The second method uses the ‘‘Counter Latch Com- NOTE:
mand’’. Like a Control Word, this command is written Don’t care bits (X) should be 0 to insure compatibility
to the Control Word Register, which is selected with future Intel products.
when A1,A0 e 11. Also like a Control Word, the Figure 9. Counter Latching Command Format
SC0, SC1 bits select one of the three Counters, but
two other bits, D5 and D4, distinguish this command
from a Control Word.

7
8254

The selected Counter’s output latch (OL) latches the A0, A1 e 11 CS e 0 RD e 1 WR e 0

count at the time the Counter Latch Command is
received. This count is held in the latch until it is read D7 D6 D5 D4 D3 D2 D1 D0
by the CPU (or until the Counter is reprogrammed). 1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0
The count is then unlatched automatically and the
OL returns to ‘‘following’’ the counting element (CE). D5: 0 e Latch count of selected counter(s)
This allows reading the contents of the Counters D4: 0 e Latch status of selected counters(s)
‘‘on the fly’’ without affecting counting in progress. D3: 1 e Select Counter 2
Multiple Counter Latch Commands may be used to D2: 1 e Select Counter 1
latch more than one Counter. Each latched Coun- D1: 1 e Select Counter 0
ter’s OL holds its count until it is read. Counter Latch D0: Reserved for future expansion; Must be 0
Commands do not affect the programmed Mode of
Figure 10. Read-Back Command Format
the Counter in any way.
The read-back command may be used to latch multi-
If a Counter is latched and then, some time later,
ple counter output latches (OL) by setting the
latched again before the count is read, the second
COUNT bit D5 e 0 and selecting the desired coun-
Counter Latch Command is ignored. The count read
ter(s). This single command is functionally equiva-
will be the count at the time the first Counter Latch
lent to several counter latch commands, one for
Command was issued.
each counter latched. Each counter’s latched count
is held until it is read (or the counter is repro-
With either method, the count must be read accord-
grammed). The counter is automatically unlatched
ing to the programmed format; specifically, if the
when read, but other counters remain latched until
Counter is programmed for two byte counts, two
they are read. If multiple count read-back commands
bytes must be read. The two bytes do not have to be
are issued to the same counter without reading the
read one right after the other; read or write or pro-
count, all but the first are ignored; i.e., the count
gramming operations of other Counters may be in-
which will be read is the count at the time the first
serted between them.
read-back command was issued.
Another feature of the 8254 is that reads and writes
The read-back command may also be used to latch
of the same Counter may be interleaved; for exam-
status information of selected counter(s) by setting
ple, if the Counter is programmed for two byte
STATUS bit D4 e 0. Status must be latched to be
counts, the following sequence is valid.
read; status of a counter is accessed by a read from
1) Read least significant byte. that counter.
2) Write new least significant byte.
The counter status format is shown in Figure 11. Bits
3) Read most significant byte.
D5 through D0 contain the counter’s programmed
4) Write new most significant byte. Mode exactly as written in the last Mode Control
Word. OUTPUT bit D7 contains the current state of
If a Counter is programmed to read/write two-byte the OUT pin. This allows the user to monitor the
counts, the following precaution applies: A program counter’s output via software, possibly eliminating
must not transfer control between reading the first some hardware from a system.
and second byte to another routine which also reads
from that same Counter. Otherwise, an incorrect
count will be read. D7 D6 D5 D4 D3 D2 D1 D0
Null
Output RW1 RW0 M2 M1 M0 BCD
READ-BACK COMMAND Count
The third method uses the Read-Back Command. D7 1 e OUT Pin is 1
This command allows the user to check the count 0 e OUT Pin is 0
value, programmed Mode, and current states of the D6 1 e Null Count
OUT pin and Null Count flag of the selected coun- 0 e Count available for reading
ter(s).
D5 –D0 Counter programmed mode (see Figure
The command is written into the Control Word Reg- 7)
ister and has the format shown in Figure 10. The
Figure 11. Status Byte
command applies to the counters selected by set-
ting their corresponding bits D3, D2, D1 e 1.

8
 8254

NULL COUNT bit D6 indicates when the last count COUNT and STATUS bits D5,D4 e 0. This is func-
written to the counter register (CR) has been loaded tionally the same as issuing two separate read-back
into the counting element (CE). The exact time this commands at once, and the above discussions ap-
happens depends on the Mode of the counter and is ply here also. Specifically, if multiple count and/or
described in the Mode Definitions, but until the count status read-back commands are issued to the same
is loaded into the counting element (CE), it can’t be counter(s) without any intervening reads, all but the
read from the counter. If the count is latched or read first are ignored. This is illustrated in Figure 13.
before this time, the count value will not reflect the
new count just written. The operation of Null Count If both count and status of a counter are latched, the
is shown in Figure 12. first read operation of that counter will return latched
status, regardless of which was latched first. The
next one or two reads (depending on whether the
This Action Causes counter is programmed for one or two type counts)
A. Write to the control word register;(1) Null Count e 1 return latched count. Subsequent reads return un-
B. Write to the count register (CR);(2) Null Count e 1 latched count.
C. New Count is loaded into Null Count e 0
CE (CR x CE);
CS RD WR A1 A0
NOTE:
1. Only the counter specified by the control word will 0 1 0 0 0 Write into Counter 0
have its Null Count set to 1. Null count bits of other
counters are unaffected. 0 1 0 0 1 Write into Counter 1
2. If the counter is programmed for two-byte counts 0 1 0 1 0 Write into Counter 2
(least significant byte then most significant byte) Null
Count goes to 1 when the second byte is written. 0 1 0 1 1 Write Control Word
Figure 12. Null Count Operation 0 0 1 0 0 Read from Counter 0
0 0 1 0 1 Read from Counter 1
If multiple status latch operations of the counter(s)
are performed without reading the status, all but the 0 0 1 1 0 Read from Counter 2
first are ignored; i.e., the status that will be read is
the status of the counter at the time the first status 0 0 1 1 1 No-Operation (3-State)
read-back command was issued. 1 X X X X No-Operation (3-State)

Both count and status of the selected counter(s) 0 1 1 X X No-Operation (3-State)

may be latched simultaneously by setting both Figure 14. Read/Write Operations Summary

Command
Description Result
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 0 1 0 Read back count and status of Count and status latched
Counter 0 for Counter 0
1 1 1 0 0 1 0 0 Read back status of Counter 1 Status latched for Counter 1
1 1 1 0 1 1 0 0 Read back status of Counters 2, 1 Status latched for Counter
2, but not Counter 1
1 1 0 1 1 0 0 0 Read back count of Counter 2 Count latched for Counter 2
1 1 0 0 0 1 0 0 Read back count and status of Count latched for Counter 1,
Counter 1 but not status
1 1 1 0 0 0 1 0 Read back status of Counter 1 Command ignored, status
already latched for Counter 1

Figure 13. Read-Back Command Example

9
8254

Mode Definitions OUT will then go high and remain high until the CLK
pulse after the next trigger.
The following are defined for use in describing the
operation of the 8254. After writing the Control Word and initial count, the
CLK Pulse: a rising edge, then a falling edge, in Counter is armed. A trigger results in loading the
that order, of a Counter’s CLK in- Counter and setting OUT low on the next CLK pulse,
put. thus starting the one-shot pulse. An initial count of N
will result in a one-shot pulse N CLK cycles in dura-
Trigger: a rising edge of a Counter’s GATE tion. The one-shot is retriggerable, hence OUT will
input. remain low for N CLK pulses after any trigger. The
Counter loading: the transfer of a count from the CR one-shot pulse can be repeated without rewriting the
to the CE (refer to the ‘‘Functional same count into the counter. GATE has no effect on
Description’’) OUT.

If a new count is written to the Counter during a one-

MODE 0: INTERRUPT ON TERMINAL COUNT shot pulse, the current one-shot is not affected un-
less the counter is retriggered. In that case, the
Mode 0 is typically used for event counting. After the
Counter is loaded with the new count and the one-
Control Word is written, OUT is initially low, and will
shot pulse continues until the new count expires.
remain low until the Counter reaches zero. OUT then
goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Coun- MODE 2: RATE GENERATOR
ter.
This Mode functions like a divide-by-N counter. It is
GATE e 1 enables counting; GATE e 0 disables typically used to generate a Real Time Clock inter-
counting. GATE has no effect on OUT. rupt. OUT will initially be high. When the initial count
has decremented to 1, OUT goes low for one CLK
After the Control Word and initial count are written to pulse. OUT then goes high again, the Counter re-
a Counter, the initial count will be loaded on the next loads the initial count and the process is repeated.
CLK pulse. This CLK pulse does not decrement the Mode 2 is periodic; the same sequence is repeated
count, so for an initial count of N, OUT does not go indefinitely. For an initial count of N, the sequence
high until N a 1 CLK pulses after the initial count is repeats every N CLK cycles.
written.
GATE e 1 enables counting; GATE e 0 disables
If a new count is written to the Counter, it will be counting. If GATE goes low during an output pulse,
loaded on the next CLK pulse and counting will con- OUT is set high immediately. A trigger reloads the
tinue from the new count. If a two-byte count is writ- Counter with the initial count on the next CLK pulse;
ten, the following happens: OUT goes low N CLK pulses after the trigger. Thus
the GATE input can be used to synchronize the
1) Writing the first byte disables counting. OUT is set
Counter.
low immediately (no clock pulse required)
2) Writing the second byte allows the new count to After writing a Control Word and initial count, the
be loaded on the next CLK pulse. Counter will be loaded on the next CLK pulse. OUT
goes low N CLK Pulses after the initial count is writ-
This allows the counting sequence to be synchroniz- ten. This allows the Counter to be synchronized by
ed by software. Again, OUT does not go high until software also.
N a 1 CLK pulses after the new count of N is written.
Writing a new count while counting does not affect
If an initial count is written while GATE e 0, it will the current counting sequence. If a trigger is re-
still be loaded on the next CLK pulse. When GATE ceived after writing a new count but before the end
goes high, OUT will go high N CLK pulses later; no of the current period, the Counter will be loaded with
CLK pulse is needed to load the Counter as this has the new count on the next CLK pulse and counting
already been done. will continue from the new count. Otherwise, the
new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
MODE 1: HARDWARE RETRIGGERABLE
ONE-SHOT
MODE 3: SQUARE WAVE MODE
OUT will be initially high. OUT will go low on the CLK
pulse following a trigger to begin the one-shot pulse, Mode 3 is typically used for Baud rate generation.
and will remain low until the Counter reaches zero. Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the

10
 8254

231164 – 7

NOTE:
The following conventions apply to all mode timing diagrams:
1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for ‘‘Control Word’’; CW e 10 means a control word of 10 HEX is written to the counter.
4. LSB stands for ‘‘Least Significant Byte’’ of count.
5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the
most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read.
N stands for an undefined count.
Vertical lines show transitions between count values.

Figure 15. Mode 0

11
8254

231164 – 8

Figure 16. Mode 1

initial count has expired, OUT goes low for the re- After writing a Control Word and initial count, the
mainder of the count. Mode 3 is periodic; the se- Counter will be loaded on the next CLK pulse. This
quence above is repeated indefinitely. An initial allows the Counter to be synchronized by software
count of N results in a square wave with a period of also.
N CLK cycles.
Writing a new count while counting does not affect
GATE e 1 enables counting; GATE e 0 disables the current counting sequence. If a trigger is re-
counting. If GATE goes low while OUT is low, OUT is ceived after writing a new count but before the end
set high immediately; no CLK pulse is required. A of the current half-cycle of the square wave, the
trigger reloads the Counter with the initial count on Counter will be loaded with the new count on the
the next CLK pulse. Thus the GATE input can be next CLK pulse and counting will continue from the
used to synchronize the Counter.

12
 8254

231164 – 9

NOTE:
A GATE transition should not occur one clock prior to terminal count.

Figure 17. Mode 2

new count. Otherwise, the new count will be loaded Odd counts: OUT is initially high. The initial count
at the end of the current half-cycle. minus one (an even number) is loaded on one CLK
pulse and then is decremented by two on succeed-
Mode 3 is implemented as follows: ing CLK pulses. One CLK pulse after the count ex-
pires, OUT goes low and the Counter is reloaded
Even counts: OUT is initially high. The initial count is with the initial count minus one. Succeeding CLK
loaded on one CLK pulse and then is decremented pulses decrement the count by two. When the count
by two on succeeding CLK pulses. When the count expires, OUT goes high again and the Counter is
expires OUT changes value and the Counter is re- reloaded with the initial count minus one. The above
loaded with the initial count. The above process is process is repeated indefinitely. So for odd counts,
repeated indefinitely. OUT will be high for (N a 1)/2 counts and low for
(N b 1)/2 counts.

13
8254

231164 – 10

NOTE:
A GATE transition should not occur one clock prior to terminal count.

Figure 18. Mode 3

14
 8254

MODE 4: SOFTWARE TRIGGERED STROBE initial count of N, OUT does not strobe low until N a
1 CLK pulses after the initial count is written.
OUT will be initially high. When the initial count ex-
pires, OUT will go low for one CLK pulse and then If a new count is written during counting, it will be
go high again. The counting sequence is ‘‘triggered’’ loaded on the next CLK pulse and counting will con-
by writing the initial count. tinue from the new count. If a two-byte count is writ-
ten, the following happens:
GATE e 1 enables counting; GATE e 0 disables 1) Writing the first byte has no effect on counting.
counting. GATE has no effect on OUT.
2) Writing the second byte allows the new count to
After writing a Control Word and initial count, the be loaded on the next CLK pulse.
Counter will be loaded on the next CLK pulse. This
CLK pulse does not decrement the count, so for an This allows the sequence to be ‘‘retriggered’’ by
software. OUT strobes low N a 1 CLK pulses after
the new count of N is written.

231164 – 11

Figure 19. Mode 4

15
8254

MODE 5: HARDWARE TRIGGERED STROBE A trigger results in the Counter being loaded with the
(RETRIGGERABLE) initial count on the next CLK pulse. The counting
sequence is retriggerable. OUT will not strobe low
OUT will initially be high. Counting is triggered by a for N a 1 CLK pulses after any trigger. GATE has
rising edge of GATE. When the initial count has ex- no effect on OUT.
pired, OUT will go low for one CLK pulse and then
go high again. If a new count is written during counting, the current
counting sequence will not be affected. If a trigger
After writing the Control Word and initial count, the occurs after the new count is written but before the
counter will not be loaded until the CLK pulse after a current count expires, the Counter will be loaded
trigger. This CLK pulse does not decrement the with the new count on the next CLK pulse and
count, so for an initial count of N, OUT does not counting will continue from there.
strobe low until N a 1 CLK pulses after a trigger.

231164 – 12

Figure 20. Mode 5

16
 8254

Signal Low Operation Common to All Modes

Status Or Going Rising High
Modes Low
PROGRAMMING
0 Disables ÐÐ Enables
Counting Counting When a Control Word is written to a Counter, all
Control Logic is immediately reset and OUT goes to
1 ÐÐ 1) Initiates ÐÐ
a known initial state; no CLK pulses are required for
Counting
this.
2) Resets Output
after Next
Clock GATE
2 1) Disables
Counting Initiates Enables The GATE input is always sampled on the rising
2) Sets Output Counting Counting edge of CLK. In Modes 0, 2, 3, and 4 the GATE input
Immediately is level sensitive, and the logic level is sampled on
High the rising edge of CLK. In Modes 1, 2, 3, and 5 the
GATE input is rising-edge sensitive. In these Modes,
3 1) Disables a rising edge of GATE (trigger) sets an edge-sensi-
Counting Initiates Enables tive flip-flop in the Counter. This flip-flop is then sam-
2) Sets Output Counting Counting pled on the next rising edge of CLK; the flip-flop is
Immediately reset immediately after it is sampled. In this way, a
High trigger will be detected no matter when it occursÐa
4 Disables ÐÐ Enables high logic level does not have to be maintained until
Counting Counting the next rising edge of CLK. Note that in Modes 2
5 ÐÐ Initiates ÐÐ and 3, the GATE input is both edge- and level-sensi-
Counting tive. In Modes 2 and 3, if a CLK source other than
the system clock is used, GATE should be pulsed
Figure 21. Gate Pin Operations Summary immediately following WR of a new count value.

Min Max COUNTER

Mode
Count Count New counts are loaded and Counters are decre-
0 1 0 mented on the falling edge of CLK.
1 1 0
2 2 0 The largest possible initial count is 0; this is equiva-
lent to 216 for binary counting and 104 for BCD
3 2 0
counting.
4 1 0
5 1 0 The Counter does not stop when it reaches zero. In
Modes 0, 1, 4, and 5 the Counter ‘‘wraps around’’ to
NOTE: the highest count, either FFFF hex for binary count-
0 is equivalent to 216 for binary counting and 104 for ing or 9999 for BCD counting, and continues count-
BCD counting.
ing. Modes 2 and 3 are periodic; the Counter reloads
Figure 22. Minimum and Maximum Initial Counts itself with the initial count and continues counting
from there.

17
8254

ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias ÀÀÀÀÀÀ0§ C to 70§ C
*WARNING: Stressing the device beyond the ‘‘Absolute
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Maximum Ratings’’ may cause permanent damage.
Voltage on Any Pin with These are stress ratings only. Operation beyond the
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7V ‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W may affect device reliability.

D.C. CHARACTERISTICS TA e 0§ C to 70§ C, VCC e 5V g 10%

Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage b 0.5 0.8 V
VIH Input High Voltage 2.0 VCC a 0.5V V
VOL Output Low Voltage 0.45 V IOL e 2.0 mA
VOH Output High Voltage 2.4 V IOH e b 400 mA
IIL Input Load Current g 10 mA VIN e VCC to 0V
IOFL Output Float Leakage g 10 mA VOUT e VCC to 0.45V
ICC VCC Supply Current 170 mA
CIN Input Capacitance 10 pF fc e 1 MHz
CI/0 I/O Capacitance 20 pF Unmeasured pins
returned to VSS(4)

A.C. CHARACTERISTICS TA e 0§ C to 70§ C, VCC e 5V g 10%, GND e 0V

Bus Parameters(1)

READ CYCLE
8254 8254-2
Symbol Parameter Unit
Min Max Min Max
tAR Address Stable Before RD v 45 30 ns
tSR CS Stable Before RD v 0 0 ns
tRA Address Hold Time After RD u 0 0 ns
tRR RD Pulse Width 150 95 ns
tRD Data Delay from RD v 120 85 ns
tAD Data Delay from Address 220 185 ns
tDF RD u to Data Floating 5 90 5 65 ns
tRV Command Recovery Time 200 165 ns

NOTE:
1. AC timings measured at VOH e 2.0V, VOL e 0.8V.

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 8254

A.C. CHARACTERISTICS TA e 0§ C to 70§ C, VCC e 5V g 10%, GND e 0V (Continued)

WRITE CYCLE
8254 8254-2
Symbol Parameter Unit
Min Max Min Max
tAW Address Stable Before WR v 0 0 ns
tSW CS Stable Before WR v 0 0 ns
tWA Address Hold Time After WR v 0 0 ns
tWW WR Pulse Width 150 95 ns
tDW Data Setup Time Before WR u 120 95 ns
tWD Data Hold Time After WR u 0 0 ns
tRV Command Recovery Time 200 165 ns

CLOCK AND GATE

8254 8254-2
Symbol Parameter Unit
Min Max Min Max
tCLK Clock Period 125 DC 100 DC ns
tPWH High Pulse Width 60(3) 30(3) ns
tPWL Low Pulse Width 60(3) 50(3) ns
tR Clock Rise Time 25 25 ns
tF Clock Fall Time 25 25 ns
tGW Gate Width High 50 50 ns
tGL Gate Width Low 50 50 ns
tGS Gate Setup Time to CLK u 50 40 ns
tGH Gate Setup Time After CLK u 50(2) 50(2) ns
tOD Output Delay from CLK v 150 100 ns
tODG Output Delay from Gatev 120 100 ns
tWC CLK Delay for Loading v 0 55 0 55 ns
tWG Gate Delay for Sampling b5 50 b5 40 ns
tWO OUT Delay from Mode Write 260 240 ns
tCL CLK Set Up for Count Latch b 40 45 b 40 40 ns

NOTES:
2. In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 8254-2) of
the rising clock edge may not be detected.
3. Low-going glitches that violate tPWH, tPWL may cause errors requiring counter reprogramming.
4. Sampled, not 100% tested. TA e 25§ C.
5. If CLK present at TWC min then Count equals N a 2 CLK pulses, TWC max equals Count N a 1 CLK pulse. TWC min to
TWC max, count will be either N a 1 or N a 2 CLK pulses.
6. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWG
max Counter will be triggered.
7. If CLK present when writing a Counter Latch or ReadBack Command, at TCL min CLK will be reflected in count value
latched, at TCL max CLK will not be reflected in the count value latched.

19
8254

WAVEFORMS

WRITE

231164 – 13

READ

231164 – 14

20
 8254

WAVEFORMS (Continued)

RECOVERY

231164 – 15

CLOCK AND GATE

231164 – 16
*Last byte of count being written.

A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT

231164 – 17
A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V
for a Logic ‘‘0.’’ Timing measurements are made at 2.0V for a
Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. 231164 – 18
CL e 150 pF
CL Includes Jig Capacitance

REVISION SUMMARY
The following list represents the key differences be-
tween Rev. 004 and Rev. 005 of the 8254 Data
Sheet.
1. References to and specifications for the 5 MHz
8254-5 are removed. Only the 8 MHz 8254 and
the 10 MHz 8254-2 remain in production.

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