DS9186B 00
DS9186B 00
DS9186B 00
RT9187B
SOT-23-5
Marking Information
04= : Product Code
04=DNN DNN : Date Code
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
1 VIN VOUT 5
VIN VOUT
CIN COUT
RT9187B
2.2µF R1 2.2µF
4
ADJ
Chip Enable 3 EN
R2
GND
2
VOUT = 0.8 x ( 1+
R1 ) Volts
R2
Ω to maintain regulation.
Note : The value of R2 should be less than 80kΩ
-
VREF +
VOUT
Current Limit
GND
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Electrical Characteristics
(VIN = VOUT + 1V, VEN = VIN, CIN = COUT = 2.2μF (Ceramic), TA = 25°C, unless otherwise specified)
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
300 300
200 200
100 100
0 0
-50 -25 0 25 50 75 100 125 3 3.5 4 4.5 5 5.5
Temperature (°C) Input Voltage (V)
4
Output Current (A)
90 TJ = 25°C 3
60 TJ = 125°C 1
TJ = −40°C 0
30
0
0.0 0.1 0.2 0.3 0.4 0.5 Time (1ms/Div)
Load Current (A)
0 0
4 2
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
4.3
VIN (V) IOUT
3.3 (200mA/Div)
10
VOUT
VOUT (mV) 0 (50mV/Div)
-10
VIN = 3.3V to 4.3V, ILOAD : 300mA VIN = 5V, IOUT = 10mA to 0.3A
-20 10
PSRR (dB)
Stable CCOUT
1
-40 Stable Range
ofStable
0.1
ILOAD = 280mA
Regionof
-60
Region
-80
0.001
10
10 100
100 1k 100010k 10000
100k 100000
1M 10M
1000000
0 0.1 0.2 0.3 0.4 0.5
Frequency (Hz)
Load Current (A)
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
VOUT = VREF × ⎛⎜ 1+ R1 ⎞⎟
difference between junction and ambient temperature. The
⎝ R2 ⎠ maximum power dissipation can be calculated by the
where VREF is the reference voltage with a typical value following formula :
of 0.8V.
PD(MAX) = (TJ(MAX) − TA) / θJA
Chip Enable Operation where TJ(MAX) is the maximum junction temperature, TA is
The RT9187B goes into sleep mode when the EN pin is in the ambient temperature, and θJA is the junction to ambient
a logic low condition. In this condition, the pass transistor, thermal resistance.
error amplifier, and band gap are all turned off, reducing
For recommended operating condition specifications, the
the supply current to 1μA (max.). The EN pin can be directly
maximum junction temperature is 125°C. The junction to
tied to VIN to keep the part on.
ambient thermal resistance, θJA, is layout dependent. For
SOT-23-5 packages, the thermal resistance, θJA, is 250°C/
CIN and COUT Selection
W on a standard JEDEC 51-3 single-layer thermal test
Like any low dropout regulator, the external capacitors of
board. The maximum power dissipation at TA = 25°C can
the RT9187B must be carefully selected for regulator
be calculated by the following formula :
stability and performance. Using a capacitor of at least
2.2μF is suitable. The input capacitor must be located at PD(MAX) = (125°C − 25°C) / (250°C/W) = 0.400W for
a distance of not more than 0.5 inch from the input pin of SOT-23-5 package
the IC. Any good quality ceramic capacitor can be used.
The maximum power dissipation depends on the operating
However, a capacitor with larger value and lower ESR
ambient temperature for fixed T J(MAX) and thermal
(Equivalent Series Resistance) is recommended since it
resistance, θJA. The derating curve in Figure 1 allows the
will provide better PSRR and line transient response. The
designer to see the effect of rising ambient temperature
RT9187B is designed specifically to work with low ESR
on the maximum power dissipation.
ceramic output capacitor for space saving and performance
0.45
consideration. Using a ceramic capacitor with value at least Single-Layer PCB
Maximum Power Dissipation (W)1
0.40
2.2μF and ESR larger than 10mΩ on the RT9187B output
ensures stability. Nevertheless, the RT9187B can still work 0.35
well with other types of output capacitors due to its wide 0.30
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
H
D
L
C B
A
A1
e
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.