Intel 8086 microprocessor architecture and features

A Microprocessor is an Integrated Circuit with all the functions of a CPU. However, it cannot be used stand-alone since unlike a microcontroller
it has no memory or peripherals. 

8086 does not have a RAM or ROM inside it. However, it has internal registers for storing intermediate and final results and interfaces with
memory located outside it through the System Bus. 

In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual Inline Packaged IC. 

The size of the internal registers(present within the chip) indicates how much information the processor can operate on at a time ( in this case
16-bit registers) and how it moves data around internally within the chip, sometimes also referred to as the internal data bus. 

8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide. The main advantage of the 8086
microprocessor is that it supports Pipelining.

Memory segmentation:  
 In order to increase execution speed and fetching speed, 8086 segments the memory. 
 Its 20-bit address bus can address 1MB of memory, it segments it into 16 64kB segments. 
 8086 works only with four 64KB segments within the whole 1MB memory.

The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The Execution Unit (EU). These are
explained as following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles
such as memory read, I/O read, etc. to transfer data between memory and I/O devices. 

BIU performs the following functions are as follows: 

 It generates the 20-bit physical address for memory access.

 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an Address Generation
Circuit. 
Instruction Pointer (IP): 
 It is a 16-bit register. It holds offset of the next instructions in the  Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.  
 CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
 The address of the next instruction is calculated by using the formula CS x 10H + IP.
Example: 
CS = 4321H IP = 1000H

then CS x 10H = 43210H + offset = 44210H

Here Offset = Instruction Pointer(IP)
This is the address of the next instruction. 

Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All programs are stored in the
Code Segment and accessed via the IP. 
Data Segment register: (16 Bit register): DS holds the base address for the Data Segment. 
Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment. 
Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment. 
Please note that segments are present in memory and segment registers are present in Microprocessor.
Segment registers store starting address of each segments in memory.
 

Address Generation Circuit: 

 The BIU has a Physical Address Generation Circuit.
 It generates the 20-bit physical address using Segment and Offset addresses using the formula: 
 In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the calculation unit which is used to
calculate the physical address of an instruction in memory.
Physical Address = Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue: 
 It is a 6-byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs. 
 The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can have in 8086 is 6 bytes. Hence to
cover up all operands and data fields of maximum size instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6
Bytes.
 The pre-Fetch queue is connected with the control unit which is responsible for decoding op-code and operands and telling
the execution unit what to do with the help of timing and control signals.
 The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor is called fetch, decode, execute
type microprocessor. Since there are always instructions present for decoding and execution in this queue the speed of
execution in the microprocessor is gradually increased.
 When there is a 2-byte space in the instruction pre-fetch queue then only the next instruction will be pushed into
the queue otherwise if only a 1-byte space is vacant then there will not be any allocation in the queue. It will wait for a
spacing of 2 bytes in subsequent queue decoding operations.
 Instruction pre-fetch queue works in a sequential manner so if there is any branch condition then in that situation pre-fetch
queue fails. Hence to avoid chaos instruction queue is flushed out when any branch or conditional jumps occur.

2.prefetch unit:

The Prefetch Unit in the 8086 microprocessor is a component responsible for fetching instructions from memory and storing
them in a queue. The prefetch unit allows the 8086 to perform multiple instruction fetches in parallel, improving the overall
performance of the microprocessor.

The prefetch unit consists of a buffer and a program counter that are used to fetch instructions from memory. The buffer stores
the instructions that have been fetched and the program counter keeps track of the memory location of the next instruction to be
fetched. The prefetch unit fetches several instructions ahead of the current instruction, allowing the 8086 to execute instructions
from the buffer rather than from memory.
This parallel processing of instruction fetches helps to reduce the wait time for memory access, as the 8086 can continue to
execute instructions from the buffer while it waits for memory access to complete. This results in improved overall performance,
as the 8086 is able to execute more instructions in a given amount of time.

The prefetch unit is an important component of the 8086 microprocessor, as it allows the microprocessor to work more efficiently
and perform more instructions in a given amount of time. This improved performance helps to ensure that the 8086 remains
competitive in its performance and capabilities, even as technology continues to advance.

3. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers, the Instruction Register and
Instruction Decoder, and the Flag/Status Register. 

1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16-bit general purpose registers  AX, BX, CX, and DX which store intermediate values during execution. Each of
these has two 8-bit parts (higher and lower). 
 AX register: (Combination of AL and AH Registers)
It holds operands and results during multiplication and division operations. Also an accumulator during String operations.  
 
 BX register: (Combination of BL and BH Registers)
It holds the memory address (offset address) in indirect addressing modes. 
 
 CX register: (Combination of CL and CH Registers)
It holds the count for instructions like a loop, rotates, shifts and string operations.  
 
 DX register: (Combination of DL and DH Registers)
It is used with AX to hold 32-bit values during multiplication and division.  
 
Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations. 
Special purpose registers (16-bit): Special purpose registers are called Offset registers also. Which points to specific memory
locations under each segment.
We can understand the concept of segments as Textbook pages. Suppose there are 10 chapters in one textbook and each
chapter takes exactly 100 pages. So the book will contain 1000 pages. Now suppose we want to access page number 575 from
the book then 500 will be the segment base address which can be anything in the context of microprocessors like Code, Data,
Stack, and Extra Segment. So 500 will be segment registers that are present in Bus Interface Unit (BIU). And 500 + 75 is called
an offset register through which we can reach on specific page number under a specific segment.

Hence 500 is the segment base address and 75 is an offset address or (Instruction Pointer, Stack Pointer, Base Pointer, Source
Index, Destination Index) any of the above according to their segment implementation.
 Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET etc.
 Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is used to access random locations
of the stack.
 Source Index: It holds offset address in Data Segment during string operations.
 Destination Index: It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder: 
The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the
information to the control circuit for execution. 

Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the microprocessor. 
6 Status flags: 
1. Carry flag(CF)
2. Parity flag(PF)
3. Auxiliary carry flag(AF)
4. Zero flag(Z)
5. Sign flag(S)
6. Overflow flag (O)
Status flags are updated after every arithmetic and logic operation. 

3 Control flags: 
1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc.  The Control flags are used to
control certain operations. 

4.Decode unit:

The Decode Unit in the 8086 microprocessor is a component that decodes the instructions that have been fetched from memory.
The decode unit takes the machine code instructions and translates them into micro-operations that can be executed by the
microprocessor’s execution unit.

The Decode Unit works in parallel with the Prefetch Unit, which fetches instructions from memory and stores them in a queue.
The Decode Unit reads the instructions from the queue and translates them into micro-operations that can be executed by the
microprocessor.

The Decode Unit is an important component of the 8086 microprocessor, as it allows the microprocessor to execute instructions
efficiently and accurately. The decode unit ensures that the microprocessor can execute complex instructions, such as jump
instructions and loop instructions, by translating them into a series of simple micro-operations.

The Decode Unit is responsible for decoding instructions, performing register-to-register operations, and performing memory-to-
register operations. It also decodes conditional jumps, calls, and returns, and performs data transfers between memory and
registers.

The Decode Unit helps to improve the performance of the 8086 microprocessor by allowing it to execute instructions quickly and
accurately. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities,
even as technology continues to advance.

5.control unit :

The Control Unit in the 8086 microprocessor is a component that manages the overall operation of the microprocessor. The
control unit is responsible for controlling the flow of instructions through the microprocessor and coordinating the activities of the
other components, including the Decode Unit, Execution Unit, and Prefetch Unit.

The Control Unit acts as the central coordinator for the microprocessor, directing the flow of data and instructions and ensuring
that the microprocessor operates correctly. It also monitors the state of the microprocessor, ensuring that the correct sequence
of operations is followed.

The Control Unit is responsible for fetching instructions from memory, decoding them, executing them, and updating the
microprocessor’s state. It also handles interrupt requests and performs system management tasks, such as power management
and error handling.

The Control Unit is an essential component of the 8086 microprocessor, as it allows the microprocessor to operate efficiently
and accurately. The control unit ensures that the microprocessor can execute complex instructions, such as jump instructions
and loop instructions, by coordinating the activities of the other components.

The Control Unit helps to improve the performance of the 8086 microprocessor by managing the flow of instructions and data
through the microprocessor, ensuring that the microprocessor operates correctly and efficiently. This improved performance
helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance.

The 8086 microprocessor uses three different buses to transfer data and instructions between the microprocessor and
other components in a computer system. These buses are:

1.Address Bus: The address bus is used to send the memory address of the instruction or data being read or written. The
address bus is 16 bits wide, allowing the 8086 to address up to 64 kilobytes of memory.
2.Data Bus: The data bus is used to transfer data between the microprocessor and memory. The data bus is 16 bits wide,
allowing the 8086 to transfer 16-bit data words at a time.
3.Control Bus: The control bus is used to transfer control signals between the microprocessor and other components in the
computer system. The control bus is used to send signals such as read, write, and interrupt requests, and to transfer status
information between the microprocessor and other components.
The buses in the 8086 microprocessor play a crucial role in allowing the microprocessor to access and transfer data from
memory, as well as to interact with other components in the computer system. The 8086’s ability to use these buses efficiently
and effectively helps to ensure that it remains competitive in its performance and capabilities, even as technology continues to
advance.

Execution of whole 8086 Architecture:

1. All instructions are stored in memory hence to fetch any instruction first task is to obtain the Physical address of the
instruction is to be fetched. Hence this task is done by Bus Interface Unit (BIU) and by Segment Registers. Suppose the
Code segment has a Segment address and the Instruction pointer has some offset address then the physical address
calculator circuit calculates the physical address in which our instruction is to be fetched.
2. After the address calculation instruction is fetched from memory and it passes through C-Bus (Databus) as shown in the
figure, and according to the size of the instruction, the instruction pre-fetch queue fills up. For example  MOV AX, BX  is 1
Byte instruction so it will take only the 1 st block of the queue, and MOV BX,4050H  is 3 Byte instruction so it will take 3
blocks of the pre-fetch queue.
3. When our instruction is ready for execution, according to the FIFO property of the queue instruction comes into the control
system or control circuit which resides in the Execution unit.  Here instruction decoding takes place. The decoding
control system generates an opcode that tells the microprocessor unit which operation is to be performed. So the control
system sends signals all over the microprocessor about what to perform and what to extract from General and Special
Purpose Registers.
4. Hence after decoding microprocessor fetches data from GPR and according to instructions like ADD, SUB, MUL, and DIV
data residing in GPRs are fetched and put as ALU’s input. and after that addition, multiplication, division, or subtraction
whichever calculation is to be carried out. 
5. According to arithmetic, flag register values change dynamically.
6. While Instruction was decoding and executing from step-3 of our algorithm, the Bus interface Unit doesn’t remain
idle. it continuously fetches an instruction from memory and put it in a pre-fetch queue and gets ready for
execution in a FIFO manner whenever the time arrives.
7. So in this way, unlike the 8085 microprocessor, here the fetch, decode, and execution process happens in parallel and not
sequentially. This is called  pipelining, and because of the instruction pre-fetch queue, all fetching, decoding, and execution
process happen side-by-side. Hence there is partitioning in 8086 architecture like Bus Interface Unit and Execution Unit to
support Pipelining phenomena. 

Pin diagram of 8086 microprocessor

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its operation. The 8086
uses a 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low
order address bus lines have been multiplexed with data and 4 high-order address bus lines have been multiplexed with status
signals. 

AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to
transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the
symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15. 
A16-A19: High order address bus. These are multiplexed with status signals. 

S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or
Tw (when ready is inactive). These are used by the 8288bus controller for generating all the memory and I/O operation) access
control signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle. 
 S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals. 

A17/
S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3
and T4. 
RD’: This is used for read operation. It is an output signal. It is active when low. 
READY : This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available
by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1). 
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each instruction for determining the availability
of the request. If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle. This can be internally masked after
resulting the interrupt enable flag. This signal is active high(1) and has been synchronized internally. 
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A subroutine is then vectored through an
interrupt vector lookup table which is located in the system memory. NMI is non-maskable internally by software. A transition made from low(0)
to high(1) initiates the interrupt at the end of the current instruction. This input has been synchronized internally. 
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle. 
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in. 
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the microprocessor to release the local bus at the
end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′. 
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain control of the system bus while LOCK’ is
active low(0). The LOCK signal will be active until the completion of the next instruction. 
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the processor remains in an idle
state. The input is internally synchronized during each of the clock cycle on leading edge of the clock. 
CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control activity. Its an asymmetric square wave
with a 33% duty cycle. 
RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal must be active high(1) for at least four
clock cycles. 
Vcc : Power Supply( +5V D.C.) 
GND : Ground 
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table shown below:

QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287 data bus transceiver. The direction
of data flow is controlled through the transceiver. 
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which uses transceiver. DEN is active
low(0) during each memory and input-output access and for INTA cycles. 
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active high(1). The microprocessor receiving
the HOLD request will issue HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle. 
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or 8283 address latch. It is an active
high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is always integer. 
Interrupts in 8086 Microprocessor

An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then returns to its previous task. An interrupt
is an event or signal that requests the CPU’s attention. This halt allows peripheral devices to access the microprocessor. Whenever an interrupt
occurs, the processor completes the current instruction and starts the implementation of an Interrupt Service Routine (ISR) or Interrupt Handler.
ISR is a program that tells the processor what to do when the interrupt occurs. After the ISR execution, control returns to the main routine where
it was interrupted. In the 8086 microprocessor following tasks are performed when the microprocessor encounters an interrupt:

1. The value of the flag register is pushed into the stack. It means that first, the value of SP (Stack Pointer) is decremented by two then the
value of the flag register is pushed to the memory address of the stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the following word location.
6. Interrupt, and Trap flags are reset to 0.
The different types of interrupts present in the 8086 microprocessor are given by:

1. Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any peripheral device by sending a signal through a
specified pin to the microprocessor. There are two hardware interrupts in the 8086 microprocessor. They are:
 NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that cannot be disabled. It is the highest priority
interrupt in the 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location
00008 H, and CS is loaded from the word location 0000A H.
  INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O port. This interrupt can be masked or
delayed. It is a level-triggered interrupt. It can receive any interrupt type, so the value of IP and CS will change on the interrupt type
received.
2. Software Interrupts – These are instructions inserted within the program to generate interrupts. There are 256 software interrupts in the
8086 microprocessor. The instructions are of the format INT type, where the type ranges from 00 to FF. The starting address ranges from
00000 H to 003FF H. These are 2-byte instructions. IP is loaded from type * 04 H, and CS is loaded from the following address given by
(type * 04) + 02 H. Some important software interrupts are:
 TYPE 0 corresponds to division by zero(0).
 TYPE 1 is used for single-step execution for debugging the program.
 TYPE 2 represents NMI and is used in power failure conditions.
 TYPE 3 represents a break-point interrupt.
 TYPE 4 is the overflow interrupt.

Flag register of 8086 microprocessor

The Flag register is a Special Purpose Register. Depending upon the value of result after any arithmetic and logical operation
the flag bits become set (1) or reset (0).

 Figure – Format of flag register There are total 9 flags in 8086 and the flag register is divided into two types: (a) Status Flags
– There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0) depending upon condition after either 8-bit
or 16-bit operation. These flags are conditional/status flags. 5 of these flags are same as in case of 8085 microprocessor and
their working is also same as in 8085 microprocessor. The sixth one is the overflow flag. The 6 status flags are:
1. Sign Flag (S)
2. Zero Flag (Z)
3. Auxiliary Carry Flag (AC)
4. Parity Flag (P)
5. Carry Flag (CY) 
These first five flags are defined here
1. Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it indicates the number is negative and the sign flag
becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive and the sign flag becomes reset i.e. 0. from 00H to
7F, sign flag is 0 from 80H to FF, sign flag is 1 1- MSB is 1 (negative) 0- MSB is 0 (positive)  
Example: MVI A 30 (load 30H in register A) MVI B 40 (load 40H in register B) SUB B (A = A – B) These set of instructions
will set the sign flag to 1 as 30 – 40 is a negative number. MVI A 40 (load 40H in register A) MVI B 30 (load 30H in register
B) SUB B (A = A – B) These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive number.
2. Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise
it becomes reset i.e. 0. 00H zero flags is 1. from 01H to FFH zero flag is 0 1- zero-result 0- non-zero result  Example: MVI A
10 (load 10H in register A) SUB A (A = A – A) These set of instructions will set the zero flag to 1 as 10H – 10H is 00H
3. Auxiliary Carry Flag (AC) – This flag is used in the BCD number system(0-9). If after any arithmetic or logical operation
D(3) generates any carry and passes it on to D(4) this flag becomes set i.e. 1, otherwise, it becomes reset i.e. 0. This is the
only flag register that is not accessible by the programmer 1-carry out from bit 3 on addition or borrows into bit 3 on
subtraction 0-otherwise 
Example: MVI A 2BH (load 2BH in register A) MVI 39H (load 39H in register B) ADD B (A = A + B) These set of instructions
will set the auxiliary carry flag to 1, as on adding 2B and 39, the addition of lower-order nibbles B and 9 will generate a
carry.
4. Parity Flag (P) – If after any arithmetic or logical operation the result has even parity, an even number of 1 bit, the parity
register becomes set i.e. 1, otherwise it becomes reset i.e. 0. 1-accumulator has an even number of 1 bits 0-accumulator
has odd parity 
Example: MVI A 05 (load 05H in register A) This instruction will set the parity flag to 1 as the BCD code of 05H is
00000101, which contains an even number of ones i.e. 2.
5. Carry Flag (CY) – Carry is generated when performing n bit operations and the result is more than n bits, then this flag
becomes set i.e. 1, otherwise, it becomes reset i.e. 0. During subtraction (A-B), if A>B it becomes reset, and if (A<B) it
becomes set. Carry flag is also called the borrow flag. 1-carry out from MSB bit on addition or borrow into MSB bit on
subtraction 0-no carry out or borrow into MSB bit. 
Example: MVI A 30 (load 30H in register A) MVI B 40 (load 40H in register B) SUB B (A = A – B) These set of instructions
will set the carry flag to 1 as 30 – 40 generates a carry/borrow. MVI A 40 (load 40H in register A) MVI B 30 (load 30H in
register B) SUB B (A = A – B) These set of instructions will reset the carry flag to 0 as 40 – 30 does not generate any
carry/borrow.
6. Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too large to fit in the number of bits
available to represent it, otherwise reset (0). After any operation, if D[6] generates any carry and passes to D[7] OR if D[6]
does not generates carry but D[7] generates, overflow flag becomes set, i.e., 1. If D[6] and D[7] both generate carry or both
do not generate any carry, then overflow flag becomes reset, i.e., 0. Example: On adding bytes 100 + 50 (result is not in
range -128…127), so overflow flag will set.
MOV AL, 50 (50 is 01010000 which is positive)

MOV BL, 32 (32 is 00110010 which is positive)

ADD AL, BL (82 is 10000010 which is negative)

1. Overflow flag became set as we added 2 +ve numbers and we got a -ve number.
(b) Control Flags – The control flags enable or disable certain operations of the microprocessor. There are 3 control flags in
8086 microprocessor and these are:
1. Directional Flag (D) – This flag is specifically used in string instructions. If directional flag is set (1), then access the string
data from higher memory location towards lower memory location. If directional flag is reset (0), then access the string data
from lower memory location towards higher memory location.
2. Interrupt Flag (I) – This flag is for interrupts. If interrupt flag is set (1), the microprocessor will recognize interrupt requests
from the peripherals. If interrupt flag is reset (0), the microprocessor will not recognize any interrupt requests and will ignore
them.
3. Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the microprocessor into single step mode for
debugging. In single stepping, the microprocessor executes a instruction and enters into single step ISR. If trap flag is set
(1), the CPU automatically generates an internal interrupt after each instruction, allowing a program to be inspected as it
executes instruction by instruction. If trap flag is reset (0), no function is performed.

Q#9 There are three types of microprocessors: **CISC**, **RISC**, and **EPIC**³.

**CISC** stands for Complex Instruction Set Computer. CISC processors have a large number of instructions that can perform
complex operations in a single instruction cycle³.

**RISC** stands for Reduced Instruction Set Computer. RISC processors have a smaller set of instructions that are simpler and
faster than CISC instructions³.

**EPIC** stands for Explicitly Parallel Instruction Computing. EPIC processors are designed to execute multiple instructions in
parallel³.

I hope this helps! Let me know if you have any other questions.

The general-purpose registers are used for holding operands and pointers ⁴. They are mainly used for storing intermediate
values and for passing parameters to functions ⁴. The special-purpose registers hold specific data during processing by the
processor². They are used for holding the results of any arithmetic or logic operations carried out by the arithmetic logic unit²

1.hardwer architecture

2.software architecture

Q#10

An instruction queue is a buffer that holds instructions that are waiting to be executed by the processor¹. Pipelining is a technique for
implementing instruction-level parallelism within a single processor³. The process of fetching the next instruction when the present instruction
is being executed is called as pipelining¹. Pipelining has become possible due to the use of queue¹. The Bus Interfacing Unit (BIU) fills in the
queue until the entire queue is full¹. The BIU restarts filling in the queue when at least two locations of queue are vacant¹.

Q#11 The 8086 microprocessor can operate in two modes: minimum mode and maximum mode¹.

In minimum mode, the 8086 is the only processor in the system which provides all the control signals that are needed for memory
operations and I/O interfacing¹. In this mode, the MN/MX' pin is set to logic 1².
In maximum mode, we can connect more processors to 8086 (such as 8087/8089)². In this mode, the MN/MX' pin is set to logic 0².

The read cycle of 8086 microprocessor in minimum mode consists of four clock cycles: first clock cycle is for address latch enable
(ALE), second clock cycle is for memory read (RD), third clock cycle is for input/output (I/O) read (IORC), and fourth clock cycle is
for data read³. The write cycle of 8086 microprocessor in minimum mode consists of three clock cycles: first clock cycle is for
address latch enable (ALE), second clock cycle is for memory write (WR), and third clock cycle is for input/output (I/O) write
(IOWC)³.

Pin diagram of 8085 microprocessor

1. Address Bus and Data Bus: 

The address bus is a group of sixteen lines i.e A0-A15. The address bus is unidirectional, i.e., bits flow in one direction from the
microprocessor unit to the peripheral devices and uses the high order address bus. 
2. Control and Status Signals: 
 
 ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle and enables the lower 8-bits
of the address, if its value is 1 otherwise data bus is activated. 

 IO/M’ – It is a status signal which determines whether the address is for input-output or memory. When it is high(1) the
address on the address bus is for input-output devices. When it is low(0) the address on the address bus is for the
memory. 
 

 SO, S1 – These are status signals. They distinguish the various types of operations such as halt, reading, instruction
fetching or writing. 
 

IO/
M’ S1 S0 Data Bus Status

0 1 1 Opcode fetch

0 1 0 Memory read

0 0 1 Memory write

1 1 0 I/O read

1 0 1 I/O write

1 1 1 Interrupt acknowledge

0 0 0 Halt

  
 RD’ – It is a signal to control READ operation. When it is low the selected memory or input-output device is read. 
 

 WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is written into the selected
memory or I/O location. 
 

 READY – It senses whether a peripheral is ready to transfer data or not. If READY is high(1) the peripheral is ready. If it is
low(0) the microprocessor waits till it goes high. It is useful for interfacing low speed devices. 
 
3. Power Supply and Clock Frequency: 
 

 Vcc – +5v power supply 

 

 Vss – Ground Reference 

 

 XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by two, therefore, to operate a system
at 3MHZ the crystal should have frequency of 6MHZ. 
 

 CLK (OUT) – This signal can be used as the system clock for other devices. 
 
4. Interrupts and Peripheral Initiated Signals: 
The 8085 has five interrupt signals that can be used to interrupt a program execution. 

(i) INTR 
(ii) RST 7.5 
(iii) RST 6.5 
(iv) RST 5.5 
(v) TRAP 

The microprocessor acknowledges Interrupt Request by INTA’ signal. In addition to Interrupts, there are three externally initiated
signals namely RESET, HOLD and READY. To respond to HOLD request, it has one signal called HLDA. 

 INTR – It is an interrupt request signal. 

 

 INTA’ – It is an interrupt acknowledgement sent by the microprocessor after INTR is received. 
 
5. Reset Signals: 
 

 RESET IN’ – When the signal on this pin is low(0), the program-counter is set to zero, the buses are tristated and the
microprocessor unit is reset. 
 

 RESET OUT – This signal indicates that the MPU is being reset. The signal can be used to reset other devices. 
 
6. DMA Signals: 
 

 HOLD – It indicates that another device is requesting the use of the address and data bus. Having received HOLD request
the microprocessor relinquishes the use of the buses as soon as the current machine cycle is completed. Internal
processing may continue. After the removal of the HOLD signal the processor regains the bus. 
 

 HLDA – It is a signal which indicates that the hold request has been received after the removal of a HOLD request, the
HLDA goes low. 
 
7. Serial I/O Ports: 
Serial transmission in 8085 is implemented by the two signals, 
 

 SID and SOD – SID is a data line for serial input where as SOD is a data line for serial output.