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    Min and Max Mode 8259

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    EC21B1005 SRAVANA SANDHYA BALLA
    The document discusses the minimum mode of operation of the 8086 microprocessor. It describes the timing diagram of an opcode fetch or read cycle in minimum mode. It shows that the address is provided by the processor in T1 state and remains valid for one T-state. In T2, the bus is tristated to change direction for a read. Data transfer occurs from T3 to T4, with wait states inserted if the device is slower. It also describes the write cycle timings and signals. Maximum mode operation uses external components like 8288 bus controller for control signals while minimum mode generates signals internally. Memory interfacing concepts involving address, data and control lines are also summarized.

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    Min and Max Mode 8259

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    EC21B1005 SRAVANA SANDHYA BALLA
    25 views11 pages
    The document discusses the minimum mode of operation of the 8086 microprocessor. It describes the timing diagram of an opcode fetch or read cycle in minimum mode. It shows that the address is provided by the processor in T1 state and remains valid for one T-state. In T2, the bus is tristated to change direction for a read. Data transfer occurs from T3 to T4, with wait states inserted if the device is slower. It also describes the write cycle timings and signals. Maximum mode operation uses external components like 8288 bus controller for control signals while minimum mode generates signals internally. Memory interfacing concepts involving address, data and control lines are also summarized.

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    The document discusses the minimum mode of operation of the 8086 microprocessor. It describes the timing diagram of an opcode fetch or read cycle in minimum mode. It shows that the address is provided by the processor in T1 state and remains valid for one T-state. In T2, the bus is tristated to change direction for a read. Data transfer occurs from T3 to T4, with wait states inserted if the device is slower. It also describes the write cycle timings and signals. Maximum mode operation uses external components like 8288 bus controller for control signals while minimum mode generates signals internally. Memory interfacing concepts involving address, data and control lines are also summarized.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    25 views11 pages

    Min and Max Mode 8259

    Uploaded by

    EC21B1005 SRAVANA SANDHYA BALLA
    The document discusses the minimum mode of operation of the 8086 microprocessor. It describes the timing diagram of an opcode fetch or read cycle in minimum mode. It shows that the address is provided by the processor in T1 state and remains valid for one T-state. In T2, the bus is tristated to change direction for a read. Data transfer occurs from T3 to T4, with wait states inserted if the device is slower. It also describes the write cycle timings and signals. Maximum mode operation uses external components like 8288 bus controller for control signals while minimum mode generates signals internally. Memory interfacing concepts involving address, data and control lines are also summarized.

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    Minimum mode circuit

    Minimum mode timing diagram:


    Opcode fetch or read timing diagram

    • All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given


    by processor in the T1 state. It is available on the bus for one T-state.
    • In T2, the bus is tristate for changing the direction of the bus (in the case of a data
    read cycle.)
    • The data transfer takes place between T 3 and T4.
    • If the addressed device is slower, then the wait state is inserted between T 3 and
    T4 .
    1. At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus
    and also M / IO’= 1, which indicates the memory operation is in progress.
    2. In T2, the address is removed from the local bus and is sent to the addressed device.
    Then the bus is tristated.
    3. When RD’ = 0 , the valid data is present on the data bus.
    4. During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that
    the data is received.
    5. During T3, data is put on the data bus and the processor reads it.
    6. The output device makes the READY line high. This means the output device has
    performed the data transfer process. When the processor makes the read signal to 1,
    then the output device will again tristate its bus drivers.

    Write cycle:

    1. At T1 state ALE =1, this indicates that a valid address is latched on the address bus
    and also M / IO’= 1, which indicates the memory operation is in progress.
    2. In T2, the processor sends the data to be written to the addressed location.
    3. The data is buffered on the bus until the middle of T4 state.
    4. The WR’=0 becomes at the beginning of T2.
    5. The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.
    6. During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates that
    the data is transferred by the processor to the addressed device.
    Maximum mode:

    When MN/ MX’ = 0 , 8086 works in max mode.


    Clock is provided by 8284 clock generator.
    8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three
    such latches are required because address bus is 20 bit. The ALE(Address latch enable) is
    connected to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller.
    The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
    because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction
    of data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected
    to T. Both DEN and DT/ R’ are given by 8288 bus controller.
    Minimum mode of 8086 Maximum mode of 8086
    MN/MX’ = 1 MN/MX’ = 0
    ALE is generated by 8086 ALE is generated by 8288
    T and OE’ are received from 8086 T and OE’ are received from 8288
    Control signal are generated by 8086 through Control signals are generated from 8288
    74138 decoder
    Bus request is done using HOLD, HLDA Bus request through RQ/GT
    Clock frequency is provided only to processor Clk frequency is provided to 8288 also
    Only one processor is used Multiple processors are used

    MEMORY INTERFACING:
    Memory is an integral part of a microcomputer system. There are two main types of
    memory.
    (i) Read only memory (ROM): As the name indicates this memory is available only for
    reading purpose. The various types available under this category are PROM, EPROM,
    EEPROM which contain system software and permanent system data.
    (ii) Random Access memory (RAM): This is also known as Read Write Memory. It is a
    volatile memory. RAM contains temporary data and software programs generally for
    different applications.
    While executing particular task it is necessary to access memory to get instruction codes and
    data stored in memory. The microprocessor should be able to read from or write into the
    specified register. The basic concepts of memory interfacing involve three different tasks
    such as selection of the required chip, identify the required register and enable the appropriate
    buffers.

    Advanced Microprocessors and Microcontrollers” by A.K Ray & K.M. Bhurchandi


    Memory device must contain address lines, Input, output lines, selection input and control
    input to perform read or write operation. All memory devices have address inputs that select
    memory location within the memory device. These lines are labelled as AO ...... AN. The
    number of address lines indicates the total memory capacity of the memory device. A 1K
    memory requires 10 address lines A0-A9. Similarly, a 1MB requires 20 lines A0-A19 (in the
    case of 8086). The memory devices may have separate I/O lines or a common set of
    bidirectional I/O lines. Using these lines data can be transferred in either direction. Whenever
    output buffer is activated, the data is read and whenever input buffers are activated the data
    is written. These lines are labelled as I/O ... I/On or DO .............Dn. The size of a memory
    location is dependent upon the number of data bits. If the numbers of data lines are eight
    ,then 8 bits or 1 byte of data can be stored in each location. Similarly, if numbers of data bits
    are 16, then the memory size is 2 bytes. For example, 2K x 8 indicates there are 2048 memory
    locations and each memory location can store 8 bits of data.
    Memory devices may contain one or more inputs which are used to select the memory device
    or to enable the memory device. This pin is denoted by CS (Chip select) or CE (Chip enable).
    When this pin is at logic '0' then only the memory device performs a read or a write operation.
    If this pin is at logic ‘1’ the memory chip is disabled. If there are more than one CS input
    then all these pins must be activated to perform read or write operation. All memory devices
    will have one or more control inputs. When ROM is used, OE (output enable) pin allows data
    to flow out of the output data pins. To perform this task both CS and OE must be active. A
    RAM contains one or two control inputs. They are R /W or RD and WR . If there is only one
    input R/W then it performs read operation when R/W pin is at logic 1. If it is at logic 0 it
    performs write operation.

    MEMORY INTERFACE USING RAMS, EPROMS AND EEPROM

    1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-
    bit bank is called ‘odd address memory bank’ and the lower 8-bit bank is called ‘even
    address memory bank’.
    2. Connect available memory address lines of memory chips with those of the
    microprocessor and also connect the memory RD and WR inputs to the corresponding
    processor control signals. Connect the 16-bit data bus of the memory bank with that of
    the microprocessor 8086.
    3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding
    the required chip select signals for the odd and even memory banks. CS of memory is
    derived from the O/P of the decoding circuit. The address map of the system should be
    continuous as far as possible, i.e. there should be no windows in the map. A memory
    location should have a single address corresponding to it, i.e. absolute decoding should
    be preferred, and minimum hardware should be used for decoding. Mostly, linear
    decoding are used to minimise the required hardware.

    EXAMPLE:
    Interface two 4K x 8 EEPROM and two 4K x 8 RAM Chips with 8086. Select suitable
    maps.
    Solution:
    After reset, the the IP and CS are initiated to form FFFF0H, hence this address must
    lie in the EEPROM. The address of RAM may be selected anywhere in the 1MB address
    space of 8086, but we will select the RAM address such that the address map is
    continuous.
    8259 PIC (PROGRAMMABLE INTERRUPT CONTROLLER)
    ICW1

    ICW2-
    ICW3

    ICW4:

    OCW1
    OCW2

    OCW3

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