Minimum and Maximum Mode of 8086 of 8086: Sutapa Sarkar

Minimum and Maximum Mode
of 8086
Sutapa Sarkar
74LS373
8 buffered latches
Can be used as 8-bit output port
74LS245
8 Bidirectional Buffers
If DIR = 1: direction from I/Ps to O/Ps
If DIR = 0: direction from O/Ps to I/Ps
Latching 20 bit Address of 8086
Buffering Data Bus of 8086
Deriving 8086 Control Signals
Minimum mode of 8086
Read Cycle Diagram for Minimum
Mode
Write Cycle Diagram for Minimum
Mode
8086
Microprocessor MINIMUM MODE
The microprocessor 8086 is operated in minimum mode by giving logic 1 to

MN / pin .
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system. The remaining
components in the system are latches, transreceivers, clock generator, memory and I/O
devices.1`
Latches are used for separating the valid address from the multiplexed address/data
signals and are controlled by the ALE signal generated by 8086.Here 8282, 8-bit latch is
used. The ALE signal is connected to STB of 8282.
When STB(ALE) is high, the input is latched and transferred to the output. Hence
address is latched.
When STB(ALE) is low, the input is discarded. Hence data is not latched. The previously
latched address remains at the output.
As totally 21 bits are to be latched (A19-A0 and BHE), 3 latches are required, each latch
being a 8-bit.
8086
Transreceivers are the bidirectional buffers. They are required to separate the valid
data from the multiplexed address/data bus.
They are controlled by two signals namely, DEN and DT/ R
The DT/ R signal indicates the direction of data, i.e. from or to the processor.
DEN enables the buffer when the multiplexed address and data bus contains data.
Control signals for all operations are generated by decoding M / IO , RD & WR

Signals
M / IO RD WR Control signal
1 0 1 Memory Read MEMR
1 1 0 Memory Write MEMW
0 0 1 I/O Read IOR
0 1 0 I/O Write IOW

8086
Minimum Mode Read Cycle
The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and
also M /IO signal. During the negative going edge of this signal, the valid address is
latched on the bus.
From T1 to T4 , the M/ IO signal indicates a memory or I/O operation.
At T2, the address is removed from the bus and is sent to the output. The bus is then
tristated. The read (RD ) control signal is also activated in T2.
The read ( RD ) enables the addressed device. After RD goes low, the valid data is
available on the data bus.
8086
Minimum Mode Read Cycle
8086 MINIMUM MODE
Microprocessor
Minimum Mode Write Cycle
A write cycle also begins with the assertion of ALE and the emission of the address.
The M/ IO signal is again asserted to indicate a memory or I/O operation. In T2,
after sending the address in T1, the processor sends the data to be written to the
addressed location.
The data remains on the bus until middle of T4 state. The WR becomes active at
the beginning of T2.
Bus Request and Bus Grant Timings in
Minimum Mode System
Maximum Mode of 8086
8288 Pin Description
Memory Read Timing in maximum
mode
Memory Write Timing in maximum
mode
8086
Microprocessor MAX-MODE
Maximum Mode 8086 System
In the maximum mode, the 8086 is operated by connecting the MN/MX pin to ground.
In this mode, the processor derives the status signal S2 , S1 , S0 . Another chip called
bus controller derives the control signals using this status information .
 In the maximum mode, there may be more than one microprocessor in the system
configuration. The other components in the system are same as in the minimum mode
system.
The basic function of the bus controller chip IC8288, is to derive control signals like RD
and WR (for memory and I/O devices), DEN, DT/ R , ALE etc. using the information
made available by the processor on the status lines.
The bus controller chip has input lines S2 , S1 , S0 and CLK which are driven by CPU.
It derives the outputs ALE, DEN, DT/ R , MRDC , MWTC , AMWC, IORC, IOWC
and AIOWC .
8086
 IORC and IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the address
port.
 The MRDC and MWTC are memory read command and memory write command
signals respectively and may be used as memory read or write signals.
All these command signals instructs the memory to accept or send data from or to the
bus.
Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.
The maximum mode timing diagrams can be categorized in two parts,

the first is the timing diagram for read cycle and
the second is the timing diagram for write cycle.
8086
8086
 S2 , S1 , S0 are set at the beginning of bus cycle. 8288 bus controller will output
a pulse as on the ALE and apply a required signal to its DT/ R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC . These signals are activated until T4.
For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or

IOWC is activated from T3 to T4.
The status bit S0 to S2 remains active until T3.

Timing for RQ / GT
RQ / GT
Thank You

Minimum and Maximum Mode of 8086 of 8086: Sutapa Sarkar

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Minimum and Maximum Mode of 8086 of 8086: Sutapa Sarkar

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Minimum and Maximum Mode

The microprocessor 8086 is operated in minimum mode by giving logic 1 to

Control signals for all operations are generated by decoding M / IO , RD & WR

1 1 0 Memory Write MEMW

0 0 1 I/O Read IOR

0 1 0 I/O Write IOW

From T1 to T4 , the M/ IO signal indicates a memory or I/O operation.

Minimum Mode Write Cycle

The maximum mode timing diagrams can be categorized in two parts,

For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or

The status bit S0 to S2 remains active until T3.

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