MAPUA UNIVERSITY

SCHOOL OF EE-ECE-CpE

Behavioral Modeling
DRILL 5

NAME: Soquiat, Marc Hendri

STUDENT NUMBER: 2021103916
TERMINAL NUMBER: 15
DATE OF PERFORMANCE: 07/07/2023
DATE OF SUBMISSION: 07/07/2023

Mark Jayson Sutayco

PROFESSOR
I. DISCUSSION

Behavioural modelling represents digital circuits at a functional and

algorithmic level. It is used mostly to describe sequential circuits, but can also be
used to describe combinational circuits.

The primary mechanisms for modeling the behavior of a design are the
following two statements:
• Initial statement
• Always statement

An initial statement executes only once and begins its execution at start of
simulation which is at time 0. initial [timing_control] procedural_statement
An always statement executes repeatedly and also begins its execution at
start of simulation which is at time 0. always [timing_control] procedural_statement

A procedural_statement is one of the following:

• procedural_assignment (blocking or non_blocking)
• procedural_continuous_assignment
• conditional_statement
• case_statement
• loop_statement
• wait_statement
• disable_statement
• event_trigger
• sequential_block
• parallel_block
• task_enable (user or system)

Behavioral descriptions use the keyword always, followed by an optional event

control expression specifies when the statements will execute. The target output of
procedural assignment statements must be of the reg data type.
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 A block statement provides a mechanism to group two or more
statements to act syntactically like a single statement. There are two kinds
of blocks in Verilog HDL. These are:
• Sequential block (begin…end): Statements are executed sequentially in the
given order.
• Parallel block (fork…join): Statements in this block execute concurrently.

A procedural assignment is an assignment within an initial

statement or an always statement. It is used only to assign to a register
data type. There are two kinds of procedural assignments:
• Blocking procedural assignment
A procedural assignment in which the assignment operator is an “=” is a
blocking procedural assignment.
• Non-blocking procedural assignment
A procedural assignment in which the assignment operator is an “<=” is a
non-blocking procedural assignment.

The Conditional Statement if-else

The if - else statement controls the execution of other statements. In

programming language like C, if - else controls the flow of program. When more
than one statement needs to be executed for an if condition, then we need to use
begin and end as seen in earlier examples.

One-Way Selection:
if (condition)
statements; Two-Way
Selection (if-else): if
(condition)
statements;
else
statements;
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Nested if (if-else-if):
if (condition) statements;
else if (condition)
statements;
else statements;

Case construct
A case statement is a multi-way conditional branch. It has the following
syntax:
case ( case_expr ) case_item_expr {,case_item_expr } :
procedural_statement
…
…
[ default : procedural_statement ]
endcase

The case construct has two important variations: casex and casez

There are four kinds of loop statements. These are:

• Forever-loop
– This loop continuously executes the procedural statement.
forever procedural_statement
• Repeat-loop
– Executes the procedural statement the specified number of
times.
repeat (loop_count) procedural_statement
• While-loop
– Executes the procedural statement until the specified condition
becomes false.
while (condition)
procedural_statement
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 • For-loop
– Repeats the execution of the procedural assignment a certain
number of times.
for (initial_assignment ; condition; step-assignment)
procedural_statement

II. DRILL EXERCISES

NOTE: Include the screenshot of the output and the timing diagram

1. Design a Verilog behavioral model of a sequence detector using D flip-flops.

The state table for a sequence detector is as follows:

Present State Input Next State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

The program below describes a behavioral model of the circuit obtained from the
state table above. Once compiled, save the file as drill5_1.vl

module flip_flop (clk, reset, d, q);

input clk, reset, d; output
q;
reg q;
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 always @ (posedge clk ) begin
if (reset == 1)
begin q <= 0;
end
else begin q
<= d;
end
end
endmodule

module circuit_ff(input clk, reset, x, output y);

wire OR1, OR2, AND1, AND2, AND3; wire A, B,
Bnot;
not (Bnot, B);
flip_flop ff1(clk, reset, OR1, A);
flip_flop ff2(clk, reset, OR2, B);
and (AND1,A,x), (AND2,B,x), (AND3,Bnot,x), (AND4,A,B);
or (OR1, AND1,AND2), (OR2,AND1,AND3);
and (y,B,A);
endmodule

module testff;
reg clk, reset,d;
wire q;
circuit_ff cff(clk, reset, d, q);

initial begin
clk=0; reset=1; d=0;
$monitor("clk=%b reset=%b d=%b q=%b",clk,reset,d,q);
end
initial begin forever #1 clk=~clk;
end
initial fork
#1 reset=0;
#2 d=1; #3 reset=1;

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 #4 reset=0;
#5 d=0;
#8 d=1;
#10 $finish;
join endmodule

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2. Create a behavioural description of an eight-to-one line multiplexer.
The program below is a behavioural description of an 8-1 MUX. Compile the
file then save it as drill5_2.vl

module mux_8_1 (output reg m_out, input [7:0]in_x, input[2:0] select);

always@(in_x[0],in_x[1],in_x[2],in_x[3],in_x[4],in_x[5],in_x[6],in_x[7],select) case(select)
3'b000: m_out=in_x[0];
3'b001: m_out=in_x[1];
3'b010: m_out=in_x[2];
3'b011: m_out=in_x[3];
3'b100: m_out=in_x[4];
3'b101: m_out=in_x[5];
3'b110: m_out=in_x[6];
3'b111: m_out=in_x[7];
endcase
endmodule

module testMux();
reg [7:0] x; reg
[2:0] select; wire
m_out;

mux_8_1 MUX1(m_out, x, select); initial

begin select=2'b00; x=8'h4F; $strobe("Select
Input Output");
$monitorb(select," ", x, " ", m_out);
#1 select=3'b000;
#1 select=3'b001;
#1 select=3'b010;
#1 select=3'b011;
#1 select=3'b100;
#1 select=3'b101;
#1 select=3'b110;
#1 select=3'b111;
#1 $display("Changing value of input");
#1 x=8'h98;
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 #1 select=3'b000;
#1 select=3'b001;
#1 select=3'b010;
#1 select=3'b011;
#1 select=3'b100;
#1 select=3'b101;
#1 select=3'b110;
#1 select=3'b111;
#100 $finish;
end endmodule

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3. Create an HDL model of the operation of a sequential circuit based from the given
state diagram:

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 0/0 1/0

0/1

00 10

0/1
1/0 0/1 1/0

01 1/0 11

The program below is formulated based from the given diagram above.
Compile the file then save it as drill5_3.vl

module state_diagram(
output reg y_out,
input x_in, clock, reset
);

reg[1:0] state, next_state;

parameter S0=2'b00,
S1=2'b01,
S2=2'b10,
S3=2'b11;
always@(posedge clock, negedge reset)
if (reset==0) state <= S0;
else state <= next_state; always@(state,
x_in) case (state)
S0: if (x_in) next_state=S1; else next_state=S0;
S1: if (x_in) next_state=S3; else next_state=S0;
S2: if (~x_in) next_state=S0; else next_state=S2;
S3: if (x_in) next_state=S2; else next_state=S0;
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 endcase
always@(state, x_in)
case (state)
S0: y_out=0;
S1,S2,S3: y_out=~x_in;
endcase
endmodule

module sdiag;
wire t_y_out;
reg t_x_in, t_clock, t_reset;
state_diagram sd(t_y_out, t_x_in, t_clock, t_reset);
initial #200 $finish; initial begin
t_clock=0;
forever #5 t_clock=~t_clock;

end
initial fork
$monitor($time,,"reset=%b clock=%b x=%b y=%b" ,t_reset, t_clock, t_x_in,
t_y_out);
t_reset=0;
#2 t_reset=1;
#87 t_reset=0;
#89 t_reset=1;
#10 t_x_in=1;
#30 t_x_in=0;
#40 t_x_in=1;
#50 t_x_in=0;
#52 t_x_in=1;
#54 t_x_in=0;
#70 t_x_in=1;
#80 t_x_in=1;
#70 t_x_in=0;
#90 t_x_in=1;
#100 t_x_in=0;
#120 t_x_in=1;
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 #160 t_x_in=0;
#170 t_x_in=1;
join
endmodule

III. PROGRAMMING EXERCISE (CHOOSE 1)

NOTE: Include the screenshot of the output and the timing diagram

1. Design a Verilog HDL behavioral model of a 4-bit up-down counter

designed using negative edge triggered T flip flops. Simulate

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IV. Review Questions
1. How is race condition experienced in Verilog HDL programming?
A race condition in Verilog HDL programming occurs when two or more
statements that are scheduled to execute in the same simulation time-step,
would give different results when the order of statement execution is
changed, as permitted by the IEEE Verilog Standard.
2. Is there a difference between the instructions
always #1 a=!a;
and forever #1 a=!a;
If yes, what is/are their difference/s?

Yes, there is a difference between the always #1 a=!a; and forever #1

a=!a; instructions in Verilog HDL. The always #1 a=!a; instruction will
execute once, and then stop. The forever #1 a=!a; instruction will execute
repeatedly, forever.
3. Differentiate the selection constructs used in Verilog with those used in
high-level languages (C++, C#, etc).
The notion of time is used in Verilog, however, it is absent from other high-
level programming languages like C++. It is required for modeling logical
circuits. Verilog is a language for describing hardware, whereas C# and C++
are more focused on computers software language.
4. How are multiple always@ blocks executed within a given program?
A parenthesis with a begin and end next to it in a given program are the
reason for the always@ blocks to run.
5. What are sensitivity lists? How do they affect the entire behavioral model
description of a program?
It is a concise way of describing the set of events and signals that may
trigger the continuation of a process. This is said following the keyword
process. It is utilized when you mention every signal that you want to
make the process's code be assessed as its state changes.
6. Why does the register operation of state transitions use a non-blocking
operator ( <= ) ?
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 The register operation of a state transition uses a non-blocking operator
in order for a one schedule assignment to be doable without causing
blocks in the processing of the program. Non-block assignments are also
sequential.

INTERPRETATION OF RESULTS

• The counter is a 4-bit counter, which means that it can count up to 16

different values.
• The counter is designed using negative edge triggered T flip flops. This
means that the flip flops will toggle their outputs when the clock signal goes
from high to low.
• The counter is controlled by three inputs: clk, reset, and up/down. The clk
signal is the clock signal for the counter. The reset signal resets the counter
to 0. The up/down signal determines whether the counter counts up or
down.
• The counter works as expected. When the up/down signal is high, the
counter counts up. When the up/down signal is low, the counter counts
down. The counter will continue to count up and down indefinitely.

RESULTS AND CONCLUSION

In conclusion, the 4-bit up-down counter created with negative edge

triggered T flip flops behaves as predicted by the Verilog HDL behavioral model. The
counter goes from 0 to 15, then counts backwards from 15 to 0. There is no end to
the up-and-down counting of the counter. This design is straightforward but
efficient and suitable for a number of uses. Overall, the negative edge triggered T
flip flop-based Verilog HDL behavioral model of a 4-bit up-down counter is a
straightforward but efficient design that may be used to a variety of tasks.

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