MAPUA INSTITUTE OF TECHNOLOGY

SCHOOL OF EE-ECE-CpE

Behavioral Modeling
DRILL 5

NAME: MANUEL, LESTER N.

STUDENT NUMBER: 2015103119
TERMINAL NUMBER: TERMINAL #18
DATE OF PERFORMANCE: JULY 27, 2019
DATE OF SUBMISSION: JULY 27, 2019

ROSEMARIE PELLEGRINO
PROFESSOR
I. DISCUSSION

Behavioural modelling represents digital circuits at a functional and

algorithmic level. It is used mostly to describe sequential circuits but can also be
used to describe combinational circuits.

The primary mechanisms for modeling the behavior of a design are the
following two statements:
 Initial statement
 Always statement

An initial statement executes only once and begins its execution at start of
simulation which is at time 0.
initial [timing_control] procedural_statement
An always statement executes repeatedly and also begins its execution at
start of simulation which is at time 0.
always [timing_control] procedural_statement

A procedural_statement is one of the following:

 procedural_assignment (blocking or non_blocking)
 procedural_continuous_assignment
 conditional_statement
 case_statement
 loop_statement
 wait_statement
 disable_statement
 event_trigger
 sequential_block
 parallel_block
 task_enable (user or system)

Behavioral descriptions use the keyword always, followed by an optional

event control expression specifies when the statements will execute. The target
output of procedural assignment statements must be of the reg data type.

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 A block statement provides a mechanism to group two or more statements
to act syntactically like a single statement. There are two kinds of blocks in Verilog
HDL. These are:
 Sequential block (begin…end): Statements are executed sequentially in the
given order.
 Parallel block (fork…join): Statements in this block execute concurrently.

A procedural assignment is an assignment within an initial statement or an

always statement. It is used only to assign to a register data type. There are two
kinds of procedural assignments:
 Blocking procedural assignment
A procedural assignment in which the assignment operator is an “=” is a
blocking procedural assignment.
 Non-blocking procedural assignment
A procedural assignment in which the assignment operator is an “<=” is a
non-blocking procedural assignment.

The Conditional Statement if-else

The if - else statement controls the execution of other statements. In

programming language like C, if - else controls the flow of program. When more
than one statement needs to be executed for an if condition, then we need to use
begin and end as seen in earlier examples.

One-Way Selection:
if (condition)
statements;
Two-Way Selection (if-else):
if (condition)
statements;
else
statements;

Nested if (if-else-if):
if (condition)
statements;
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 else if (condition)
statements;
else
statements;

Case construct
A case statement is a multi-way conditional branch. It has the following
syntax:
case ( case_expr )
case_item_expr { case_item_expr } : procedural_statement
…
…
[ default : procedural_statement ]
endcase

The case construct has two important variations: casex and casez

There are four kinds of loop statements. These are:

 Forever-loop
– This loop continuously executes the procedural statement.
forever procedural_statement
 Repeat-loop
– Executes the procedural statement the specified number of
times.
repeat (loop_count) procedural_statement
 While-loop
– Executes the procedural statement until the specified condition
becomes false.
while (condition)
procedural_statement
 For-loop
– Repeats the execution of the procedural assignment a certain
number of times.
for (initial_assignment ; condition; step-assignment)
procedural_statement

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II. Drill Exercises
1. Design a Verilog behavioural model of a sequence detector using D flip-flops.

The state table for a sequence detector is as follows:

Present State Input Next State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

The program below describes a behavioural model of the circuit obtained

from the state table above. Once compiled, save the file as drill5_1.vl

module flip_flop (clk, reset, d, q);

input clk, reset, d;
output q;
reg q;

always @ (posedge clk )

begin
if (reset == 1)
begin
q <= 0;
end
else
begin
q <= d;
end
end
endmodule

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module circuit_ff(input clk, reset, x, output y);
wire OR1, OR2, AND1, AND2, AND3;
wire A, B, Bnot;
not (Bnot, B);
flip_flop ff1(clk, reset, OR1, A);
flip_flop ff2(clk, reset, OR2, B);
and (AND1,A,x), (AND2,B,x), (AND3,Bnot,x), (AND4,A,B);
or (OR1, AND1,AND2), (OR2,AND1,AND3);
and (y,B,A);
endmodule

module testff;
reg clk, reset,d;
wire q;
circuit_ff cff(clk, reset, d, q);

initial begin
clk=0; reset=1; d=0;
$monitor("clk=%b reset=%b d=%b q=%b",clk,reset,d,q);
end
initial begin
forever #1 clk=~clk;
end
initial fork
#1 reset=0;
#2 d=1;
#3 reset=1;
#4 reset=0;
#5 d=0;
#8 d=1;
#10 $finish;
join
endmodule

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2. Create a behavioural description of an eight-to-one line multiplexer.

The program below is a behavioural description of an 8-1 MUX. Compile the

file then save it as drill5_2.vl

module mux_8_1 (output reg m_out, input [7:0]in_x, input[2:0] select);

always@(in_x[0],in_x[1],in_x[2],in_x[3],in_x[4],in_x[5],in_x[6],in_x[7],select
)
case(select)
3'b000: m_out=in_x[0];
3'b001: m_out=in_x[1];
3'b010: m_out=in_x[2];
3'b011: m_out=in_x[3];
3'b100: m_out=in_x[4];
3'b101: m_out=in_x[5];
3'b110: m_out=in_x[6];
3'b111: m_out=in_x[7];
endcase
endmodule

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module testMux();
reg [7:0] x;
reg [2:0] select;
wire m_out;

mux_8_1 MUX1(m_out, x, select);

initial begin
select=2'b00; x=8'h4F;
$strobe("Select Input Output");
$monitorb(select," ", x, " ", m_out);
#1 select=3'b000;
#1 select=3'b001;
#1 select=3'b010;
#1 select=3'b011;
#1 select=3'b100;
#1 select=3'b101;
#1 select=3'b110;
#1 select=3'b111;
#1 $display("Changing value of input");
#1 x=8'h98;
#1 select=3'b000;
#1 select=3'b001;
#1 select=3'b010;
#1 select=3'b011;
#1 select=3'b100;
#1 select=3'b101;
#1 select=3'b110;
#1 select=3'b111;
#100 $finish;
end
endmodule

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3. Create an HDL model of the operation of a sequential circuit based from the
given state diagram:
0/0 1/0

0/1

00 10

0/1
1/0 0/1 1/0

01 1/0 11

The program below is formulated based from the given diagram above.
Compile the file then save it as drill5_3.vl

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module state_diagram(
output reg y_out,
input x_in, clock, reset
);

reg[1:0] state, next_state;

parameter S0=2'b00,
S1=2'b01,
S2=2'b10,
S3=2'b11;
always@(posedge clock, negedge reset)
if (reset==0) state <= S0;
else state <= next_state;
always@(state, x_in)
case (state)
S0: if (x_in) next_state=S1; else next_state=S0;
S1: if (x_in) next_state=S3; else next_state=S0;
S2: if (~x_in) next_state=S0; else next_state=S2;
S3: if (x_in) next_state=S2; else next_state=S0;
endcase
always@(state, x_in)
case (state)
S0: y_out=0;
S1,S2,S3: y_out=~x_in;
endcase
endmodule

module sdiag;
wire t_y_out;
reg t_x_in, t_clock, t_reset;
state_diagram sd(t_y_out, t_x_in, t_clock, t_reset);
initial #200 $finish;
initial begin
t_clock=0;
forever #5 t_clock=~t_clock;

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 end
initial fork
$monitor($time,,"reset=%b clock=%b x=%b y=%b" ,t_reset, t_clock,
t_x_in, t_y_out);
t_reset=0;
#2 t_reset=1;
#87 t_reset=0;
#89 t_reset=1;
#10 t_x_in=1;
#30 t_x_in=0;
#40 t_x_in=1;
#50 t_x_in=0;
#52 t_x_in=1;
#54 t_x_in=0;
#70 t_x_in=1;
#80 t_x_in=1;
#70 t_x_in=0;
#90 t_x_in=1;
#100 t_x_in=0;
#120 t_x_in=1;
#160 t_x_in=0;
#170 t_x_in=1;
join
endmodule

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III. Programming Exercise

1. Design a Verilog HDL behavioural model of a 4-bit up-down counter

designed using negative edge triggered T flip flops. Save the file as
exercise5_1.vl
2. Code a behavioural description of a sequential circuit with two JK flip-
flops F1 and F2 and two inputs X and Y. If X=0 and Y=1, the circuit goes
from transitions 01 to 00 to 10 to 11 back to 01. If X=0, and Y=0, the
circuit goes through the transition 01 to 11 to 10 to 00 back to 01. The
circuit remains the same regardless of the value of Y if X=1.
3. Code a behavioural model of a four-bit shift register with parallel load
using positive edge triggered D flip-flops. There are two control inputs:
load and shift. When shift=1, the contents of the register are shifted
by one position. New data are transferred into the register when
load=1 and shift=0. If both control inputs are equal to 0, the contents
of the register do not change.

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IV. Review Questions
1. How is race condition experienced in Verilog HDL programming?
In Verilog certain type of assignments or expression are scheduled for
execution at the same time and order of their execution is not
guaranteed. This means they could be executed in any order and the
order could be change from time to time.
A Verilog race condition occurs when two or more statements that are
scheduled to execute in the same simulation time-step, would give
different results when the order of statement execution is changed, as
permitted by the IEEE Verilog Standard.
To avoid race conditions, it is important to understand the scheduling
of Verilog blocking and nonblocking assignments.

2. Is there a difference between the instructions

always #1 a=!a;
and
forever #1 a=!a;
If yes, what is/are their difference/s?
An always construct declares a permanent thread of execution. At time
0, it starts the thread by executing the procedural statement that is part
of the construct (in this case the begin/end block). When the procedural
statement finishes, it executes it again. This thread of execution exists
for the entire simulation and can never be terminated.
An initial construct declares a thread of execution that exists as long as
there are procedural statements to execute. At time 0, it starts the
thread by executing the procedural statement that is part of the
construct (in this case the forever statement). When the procedural
statement finishes, the thread terminates. In this case the thread does
not terminated because the looping statement never ends.
More specifically, there are a few more things you can do with a forever
statement that you cannot easily do with an always construct. By adding
a delay before executing the forever statement you can introduce a
phase shift.
As a looping statement, you can break out of a forever loop, and if you
name the statement, you can disable it. So, you can terminate the

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 process created by an initial block. There is no way to terminate the
process created by an always block.

3. Differentiate the selection constructs used in Verilog with those used in

high-level languages (C++, C#, etc).
A selection construct is a programming construct supported by C# that
controls the flow of a program. It executes a specific block of statements
based on a Boolean condition, that is an expression returning true or
false. The selection constructs are referred to as decision-making
constructs. Therefore, selection constructs allow you to take logical
decisions about executing different blocks of a program to achieve the
required logical output.
Both languages support the same selection construct. However, in
Verilog, the if-else statement controls the execution of other
statements. In programming language like C, if-else controls the flow of
program. When more than one statement needs to be executed for an
if condition, then we need to use begin and end. As for case construct
as alternative for selection construct, syntax varied by a little, and two
case variations exist in Verilog: casex and casez.

4. How are multiple always@ blocks executed within a given program?

An always block is used to execute a block of statements depending
upon if the values of any of the inputs to the block (called a sensitivity
list) changes.
If we have multiple always blocks inside one module, then all the blocks
(i.e. all the always blocks) will start executing at time 0 and will continue
to execute concurrently. Sometimes this is leads to race condition, if
coding is not done properly.

5. What are sensitivity lists? How do they affect the entire behavioural
model description of a program?
A simple always block runs forever it means as it touches the “end”
again starts from beginning. The sensitivity list controls when the
statements in an always block are evaluated. The sensitivity list must
include all input signals used by an always block to properly model
combinational logic. It is easy to inadvertently omit an input signal from
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 the sensitivity list, which can lead to simulation and synthesis
mismatches.

6. Why does the register operation of state transitions use a non-blocking

operator (<=)?
Nonblocking statements allow you to schedule assignments without
blocking the procedural flow. You can use the nonblocking procedural
statement whenever you want to make several register assignments
within the same time step without regard to order or dependence upon
each other. It means that nonblocking statements resemble actual
hardware more than blocking assignments.
Blocking assignment executes "in series" because a blocking assignment
blocks execution of the next statement until it completes. Therefore,
the results of the next statement may depend on the first one being
completed.
Non-blocking assignment executes in parallel because it describes
assignments that all occur at the same time. The result of a statement
on the 2nd line will not depend on the results of the statement on the
1st line. Instead, the 2nd line will execute as if the 1st line had not
happened yet.
"=" executes code sequentially inside a begin/end, whereas
nonblocking "<=" executes in parallel.

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