Case

Study
• 9 axis IMU (Inertial Measurement Unit)
• Accelerometer

Communication Protocols • Gyroscope

• Magnetometer
Notes and/or Reference • One of the only real MEMS (MicroElectroMechanical Systems)
Joe Steinmeyer applications that has gone full-scale (others might be TI’s DMD,
gyroscopes, microphones, some microfluidics, Si resonators,
6.111 October 24, 2017
Piezoelectrics from Inkjets, etc…)

6.111 Fall 2017 1 6.111 Fall 2017 3

Overview of Today Accelerometers

• How does an Accelerometer Work and how can we use it? • First MEMS accelerometer: 1979
• Position of a proof mass is capacitively sensed and decoded to
• Discussion of Particular Chip-to-Chip Communication Protocols provide acceleration data

• Discussion of Device-to-Device Communication Protocols Proof Mass

Spring Spring

%
Measure
Capacitance via
!" → Δ% Impedance
Divider

6.111 Fall 2017 2 6.111 Fall 2017 SEM of two-axis accelerometer 4

Uses of Acceleration Measurements:
Bring in Gyroscopes

Angular velocity (arb. units)

• Acceleration can be used to detect motion
• (pedometer, free-fall/drop detection):
• Provide Direct Angular Velocity
which we can integrate to get angle
!1 = !.2 + !'2 + !"2 Accelerometer directions
+X, +Y, +Z • Very little high-frequency noise, but
Chip lots of low frequency noise (Gyros
• Use gravity and trig to find orientation: drift like crazy)
−!.

!"

angle (arb. units)

&' = tan,- −!"
!. Gyro readings are “around” the
axis they refer to (use right-hand
rule):
time (seconds)

6.111 Fall 2017 0 5 6.111 Fall 2017 7

Gyro Operation Resonating

Problems • Resonating Proof Mass
Spring Spring
Proof Mass
• Accelerometers have huge amounts of high-frequency noise
• Electrostatic Drive
• To fix, usually Low Pass Filter the raw signal (IIR shown below) • Piezoelectric Drive Measure Measure
• This cuts down on frequency response though L • Turning out-of-plane:
Capacitance via
Impedance
Capacitance via
Impedance
Divider Divider
• Proof-mass fights the turn
• Detect deviation via capacitance
!" [6 − 1] • Do this for all three axes
&' [6] = &' [6 − 1]9 + 1 − 9 tan,- Rotation of Device

!. [6 − 1]

!. X acceleration 0<9<1 Filter Coefficient Changes in capacitance

measured at different
!" z acceleration
&' Angle estimate around y axis
points
6.111 Fall 2017 6 6.111 Fall 2017 8
Scale not accurate/nor design details
How to use Gyro Readings: Merge the signals
• Because of Drift (low frequency noise/offset) you want to • Complementary Filter:
avoid doing much long-term integration with a gyro reading
• Having beta less than unity ensures any angle that comes !" [6 − 1]
from gyro reading will eventually disappear, but in short
&' 6 = 9 &' 6 − 1 + >0' [6 − 1] + 1 − 9 tan,-
!. [6 − 1]
term it will dominate
• Depending on time step: 0<9<1 Filter Coefficient 0' Gyro y reading !. X acceleration

&= 6 = 9&= 6 − 1 + >0' [6 − 1] 9 ≈ 0.95 good starting point

!" z acceleration
> Time Step

0<9<1 Filter Coefficient 0' Gyro y reading

• Could also do Kalman Filter (LQE) if desired (or others)

9 ≈ 0.95 starting point
6.111 Fall 2017
> Time Step
9 6.111 Fall 2017 11

What to do? How to get Access to the signals in first place?

• Using only accelerometer, leaves us blind to motion/change in the • Some accelerometers are analog out (can therefore read them with
short term but fine in the long-term an A-to-D converter) (ADXL335, for example)
• These have limited functionality…and also it is analog so there’s the
• Using only gyroscope, leaves us blind in the long term, but good in whole noise issue....which is not nice
the short term • Most flavors of sensors are digital

• What to do?

6.111 Fall 2017 10 6.111 Fall 2017 12

 MPU-9250
Serial and Parallel at High Level
• 3-axis Accelerometer (16-bit readings)
• 3-axis Gyroscope (16-bit readings) Parallel Link: Serial Link:
• 3-axis Magnetic Hall Effect Sensor (Compass) (16 bit readings)
• SPI or I2C communication (!)…no analog out
• On-chip Filters (programmable)
Board: $5.00 from Ebay
• On-chip programmable offsets Chip: $3.00 in bulk
• On-chip programmable scale!
• On-chip sensor fusion possible (with quaternion output)!
• Interrupt-out (for low-power applications!)
• On-chip sensor fusion and other calculations (can do orientation math on-
chip or pedometry even) Currently pushing 10-30Gb/s …
• So cheap they usually aren’t even counterfeited! J
6.111 Fall 2017 13 6.111 Fall 2017 15

Serial Communications
Common Chip-Chip Communication Protocols • Sending information one bit at a time vs. many bits in parallel
• Serial: good for long distance (save on cable, pin and connector cost,
easy synchronization). Requires “serializer” at sender, “deserializer” at
• Parallel (not so much anymore). receiver
• Parallel: issues with clock skew, crosstalk, interconnect density, pin
count. Used to dominate for short-distances (eg, between chips).
• Serial (UART) (still common in some communication and GPS devices) • BUT modern preference is for parallel, but independent serial links (eg,
PCI-Express x1,x2,x4,x8,x16) as a hedge against link failures.
• A zillion standards
• SPI (Serial Peripheral Interface) very common • Asynchronous (no explicit clock) vs. Synchronous (CLK line in addition
to DATA line).
• Recent trend to reduce signaling voltages: save power, reduce
• I2C (Inter-Integrated Circuit Communication) very common transition times
• Control/low-bandwidth Interfaces: SPI, I2C, 1-Wire, PS/2, AC97
• Networking: RS232, Ethernet, T1, Sonet
• Computer Peripherals: USB, FireWire, Fiber Channel, Infiniband, SATA,
• I2S (Inter-Integrated Circuit Sound Bus) common Serial Attached SCSI

6.111 Fall 2017 14 6.111 Fall 2017 16

Common Chip-Chip Communication Protocols Note on Terminology
• Parallel (not so much anymore). • In device-to-device communication, it is common to have one device
labeled the ”Master” and one labeled the “Slave”…the Master
controls the Slave(s) in these settings.
• Serial (UART) (still common in some communication and GPS devices)
• Trace history of this naming terminology back to 1940s
• SPI (Serial Peripheral Interface) very common • I’ve seen some alternatives suggested: Leader/Follower,
Primary/Secondary (other ideas?), but this naming scheme persists in
the field and on data sheets
• I2C (Inter-Integrated Circuit Communication) very common
• Movement from this terminology has occurred more readily in
software than hardware…Django has transitioned
• I2S (Inter-Integrated Circuit Sound Bus) common
• Los Angeles actually requested manufacturers to use alternative
6.111 Fall 2017 17
naming scheme as far back as 20036.111 Fall 2017 19

MOSI

Serial (UART) SPI Master

Device
MISO
SCK
Slave
Device

CE/CS
• Stands for Universal Asynchronous Receiver Transmitter • Stands for Serial-Peripheral Interface
• Requires agreement ahead-of-time between devices regarding things • Four Wires:
like clock rate (BAUD), etc… • MOSI: Master-Out-Slave-In
• Two wire communication • MISO: Master-In-Slave-Out
• Cannot really share • SCK: Serial Clock
• (every pair of devices needs own pair of lines) TX/RX • CE/CS (Chip Enable or Chip Select)
Device 2
• Data rate really < 115.2Kbps Device 1 • SCK removes need to agree ahead of time on data rate (from UART)
RX/TX
• High Data Rates: (1MHz up to ~70 MHz clock (bits))

6.111 Fall 2017 18 6.111 Fall 2017 20

 MOSI

SPI Master
Device
MISO
SCK
Slave
Device 1 SPI Example
“Give me a
CE0/CS0 single-ended
reading…” “From your “0001011011” ”We’re done
• Can share MOSI/MISO Bus “Hey MCP3008” channel 1” here. ”
• Addition of multiple slaves requires
additional select wires CS
Slave
• Hardware/firmware for SPI is pretty easy to Device 2
MOSI
implement: X X 1 1 0 0 1 X X X X X X X X X X X X X
CE1/CS1
• Wires are uni-directional
• Classic “duh” sort of approach to digital
MISO …
X X X X X X X X 0 0 0 0 1 0 1 1 0 1 1
communication, but very robust.
SCK

Artix-7 (Master Device) Dialog

6.111 Fall 2017 21 MCP3008 (Slave Device) Dialog 6.111 Fall 2017 23

From MCP3008 Datasheet

SPI Example SPI In Real Life

MCP3008
CMOD-A7-35T
• Here I am talking to the same chip I CS
was daydreaming about talking to on
the previous slide.
CS • Dreams do come true SCK

MOSI
• I’m saying, give me your measurement 11001000001011011
MOSI
X X 1 1 0 0 1 X X X X X X X X X X X X X on Channel 1, and it is responding
Here I am talking to a MCP3008 10 bit ADC
with 10’b0001011011 mapped to 3.3V
MISO … or 0.293 V MISO
X X X X X X X X 0 0 0 0 1 0 1 1 0 1 1

SCK

6.111 Fall 2017 22 6.111 Fall 2017 24

 MOSI
On i2C Multiple Devices Require Same # of
SPI* Master MISO Slave

Wires
Device Device
SCK
CE0/CS0
• Six Wires: D/C • Devices come with their own
• MOSI: Master-Out-Slave-In RES ID numbers (originally a 7 bit Master SDA
Device Slave
• MISO: Master-In-Slave-Out value but more modern ones Device 1
• SCK: Clock have 10 bits)…allows SCL
• CE/CS (Chip Enable or Chip Select) potentially up to 2^7 devices or
• RES: Reset Device 2^10 on a bus (theoretically
• D/C: Data/Command (often seen in devices where you need
anyways)
to write tons of data (i.e. a display) Slave
• Three/Two Wires: • ID’s are specified at build, Device 2

• If a device has nothing to say, drop MISO: usually several to choose from
and you select them by pulling
• If you assume only one device on bus drop CE/CS
external pins HI or LOW
6.111 Fall 2017 25 6.111 Fall 2017 27

i2C More to story (need pull-up resistors)

• i2C uses an open drain
• Stands for Inter-Integrated Circuit communication • Meaning both Master and Slave
• Invented in 1980s Device are either:
• Two Wire, One for Clock, one for data (both directions) • LOW
• High-Impedance
• Usually 100kHz or 400 kHz clock (newer versions go to 3.4 MHz) 3.3V 3.3V
• Need external pull-up resistors
4.7kΩ 4.7kΩ
Master SDA Slave
Device Device
Master SDA Slave
Device Device
SCL

SCL

6.111 Fall 2017 26 6.111 Fall 2017 28

 Tri-State i2C Operation
• inout cannot be a reg ever, ever…it is closer to a • Data is conveyed on SDA (Either from Master or Slave depending on
wire...usual way to work with them is the point during communication)
following:
• SCL is 50% duty cycle
In verilog… • SDA generally changes on falling edge of SCL (isn’t required)
inout sda;
• SDA sampled at rising edge of SCL
reg sda_val;
• Master is in charge of setting SCL frequency and driving it

assign sda = sda_val? 1’bz: 1’b0;

6.111 Fall 2017 29 6.111 Fall 2017 31

3.3V

As a result: Meanings I: (Start, Stop, Sampling)

4.7kΩ
inout sda;
Master Releases Bus (STOP)
reg sda_val;
By pulling SDA HI while SCL is HI
assign sda = sda_val? 1’bz: 1’b0; SDA Master Claims Bus (START)
Idle State By pulling SDA LOW while SCL is HI
SDA and SCL sit HI
Wanna write to SDA? SDA in
sda_val <= 0; //or 1 if desired :wq
SDA: HI

Wanna read to SDA? LO

VGS
sda_val <= 1;
//wait clock cycle…
some_reg <= sda; //read from input
Data/State on SDA transitions
SCL: HI @ negedge of SCL*
Mode Master Slave LO
Master Transmit HiZ (HI) or LOW HiZ (listening)
Slave ACK/NACK HiZ (listening) HiZ (HI) or LOW Data from SDA sampled @ posedge of SCL
Slave Transmit HiZ (listening) HiZ (HI) or LOW
Master ACK/NACK HiZ (HI) or LOW 6.111 Fall 2017
HiZ (listening) 30 6.111 Fall 2017 *not specified but probably easiest spot to do
32
Meanings II Address Meanings IV (ACK/NACK)
• First thing sent by Master is 7 bit address (10 bit in more modern • After every 8 bits, it is the listener’s job to acknowledge or not
i2C…has some leading 11111’s in it..don’t worry about that) acknowledge the data just sent (called an ACK/NACK)
• Transmitter pulls SDA HI and listens for next reading (@posedge of
• If a device on the bus possesses that address, it acknowledges SCL):
(ACK/NACK=0) and it becomes the slave • If LOW, then receiver acknowledges data
• If remains HI, no acknowledgement
• Transmitter/Receiver act accordingly
• All other devices (other than Master/Slave Devices) will ignore until
STOP signal appears later on.

6.111 Fall 2017 33 6.111 Fall 2017 35

Meanings III (Read/Write Bit) Meanings V

• For Master Device to write to Slave Device:
• After sending address, a Read/Write Bit is specified by Master on • START
SDA: • Send Device Address (with Write bit)
• Send register you want to write to
• If Write (0) is specified, the next byte will be a register to write to, and • Send data…until you’re satisfied
following bytes will be information to write into that register • STOP
• If Read (1) is specified, the Slave will start sending data out, with the Master • For Master Device to read from Slave Device:
acknowledging after every byte (until it wants data to not be sent anymore) • START
• Send Device Address (with Write bit)
• Send register you want to read from
• ReSTART communication
• Send Device Address (With Read bit)
• Read in bits
• After every 8 bits, it is Master’s job to acknowledge Slave…continued acknowledgement leads
to continued data out by Slave.
• Not-Acknowledge says “no more data to Slave”
• STOP leads to Master ceasing all communication
6.111 Fall 2017 34 6.111 Fall 2017 36
 State-Machine
Implementing i2C on FPGA with MPU9250: Implementation of
• Made master i2C controller in Verilog i2C Master
• Redundant states (repeated
• Used MPU9250 Data sheet: 42 pages (basic functionality, timing READ/WRITE, ADDRESS, ACK/NACK,
requirements, etc…) etc…)
• MPU9250 Register Map: 55 pages
• ARM manual describes ~20 state FSM

• Included code on site for

reference/starting point

• Diagram: on next page for reference

6.111 Fall 2017 37 6.111 Fall 2017 39

…200 more lines

State-Machine STOP IDLE

START1 ACKNACK1A
IDLE

Implementation of ADDRESS1 READWRITE1

i2C Master 7x
ACKNACK1C
NACK

• Continuously reads 2 bytes NACK ACK

READ3
starting at the 0x3B register ADDRESS2
(X accelerometer data) 8x
ADDRESS3
REGISTER1
• Print out value in hex in LEDs ACK4
READ4 7x
• 34 States 8x
START2
• Clocked at 200kHz, and creates
100 kHz SCL READ2 ACKNACK3A
ADDRESS4
REGISTER2

• Change SDA on falling edge of ACK

SCL 8x
• Sample SDA on rising edge of ACKNACK3C

SCL READ1
READWRITE2 ACKNACK2C ACKNACK2A

6.111 Fall 2017 38 ACK 6.111 Fall 2017 40

IDLE IDLE
NACK NACK
 Communication Part
Communication Part VCC

VCC GND
SCL

GND
SCL SDA
Nexys4 “I’m here. Sounds good” “OK” “Hey, 0x68…” MPU9250
SDA “Hey, 0x68…” “For sure”
”More, please”
“Different thought” “Read to me
MPU9250 “Look at your
“I wanna tell from where
Nexys4 0x6B register” “0x6D”
“I claim this bus” you something” you’re looking”

1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0
SDA
SDA
01010101010101010101010101010101010101110101010101010101010101010101010101010 … 01010101010101010101010101010101010101110101010101010101010101010101010101010 …
SCL
SCL
6.111 Fall 2017 41 Nexys4 (Master Device) Dialog 6.111 Fall 2017
MPU9250 (Slave Device) Dialog
43

Communication in Real-Life: Data being sent from MPU9250

Communication Part
VCC

GND
SDA = Yellow
SCL

SDA
Nexys4 Acknowledge=0 ReStart MPU9250
Write=0 Read=1 Acknowledge=0
Device Address (0x68) Device Address (0x68) Data Read In
Start Device Register (0x3B)
1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 SCL = Purple
SDA

SCL
01010101010101010101010101010101010101110101010101010101010101010101010101010 …
6.111 Fall 2017 42 6.111 Fall 2017 44
Triggered on leaving IDLE state
 Running and reading X acceleration: Master Slave
I2s (Inter-IC Sound Bus) SDA
WS

• Not related to i2C at all SCL

• Intended for Digitized Stereo Data

• Three Wires:
• SDA: Serial Data (The actual music)
• WS: Word Select (Left/Right Channel)
HOOKUP • SCL: Serial Clock (For Synchronization)
• Push-Pull Driving (like SPI…no need for pull-up resistors)
Horizontal: Vertical: • Data sent MSB first
16’hFD88 = 16’b1111_1101_1000_1000 (2’s complement) 16’h4088 = 16’b0100_0000_1000_1000 (2’s complement)
Flip bits to get magnitude: 16’b0000_0010_0111_0111 Leave bits to get magnitude: 16’b0100_0000_1000_1000 • Clock-rate dictated by sample rate (44.1kHz @16 bits per channel /w 2
=-315 =+16520
Full-scale (default +/- 2g) Full-scale (default +/- 2g)
channels = ~1.4 MHz for example
-315/(2**15)*2g = -0.02g J makes sense 6.111 Fall 2017 -16520/(2**15)*2 = +1.01g J makes sense! 45 6.111 Fall 2017 47

Clock-Stretching (Cool part of i2C!!!) ! i2S

• Normally Master drives SCL, but since Master drives SCL high by going
hiZ, it leaves the option open for Slave to step in and prevent SCL
from going high by pulling SCL LOW
Master wanted to pull SCL HI but slave
prevents by pullLOW
(red never happens)

SCL:

Once Slave goes HiZ again, Master

picks back up on SCL

• Allows Slave a way to buy time/slow down things (if it requires

multiple clock cycles to process incoming data and/or generate
output) 6.111 Fall 2017 46 6.111 Fall 2017 48
Implementation Which to Choose?
• You’ve built a UART/serial module already…it was pretty short/easy • SPI is generally easier and more flexible to implement, but only
• Vivado has IP cores for i2C Master and i2S Masters certain devices use it since it takes up a lot of pins (and pins are
expensive/limited)
• SPI is much more open to interpretation and loose on its specs so no
default core that I can find: • ”Slow” and “Fast” data rates are relative too…i2C is not as much of a
• I put some generic skeleton code on github/site with a FIFO buffer that can compromise now as it was fifteen years ago, particularly with high-
get folks started if they need it. speed i2C (or even now that 400 kHz rates are common)
• I put/will put that i2C MPU9250 code on the site as well • Remember, these are all meant for chip-to-chip communications!
• Check out the example i2C code from this lecture for the IMU, and a
generic SPI master I wrote up as well…see if you can add clock-
stretching! (not required)
6.111 Fall 2017 49 6.111 Fall 2017 51

Compare and Contrast? Going Between boards

• Generally the fewer the wires the more rigid the protocol • Previous protocols are meant for device-to-device communication
• SPI can be very flexible and high speed (have only 10 bits to send? No • There is no cabling standard for these protocols
problem…send 10!...can’t do that do that with i2C…need to zero-pad • Distances are not specified for i2C, SPI, i2S, but think in terms of
up to the next full byte (16 bits) inches
• In terms of implementation, generally with communication protocols, • Open-Drain protocols are particularly susceptible to parasitics so keep
the more wires, the easier the protocol/less overhead leads short where possible!
• To go between devices we must use other protocols!

6.111 Fall 2017 50 6.111 Fall 2017 52

 RS232 (aka “serial port”) PS/2 Keyboard/Mouse Interface
• 2-wire interface (CLK, DATA), bidirectional transmission of
• Labkit: simple bidirectional data connection with computer. serial data at 10-16kHz
• Characteristics • Format
• Large voltages => special interface chips • Device generates CLK, but host can
(1/mark: -12V to -3V, 0/space: 3V to 12V) request-to-send by holding CLK low
• Separate xmit and rcv wires: full duplex for 100us
• Slow transmission rates (1 bit time = 1 baud); most interfaces support standardized • DATA and CLK idle at “1”, CLK starts when
baud rates: 1200, 2400, 4800, 9600, 19.2K, 38.4K, 57.6K, 115.2K there’s a transmission. DATA changes on
Figures from digilentinc.com

• Format CLKé, sampled on CLKê

• Wire is held at 1/mark when idle • 11-bit packets: one start bit of “0”, 8 data bits (LSB first), odd
• Start bit (1 bit of “0” at start of transmission) parity bit, one stop bit of “1”.
• Data bits (LSB first, can be 5 to 8 bits of data) • Keyboards send scan codes (not ASCII!) for each press, 8’hF0
• Parity bit (none, even, odd) followed by scan code for each release
• Stop bits (1, 1.5 or 2 bits of 1/mark at end of symbol) • Mice send button status, Δx and Δy of movement since last
• Most common 8-N-1: eight data bits, no parity, one stop bit transmission

6.111 Fall 2017 53 6.111 Fall 2017 55

RS232 interface PS/2 Keyboard/Mouse Interface

• Transmit: easy, just build FSM to
generate desired waveform with
correct bit timing • 2 signal wire interface (CLK, DATA), bidirectional
• Receive: transmission of serial data at 10-16kHz
• Want to sample value in middle of each
bit time
• Oversample, eg, at 16x baud rate
• Look for 1->0 transition at beginning of
start bit
• Count to 8 to sample start bit, then
repeatedly count to 16 to sample other
bits
Figure from
• Check format (start, data, parity, stop) http://www.arcelect.com/rs232.htm
before accepting data.
Should look familiar from Lab 2!
6.111 Fall 2017 54 6.111 Fall 2017 Figures from digilentinc.com 56
 IDE Bus – Serial ATA (SATA) USB: Universal Serial Bus
• More defined layers than your other things we’ve seen
SATA
• The 2000 version of USB spec was 570 pages long
2-wire (+,-) for high-speed

SATA 1: 1.5Gb/s
SATA 2: 3Gb/s • Current USB 3.2 (9/22/2017 release!...so new! so fresh!)
SATA 3: 6Gb/s • spec is 103 MB zip file*
• Approximately 8,000 pages long at this point
• I’ll summarize in a few slides

*and hosted on web page that has painfully slow DL speeds and looks like it is from 2000
6.111 Fall 2017 57 6.111 Fall 2017 59

USB: Universal Serial Bus How is Data Transmitted in USB (High Level):
• USB 1.0 (12 Mbit/s) introduced in 1996
• USB 2.0 (480 Mbit/s) in 2000 • Communication uses handshakes to establish capable/expected data
• USB 3.0 (5 Gbit/s) in 2012 rates
• USB-C 2016.
• Host device (computer for example), assigns connected devices
• USB 3.2 (30 Gbit/s) in July 20, 2017
• Created by Compaq, Digital, IBM, Intel, Northern Telecom and Microsoft. Credit: Reddit
temporary IDs on shared bus.
• Uses differential bi-direction serial communications • Packets of information, including headers, payloads, and error checks
(CRC5, CRC16, and CRC32 are used) are sent between host and client
devices
Type A USB 2.0 – 4 pins

Type A & B Pinout USB 3.0

Mini/Micro Pinout
6.111 Fall 2017 58 6.111 Fall 2017 60
 How is Data Transmitted in USB (Bit Level): Potential Problems
• USB uses twisted wire pairs and there is no CLOCK wire • If we all followed the laws life would be grand
• All data is transmitted using Non-Return-Zero-Inverted (NRZI) encoding: • Not everyone can read all 8,000 pages
• A 0 is encoded as a value change • Not everyone wants to read all 8,000 pages
• A 1 is encoded by no change
• Difference between 5V and 20V going into your laptop
• After initial synchronization byte, the receiver extracts the clock from the on- is now based on software handshakes between two
average probability of 0’s in the data (which give transitions) using local devices.
oscillator and Phase-Locked Loops (Maybe talk about in Lecture 15 because it is
really cool actually) • Do you trust your devices?
• Avoid long stretches of 1’s by bit-stuffing (shoving 0’s in to avoid periods of time • Solution is now to do hardware verification prior to any
where no transitions happen)…similar to ether protocols power delivery using table of approved-devices for via
128 bit encryption (mid 2016)
• Capable of up to 30 Gbit/s
• ~2 HD movies per second 6.111 Fall 2017 61
• It’ll be interesting to see how quickly this gets hacked
6.111 Fall 2017 63

USB - C Getting data back to the board…

• Universal connector for power and data – first product MacBook Air – one and only port!
• Symmetrical – no orientation (Good for 10,000 insert/withdrawals…10 kiloinserts)
• Supports DisplayPort, HDMI, power, USB, and VGA. Uses differential bi-direction serial
communications
• Supplies up to 100W power (5V @ up to 2A, 12V @ up to 5A, and 20V @ up to 5A)
• Voltage dictated by software handshake, etc..
• New adapters required for DisplayPort, HDMI, power, USB, and VGA – omg!

6.111 Fall 2017 62 6.111 Fall 2017 64

FTDI Chipsets Human Interface Device Classes
• Future Technology Devices International Ltd (FTDI) is a Scottish • Complex, yet implementable communication protocol that utilizes
Electronics firm that makes USB interfaces widely accepted protocol:
• They produce devices that convert between USB and: • Have a device and/or FPGA directly run implement that part of the
• UART USB stack
• SPI • Can implement in ~10 state FSM or so
• I2C
• Appear as a “mouse” or a “keyboard” or a “webcam”, etc…
• Parallel Out
• Extremely common • Medium speeds…really need specialized hardware for the super
speeds

6.111 Fall 2017 65 6.111 Fall 2017 67

The Great FTDI Bricking of 2014 RFID: Radio Frequency Identification Like in MIT IDs:

• Used to provide remote

• From the beginning of USB to only recently, most USB devices used interrogation/identification
FTDI-based chip sets to interface (source of those annoying FTDXX.h • Frequency bands:
library issues you’d always see in Windows) • 125 - 134 kHz [MIT ID]* Transmitting
• Your optical mouse would have some circuit and it would communicate • 13.56 MHz [US Passports]* antenna
internally with UART…then the FTDI chip would convert to USB • 400 – 960 MHz UHF
• Dozens of “clones” were built to work with that software, these [EZPASS 915mhz ~ 1 mw]**
clones often times selling for a small fraction of the cost of the • 2.45 GHz
original FTDI chips • 5.8 GHz
• In 2014 FTDI they released a software update, included in most
Windows Service Packs that bricked all “non-genuine” devices * excitation/broadcast powered
** battery powered Battery
• Turned out a lot of ”legit” products were using counterfeits/clones EZ Pass Internals
6.111 Fall 2017 66 6.111 Fall 2017 68
*http://groups.csail.mit.edu/mac/classes/6.805/student-papers/fall04-papers/mit_id/#specs
 125khz RFID Next Monday
• Potpourri…
• FFTs
• Bluetooth, BLE discussion
• Maybe PLLs
• Some other stuff

Receiver
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125khz transmitter signal

6.111 Fall 2017 69 6.111 Fall 2017 71

MIT RFID Stimulating and Receiving Coils

• 125 kHz carrier

• 62.5 kHz modulating wave
phase-shifts every 16
FFT of Pickup on Receiving
cycles: Coil while Stimulating Coil
• C shift indicates a 1 has 125 kHz driven into it
and NO CARD in between
• No shift indicates a 0
(Spike is 125 kHz centered)
• …so we’ve got:
• Phase-shift-encoded Non- FFT of Pickup on Receiving Coil while
Return-to-Zero-Mark Stimulating Coil has 125 kHz driven
Encoding (NRZ-M) into it and CARD is in between
(LOOK AT THAT SIDEBAND
6.111 Fall 2017
ACTION!!!) 70