ARM Version (History)

ARM CORTEX
❖ CORTEX A: Application processors which are designed to handle complex
applications such as high end embedded operating systems.(Eg- Symbian,
Linux,windows embedded)
➢ requiring the highest processing power, virtual memory system
➢ Required support with memory management units (MMUs)
➢ Required enhanced Java support (optional) and a secure program execution
environment.
➢ Eg: Smart phones, Electronics wallet.
 ARM CORTEX
❖ CORTEX R: Real-time, high-performance processors targeted primarily at
the higher end of the real-time market.
➢ Used in applications which requires high processing power and high reliability & low
latency is important.
➢ Eg: high-end breaking systems and hard drive controllers

❖ CORTEX M: Processors targeting for low-cost applications

➢ which processing efficiency is important and cost
➢ power consumption, low interrupt latency
➢ Eg: industrial control applications, real-time control systems
Architecture Developmemt
CORTEX processor Vs MCU
Instruction set Architecture (Thumb2)
Instruction set Architecture (Thumb2)
❖ Thumb-2 is a superset of the previous 16-bit Thumb instruction set, with
additional 16-bit instructions alongside 32-bit instructions.
❖ It allows more complex operations to be carried out and allows higher
efficiency by reducing the number of states switching between ARM state
and Thumb state.
❖ Focused on small memory system devices such as microcontrollers.
❖ Hardware divide & more number of multiply instructions are also
available.
Instruction set Architecture (Thumb2)
Note:

Cortex-M3 supports only the Thumb-2 (and traditional Thumb) instruction set
so it is not backward compatible with traditional ARM processors.
Cortex M3 Features
Cortex-M3 addresses the requirements for the 32-bit embedded processor
market din following ways

❖ Greater performance efficiency:

➢ allowing more work to be done without increasing the frequency or power requirements
❖ Low power consumption:
➢ enabling longer battery life, especially critical in portable products including wireless
networking applications.
❖ Improved code density
➢ ensuring that code fits in even the smallest memory footprints
❖ Enhanced determinism:
➢ guaranteeing that critical tasks and interrupts are serviced as quickly as possible and in a
known number of cycles
Cortex M3 Features
❖ Lower cost solutions:
➢ reducing 32-bit-based system costs close to those of legacy 8-bit and 16-bit devices and
32-bit microcontrollers to be priced at less than US$1.
❖ Ease of use:
➢ providing easier programmability and debugging for the growing number of 8-bit and 16-
bit users migrating to 32 bits
❖ Wide choice of development tools:
➢ from low-cost or free compilers to full-featured development suites from many
development tool vendors
Cortex M3 Applications
❖ Low-cost microcontrollers
➢ ease-of-use advantages enable embedded developers to migrate to 32-bit systems and
develop products with the ARM architecture.
❖ Automotive
➢ high-performance efficiency and low interrupt latency, allowing it to be used in real-time
systems.
❖ Data communications
➢ More no of multiply and bit field instructions Cortex-M3 ideal for many communications
applications, such as Bluetooth and ZigBee.
❖ Industrial control
➢ fast response, and reliability nd enhanced fault-handling features Cortex-M3 is suitable
for this area.
❖ Consumer products
➢ small processor, highly efficient and low in power as well as supports MPU
Cortex M3 Data flow diagram
Cortex M3 Data flow diagram
● The Cortex™-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-
bit register bank, and 32-bit memory interfaces.
● The processor has a Harvard architecture, which means that it has a
separate instruction bus and data bus.
● For complex applications that require more memory system features, the
Cortex-M3 processor has an optional Memory Protection Unit (MPU)
● The Cortex-M3 processor includes a number of fixed internal debugging
components. These components provide debugging operation supports
and features, such as breakpoints and watchpoints.
Cortex M3 Registers
Cortex M3 Registers
❖ Cortex-M3 processor has registers R0 through R15.

General-Purpose Registers (R0–R12)

R0–R12 are 32-bit general-purpose registers for data operations. Divided into
low registers (R0–R7) & high registers (R8-R12)

Stack Pointers (R13 )

There are two stack pointers (R13) They are banked so that only one is visible
at a time.

This duality allows two separate stack memories to be set up. When using the
register name R13, you can only access the current SP
Cortex M3 Registers
1. Main Stack Pointer (MSP): The default stack pointer, used by the operating
system (OS) kernel and exception handler and and all application codes
that require privileged access.
2. Process Stack Pointer (PSP): Used by user application code

Eg: PUSH {R0} ; R13= R13-4 Then memory [R13]=R0

POP {R0} ; R0=memory R13 Then R13=R13+4

We can PUSH or POP multiple registers in one instruction

Eg: PUSH {R0-R7, R12, R14} ; Store registers in stack

POP {R0-R7, R12, R14} ; Restore registers from stack

Cortex M3 Registers main ; Main program

Link Register (R14) ...

❖ R14 is the link register (LR). Inside BL function1 ; Call function1 using Branch
with Link instruction.
an assembly program, you can
; PC = function1 and
write it as either R14 or LR
❖ When a subroutine is called, the ; LR = the next instruction in main

return address is stored in the link ...

register
function1

... ; Program code for function 1

BX LR ; Return
Cortex M3 Registers
Program Counter (R15)

❖ Hold address of next instruction to be executed.This register can be

written to control the program flow.
❖ Because of the pipelined nature of the Cortex-M3 processor, when you
read this register, you will find that the value is different than the location
of the executing instruction, normally by 4.
➢ Eg: 0x1000 : MOV R0, PC ; R0 = 0x1004
Cortex M3 Registers
Cortex M3 Registers
❖ Special registers can only be accessed via MSR and MRS instructions; they
do not have memory addresses.
➢ Eg: MRS <reg>, <special_reg>; Read special register
➢ Eg1; MSR <special_reg>, <reg>; write to special register
Cortex M3 Registers (SFR)
1. Program status register (Source: Definitive guide to ARM cortex M3)
PSR
❖ The three PSRs can be accessed together or separately using the special
register access instructions MSR and MRS. When they are accessed as a
collective item, the name xPSR is used

Eg: MRS r0, APSR ; Read Flag state into R0

MRS r0, IPSR ; Read Exception/Interrupt state

MRS r0, EPSR ; Read Execution state

MSR APSR, r0 ; Write Flag state

One PSR Can be written as

Eg: MRS r0, PSR ; Read the combined program status word

MSR PSR, r0 ; Write combined program state word

Bit Fields in PSR
Bit Description

N Negative

Z Zero

C Carry/borrow

V Overflow

Q Sticky saturation flag

ICI/IT Interrupt-Continuable Instruction (ICI) bits, IF-THEN instruction status bit ;

T T Thumb state, always 1; trying to clear this bit will cause a fault exception

Exception number Indicates which exception the processor is handling

MASK Registers (SFR)
Register Name Operation

PRIMASK A 1-bit register, when this is set, NMI and the hard fault exception; all other
interrupts and exceptions are masked. The default value is 0 (No masking)

FAULTMASK A 1-bit register, when this is set, it allows only the NMI, and all interrupts
and fault handling exceptions are disabled. The default value is 0 (No
masking)

BASEPRI A register of up to 8 bits It defines the masking priority level. When this is
set, it disables all interrupts of the same or lower level.
default value is 0.
MASK Registers (SFR)
In assembly language, the MRS and MSR instructions are used. For example

Eg: MRS r0, BASEPRI ; Read BASEPRI register into R0

MRS r0, PRIMASK ; Read PRIMASK register into R0

MRS r0, FAULTMASK ; Read FAULTMASK register into R0

MSR BASEPRI, r0 ; Write R0 into BASEPRI register

MSR PRIMASK, r0 ; Write R0 into PRIMASK register

MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register

Control Registers (SFR)
The control register is used to define the privilege level and the SP selection.
This register is 2 bit wide
Bit Function

CONTROL[1] Stack status:

1 = Alternate stack is used
0 = Default stack (MSP) is used
If it is in the thread or base level, the alternate stack is the PSP. There is no
alternate stack for handler mode, so this bit must be 0 when the processor is in
handler mode

CONTROL[0] 0 = Privileged in thread mode

1 = User state in thread mode
If in handler mode (not thread mode), the processor operates in privileged
mode
Control Registers (SFR)
❖ Control [1]: This bit is writable only when the core is in thread mode and
privileged. In the user state or handler mode, writing to this bit is not
allowed.
❖ Control [0]: This bit is writable only in a privileged state. Once it enters the
user state, the only way to switch back to privileged is to trigger an
interrupt and change this in the exception handler

In assembly language, the MRS and MSR instructions are used

Eg: MRS r0, CONTROL ; Read CONTROL register into R0

MSR CONTROL, r0 ; Write R0 into CONTROL register

MASK Registers (SFR)
❖ A number of functions are available in the device driver libraries provided
by the microcontroller vendors. CMSIS functions are available in CMSIS
compliant device driver libraries
Operation modes
Source: Definitive guide to Cortex M3
Operation modes
❖ ARM cortex M3 supports two operating
modes and two privilege levels.
❖ If processor is running in thread mode,
it can be in a privileged or user level.
❖ handlers can only be in the privileged
level
❖ When the processor exits reset, it is in
thread mode, with privileged access
rights
Operation modes
User Level (Thread Mode)

❖ access to the system control space that is part of the memory region for
configuration registers and debugging components are blocked.
❖ instructions that access special registers (such as MSR, except when
accessing APSR) cannot be used.
❖ If a program running at the user access level tries to access SCS or special
registers, a fault exception will occur.
❖ The core in a privileged access level can switch the program into the user
access level using the control register. BIT [0]-1
Operation modes
❖ When an exception takes place, the processor will always switch to a
privileged state and return to the previous state when exiting the
exception handler
❖ user program cannot change back to the privileged state directly by
writing to the control register.
❖ It has to go through an exception handler that programs the control
register to switch the processor back into privileged access level when
returning to thread mode
Operation modes
Operation modes (Switching at interrupt)
Operation modes (Switching at interrupt user)
Operation modes
Operation modes (Switching at interrupt user)
❖ The support of privileged and user access levels provides a more secure
and robust architecture.
❖ If a user program goes wrong, it will not be able to corrupt control
registers in the Nested Vectored Interrupt Controller (NVIC)
❖ If the Memory Protection Unit (MPU) is present, it is possible to block user
programs from accessing memory regions used by privileged processes.
❖ In simple applications, there is no need to separate the privileged and
user access levels
Operation modes (Switching at interrupt user)
❖ We can separate the user application stack from the kernel stack memory
to avoid the possibility of crashing a system caused by stack operation
errors in user programs.
❖ With this arrangement, the user program (running in thread mode) uses
the PSP, and the exception handlers use the MSP
❖ The switching of SPs is automatic upon entering or leaving the exception
handlers
Operation modes (Switching at interrupt user)
❖ We can separate the user application stack from the kernel stack memory
to avoid the possibility of crashing a system caused by stack operation
errors in user programs.
❖ With this arrangement, the user program (running in thread mode) uses
the PSP, and the exception handlers use the MSP
❖ The switching of SPs is automatic upon entering or leaving the exception
handlers
Exceptions & Interrupts in ARM
Exceptions & Interrupts in ARM
❖ Cortex M3 have fixed number of system exceptions and a number of
interrupts, commonly called IRQ.
❖ The number of interrupt inputs on a Cortex-M3 microcontroller depends
on the individual design.
❖ There is also a nonmaskable interrupt (NMI) input signal. In most cases,
the NMI could be connected to a watchdog timer or a voltage-monitoring
block that warns the processor when the voltage drops below a certain
level.
❖ use of NMI depends on the design of the microcontroller or system-on-
chip (SoC) product.
Vector Table in Cortex M3
Vector Table in Cortex M3
❖ To determine the starting address of the exception handler, a vector table
mechanism is used.
❖ The vector table is relocatable, and the relocation is controlled by a
relocation register in the NVIC.
❖ After reset, this relocation control register is reset to 0; therefore, the
vector table is located in address 0x0 after reset.
Stack Implementation in Cortex M3
Self Study
Two stack model in cortex M3
❖ There are two SP in cortex M3. SP register to be used is controlled by the
control register bit 1 (CONTROL[1].
❖ When CONTROL[1] is 0, the MSP is used for both thread mode and
handler mode In this arrangement, the main program and the exception
handlers share the same stack memory region.
❖ This is the default setting after power-up.
Two stack model in cortex M3
CONTROL[1]=0- Thread and handler use main Stack
Two stack model in cortex M3
❖ When the CONTROL[1] is 1, the PSP is used in thread mode.
❖ In this arrangement the main program and the exception handler can
have separate stack memory regions.
❖ This can prevent a stack error in a user application from damaging the
stack used by the OS.
❖ in this situation, the automatic stacking and unstacking mechanism will
use PSP, whereas stack operations inside the handler will use MSP
Two stack model in cortex M3
CONTROL[1]=1 Thread and handler use separate Stack
Memory Map of CORTEX M3
Memory Map of CORTEX M3
Memory Map of CORTEX M3
❖ The Cortex-M3 processor has a total of 4 GB of address space.
❖ Program code can be located in the code region, the Static Random
Access Memory (SRAM) region, or the external RAM region.
❖ it is best to put the program code in the code region because of
instruction fetches and data accesses are carried out simultaneously on
two separate bus interfaces.
❖ 0.5Gb address range is allocated to on-chip peripherals.
❖ 1 GB memory space are allocated for external RAM and external devices.
➢ Data coming from external peripherals can be stored in that location.
Memory Map of CORTEX M3
❖ 0.5-GB memory is allocated for the system-level components such as
➢ internal peripheral buses, external peripheral bus, and vendor-specific system
peripherals

❖ There are two segments of the private peripheral bus (PPB) those are
accessed as AHB & APB peripherals.
➢ AHB: or Cortex-M3 internal AHB peripherals only; this includes NVIC, FPB, DWT, and ITM
➢ APB: for Cortex-M3 internal APB devices as well as external peripherals (external to the
Cortex-M3 processor) vendor specific peripherals.

❖ The NVIC is located in a memory region called the system control space
(SCS)
Memory Map of CORTEX M3
❖ Besides providing interrupt control features, this region also provides the
control registers for SYSTICK, MPU, and code debugging control
Memory Map of CORTEX M3
Self Study

Memory Access Attributes

Default memory Access permissions

Bit- Band Operations
❖ It allows a single load/store operation to access (read/write) to a single
data bit within a word
❖ Cortex-M3, this operation is supported in two predefined memory regions
called bit-band regions.
➢ One is located in the first 1 MB of the SRAM region and other is located in the first 1 MB
of the peripheral region.

❖ These two memory regions can be accessed like normal memory, but
they can also be accessed via a separate memory region called the bit-
band alias
Bit- Band Operations
❖ When the bit-band alias address is used, each individual bit can be
accessed separately in the least significant bit (LSB) of each word-aligned
address.
❖ Bit-band region: This is a memory address region that supports bit-band
operation.
❖ Bit-band alias: Access to the bit-band alias will cause an access (a bit-band
operation) to the bit-band region. (Note: A memory remapping is
performed.)
Bit- Band Operations
Remapping of Bit- Band Address
Writing with & without Bit- Band
Writing with & without Bit- Band
Without Bit Band With Bit band

LDR R0,=0x20000000 ; Setup address LDR R0, = 0x22000008 ; Setup address

MOV R1, #1 ; Setup data

LDR R1, [R0] ;Read data
STR R1, [R0] ; Store result
ORR.W R1, #0x4 ; SET (Modify) Bit

ORR.W R1, #0x4 ; Store result

Reading with & without Bit- Band
Reading with & without Bit- Band
Without Bit Band With Bit Band

LDR R0,=0x22000008 ; Setup address

LDR R0, =0x20000000 ; Setup address
LDR R1, [R0] ; Read
LDR R1, [R0] ; Read

UBFX.W R1, R1, #2, #1 ; Extract bit[2]

Example
Problem Statement:

Set address 0x20000000 to a value of 0x3355AACC. Write 0 to bit no 2 of

the data & read the final value.

Read address 0x22000008. This read access is remapped into read access to
0x20000000. The return value is 1 (bit[2] of 0x3355AACC).

Write 0x0 to 0x22000008. This write access is remapped into a READ-MODIFY-

WRITE to0x20000000. The value 0x3355AACC is read from memory, bit 2 is
cleared, and a result of0x3355AAC8 is written back to address 0x20000000
Advantages of Bit-Band Operations
❖ bit-band operation is atomic.
❖ READ-MODIFY-WRITE sequence cannot be interrupted by other bus
activities
❖ In serial data transfer
➢ serial data and clock signals can be separated
❖ simplify branch decisions
➢ branch should be carried out based on 1 single bit instead of
■ Reading the whole register
■ Masking the unwanted bits
■ Comparing and branching
➢ With bit band
■ Reading the • status bit via the bit-band alias
■ Comparing and branching
(without bit band in interrupt: data loss)
(with bit band in interrupt)
(without bit band in multitasking: data loss)
(with bit band in multitasking)
Cortex microcontroller software interface standard
(CMSIS)

The Cortex Microcontroller Software Interface Standard (CMSIS) supports

developers and vendors in creating reusable software components for ARM
Cortex-M based systems.
Cortex microcontroller software interface standard
(CMSIS)
Need ?
Cortex microcontroller software interface standard
❖ The latest study of the development for the embedded market shows that
software complexity and cost will increase over time.
❖ ARM has recognized that after solving the diversity issue on the hardware
side, there is still a need to create a standard to access these hardware
components.
❖ The result of that effort is CMSIS:
❖ a framework to be extended by vendors, while taking advantage of a
common API.
Cortex microcontroller software interface standard
The main aim of CMSIS is

❖ improve software portability and reusability

❖ enable software solution suppliers to develop products that can work
seamlessly with device libraries from various silicon vendors.
❖ allow embedded developers to develop software quicker with an easy-to-
use and standardized software interface.
❖ allow embedded software to be used on multiple compiler products.
❖ avoid device driver compatibility issues when using software solutions
from multiple sources
Cortex microcontroller software interface standard
Cortex microcontroller software interface standard
CMSIS is divided into following layers

1. Core Peripheral Access Layer (CPAL)

Name definitions, address definitions and helper functions to access core

registers and core peripherals

➢ Consistent layout of all peripheral register

➢ Vector definitions of all exceptions and interrupts
➢ Functions to access core registers & core peripherals
➢ Device independent interface RTOS kernels
➢ Debug channel
Cortex microcontroller software interface standard
2. Middleware Access Layer (MWAL)

➢ Targeted communication interfaces include Ethernet, UART, and SPI

➢ Common method to access peripherals for the software industry.

3. Device Peripheral Access Layer (DPAL)

❖ Name definitions, address definitions, and driver code to access

peripherals. Same as CPAL but provided by the silicon vendor.
➢ include device specific exception handler address
➢ Functions to access core registers & peripherals (Device specific)
CMSIS file structure
Compiler vendor-Independent files

❖ Cortex -M3 core files

➢ Core_cm3.h
➢ Core_cm3.c

❖ Device specific files

➢ Register header file device.h (eg; LPC1768.h)
➢ System startup file System_device.c

❖ Compatible with all supported compilers (IAR, RealView, GNU, Eclipse)

CMSIS file structure
Compiler-vendor+device specific startup file

❖ Startup_device.s
CMSIS file structure
Benefits of CMSIS
Instruction set in Cortex M3
❖ To support Thumb 2 instruction set the Unified Assembler Language(UAL)
was developed to allow selection of 16-bit and 32-bit instructions.
➢ ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax
➢ ADD R0, R0, R1 ; Equivalent instruction using UAL syntax

❖ The choice between whether the instructions are interpreted as

traditional Thumb code or the new UAL syntax is normally defined by the
directive in the assembly file.
➢ with ARM assembler tool, a program code header with “CODE16” directive implies the
code is in the traditional Thumb syntax, and “THUMB” directive implies the code is in the
new UAL syntax.
Instruction set in Cortex M3
❖ With UAL,16bit and 32 bit instructions can specify by adding suffixes:
➢ Eg: ADDS R0, #1 ; Use 16-bit Thumb instruction by default ; for smaller size
➢ ADDS. N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
➢ ADDS. W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)

❖ If no suffix is given, the assembler tool can choose either instruction but
usually defaults to 16-bit Thumb code to get a smaller size. (with
minimum code size)
Instruction set in Cortex M3
Note:

Some 16 bit Thumb some instructions change the flags in APSR, even if the S
suffix is not used. However, when the UAL syntax is used, whether the
instruction changes the flag depends on the S suffix.

➢ Eg: AND R0, R1 ; Traditional Thumb syntax

➢ ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)

Most of the 16 bit thumb instructions access only R0-R7 registers.

Instruction set in Cortex M3 : Data Processing
MOV Instruction

Eg: MOV R4, R5 : Copy R5 into R4

MOV R7, # 0x1234 ; Move immediate number into R7

MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A

MOVT.W R0,#0x3456 ; Set R0 upper half to 0x3456.

Now R0=0x3456789A
Instruction set in Cortex M3
MVN Instruction

Move negative value of the original data

Eg: MVN R0, # 0xA5A5AA5;

Instruction set in Cortex M3 : Arithmetic
Instruction set in Cortex M3 : Arithmetic
Eg: ADD R0, R0, R1 ; R0 = R0 + R1

ADDS R0, R0, #0x12 ; R0 = R0 + 0x12

ADD.W R0, R1, R2 ; R0 = R1 + R2

Eg: SDIV/ UDIV <c> <Rd>,<Rn>,<Rm> Unsigned and signed division

<Rd> Specifies the destination register. If <Rd> is omitted, this register is the same
as <Rn>.

<Rn> Specifies the register that contains the dividend.

<Rm> Specifies the register that contains the divisor.

Instruction set in Cortex M3 : Arithmetic
Eg:

LDR R0,=300 ; Decimal 300

MOV R1,#5

UDIV.W R2, R0, R1

What will be the value in R2

Instruction set in Cortex M3 : Arithmetic
Long Multiplication and Multiply and accumulate
Instruction set in Cortex M3 : Logical
Instruction set in Cortex M3 : Logical
ORN

Logical OR NOT (immediate) performs a bitwise (inclusive) OR of a register

value and the complement of and immediate value, and writes the result to
the destination register.

Eg: ORN R0 , #0x12121212

ORN R1, R3
Instruction set in Cortex M3 : Shift & Rotate
Instruction set in Cortex M3 :
Call and Unconditional Branch

● B label ; Branch to a labeled address

○ B Label ; Pc=Label

● BX reg ; Branch to an address specified by a register

○ BX R5; Pc=R5

● BL label ; Branch to a labeled address and save return address in LR

○ BL UP ; PC=UP

● BLX reg ; Branch to an address specified by a register and save return

address in LR
○ BLX R7 ; PC=R7
Instruction set in Cortex M3 :
we can also carry out a branch operation using MOV instructions and LDR
instructions

❖ MOV R15, R0 ; Branch to an address inside R0

❖ LDR R15, [R0] ; Branch to an address in memory location ; specified by R0
❖ POP {R15} ; Do a stack pop operation, and change the; program counter
value ; to the result value
Instruction set in Cortex M3 : Load/ store
Instruction set in Cortex M3 : Load/ store
Eg:

LDR.W R0,[R1, #offset]!

Read memory[R1+offset], with R1 update to R1+offset

LDR R0, [R1, #0x04]!

Assume R1=0x00008000

What will be the value in R0 & R1 after execution

Instruction set in Cortex M3 : Load/ store
Load Register Dual (literal) calculates an address from the PC value and an
immediate offset, loads two words from memory, and writes them to two
registers.

Assume R1=0x0005000
Eg: LDRD RD5, RD6 [R1, #0x02]
Instruction set in Cortex M3 : Load/ store(Multiple)
1. LDM - Load multiple values
2. STM - Store multiple values

Eg: Assume R8=0x00008000

1. STMIA.W R8! , {R0-R3} what will be the value in R8

2. STMIA.W R8 , {R0-R3} what will be the value in R8
Instruction set in Cortex M3 : Compare instructions
❖ The compare (CMP) instruction subtracts two values and updates the flags
(just like SUBS), but the result is not stored in any registers.
➢ CMP R0, R1 ; Calculate R0 – R1 and update flag
➢ CMP R0, #0x12 ; Calculate R0 – 0x12 and update flag

❖ CMN (compare negative). It compares one value to the negative (two’s

complement) of a second value; the flags are updated
➢ CMN R0, R1 ; Calculate R0 – (-R1) and update flag
➢ CMN R0, #0x12 ; Calculate R0 – (-0x12) and update flag
Instruction set in Cortex M3 : Compare instructions

❖ The TST (test) instruction is more like the AND instruction. It ANDs two values
and updates the flags. However, the result is not stored in any register.
➢ TST R0, R1 ; Calculate R0 AND R1 and update flag
➢ TST R0, #0x12 ; Calculate R0 AND 0x12 and update flag
Instruction set in Cortex M3 : Conditional attributes
Instruction set in Cortex M3
❖ Combined branch & conditions
➢ BEQ label : Branch to address 'label' if Z flag is set
➢ CBZ (compare and branch if zero) and
➢ CBNZ (compare and branch if nonzero)
Instruction set in Cortex M3
Eg: In assembly
The compare and branch instructions
only support forward branches MOV R0, #5 ; Set loop counter

loop1 CBZ R0,loop1exit ;( if loop

Eg: i = 5;
counter = 0 then exit the loop)

while (i != 0 ){ BL func1 ; call a function

func1(); ; call a function SUB R0, #1 ; loop counter decrement

B loop1 ; next loop

i−−;
Loop1exit
}
Instruction set in Cortex M3
...
status = strchr(email_address, '@');
BL strchr
if (status == 0){//status is 0 if @ is not in
email_address CBNZ R0, email_looks_okay ; Branch if
result is not zero
show_error_message();
BL show_error_message

exit(1); BL exit

} email_looks_okay

...
Instruction set in Cortex M3
Combined Compare and Conditional Branch

● The IT (IF-THEN) block is very useful for handling small conditional code. It
avoids branch penalties because there is no change to program flow.
● It can provide a maximum of four conditionally executed instructions.
● The first statement after the IT command must be TRUE-THEN-EXECUTE,
which is always written as ITxyz, where T means THEN and E meansELSE
Instruction set in Cortex M3
IT<x><y><z> <cond> ; IT instruction (<x>, <y>,; <z> can be T or E)

instr1<cond> <operands> ; 1st instruction (<cond>; must be same as IT)

instr2<cond or not cond> <operands> ; 2nd instruction (can be; <cond> or

<!cond>

instr3<cond or not cond> <operands> ; 3rd instruction (can be; <cond> or

<!cond>

instr4<cond or not cond> <operands> ; 4th instruction (can be; <cond> or

<!cond>
Instruction set in Cortex M3
if (R1<R2) then CMP R1, R2 ; If R1 < R2 (less then)

ITTEE LT ; then execute instruction 1 and 2; (indicated by T)

R2=R2−R1
; else execute instruction 3 and 4; (indicated by E)
R2=R2/2
SUBLT.W R2,R1 ; 1st instruction
else
LSRLT.W R2,#1 ; 2nd instruction
R1=R1−R2
SUBGE.W R1,R2 ; 3rd instruction (notice the GE is; opposite
of LT)
R1=R1/2
LSRGE.W R1,#1 ; 4th instruction
Instruction set in Cortex M3
REV, REVH, and REVSH

REV reverses the byte order in a data word, and REVH reverses the byte order
inside a half word

Eg: 1. R0=0x12345678

REV R1, R0 ; R1=0x78563412

Eg: 2. REVH R2, R0 ; R2=0x34127856

Instruction set in Cortex M3
Reverse Bit

The RBIT instruction reverses the bit order in a data word

Syntax: RBIT.W <Rd>, <Rn>

Eg: R0=0xB4E10C23 (binary value

1011_0100_1110_0001_0000_1100_0010_0011)

RBIT.W R0, R1

R0=0xC430872D

(binary value 1100_0100_0011_0000_1000_0111_0010_1101)

Instruction set in Cortex M3
SXTB, SXTH, UXTB, and UXTH

The four instructions SXTB, SXTH, UXTB, and UXTH are used to extend a byte or
half word data into

a word. The syntax of the instructions is as follows:

SXTB <Rd>, <Rn>

SXTH <Rd>, <Rn>

UXTB <Rd>, <Rn>

UXTH <Rd>, <Rn>

Instruction set in Cortex M3
SXTB, SXTH, UXTB, and UXTH

For SXTB/SXTH, the data are sign extended using bit[7]/bit[15] of Rn. With UXTB
and UXTH the value is zero extended to 32-bit.

Eg: If R0= 0x55AA8765

SXTB R1, R0 ; R1 = 0x00000065

SXTH R1, R0 ; R1 = 0xFFFF8765

UXTB R1, R0 ; R1 = 0x00000065

UXTH R1, R0 ; R1 = 0x00008765

Instruction set in Cortex M3
Bit Field Clear and Bit Field Insert

Bit Field Clear (BFC) clears 1–31 adjacent bits in any position of a register. The
syntax of the instruction is as follows:

BFC.W <Rd>, <#lsb>, <#width>

For example,

LDR R0,=0x1234FFFF

BFC.W R0, #4, #8

This will give R0 = 0x1234F00F.

Instruction set in Cortex M3
Bit Field Insert (BFI) copies 1–31 bits (#width) from one register to any
location (#lsb) in another register. The syntax is as follows:

BFI.W <Rd>, <Rn>, <#lsb>, <#width>

For example,

LDR R0,=0x12345678

LDR R1,=0x3355AACC

BFI.W R1, R0, #8, #16 ; Insert R0[15:0] to R1[23:8]

This will give R1 = 0x335678CC