MC74VHC00 D-2315589

MC74VHC00
Quad 2-Input NAND Gate

The MC74VHC00 is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
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output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V MARKING
systems to 3 V systems. DIAGRAMS
Features 14
• High Speed: tPD = 3.7 ns (Typ) at VCC = 5 V VHC00G
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C SO−14 AWLYWW
D SUFFIX
• High Noise Immunity: VNIH = VNIL = 28% VCC CASE 751A
1
• Power Down Protection Provided on Inputs

• Balanced Propagation Delays
14
• Designed for 2 V to 5.5 V Operating Range
VHC
• Low Noise: VOLP = 0.8 V (Max) 00
TSSOP−14
• Pin and Function Compatible with Other Standard Logic Families DT SUFFIX
ALYW G
G
• Latchup Performance Exceeds 300 mA CASE 948G
1
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 32 FETs or 8 Equivalent Gates
A = Assembly Location
• These Devices are Pb−Free and are RoHS Compliant L, WL = Wafer Lot
Y = Year
W, WW = Work Week
VCC B4 A4 Y4 B3 A3 Y3 G, G = Pb−Free Device
14 13 12 11 10 9 8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1 2 3 4 5 6 7
A1 B1 Y1 A2 B2 Y2 GND
Figure 1. Pinout: 14−Lead Packages

(Top View)
FUNCTION TABLE
Inputs Output
A B Y
L L H
L H H
H L H
H H L
© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

September, 2014 − Rev. 7 MC74VHC00/D
MC74VHC00
1
A1 3
2 Y1
B1
4
A2 6
5 Y2
B2
Y = AB
9
A3 8
10 Y3
B3
12
A4 11
13 Y4
B4
Figure 2. Logic Diagram
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage −0.5 to +7.0 V
VIN Digital Input Voltage −0.5 to +7.0 V
VOUT DC Output Voltage −0.5 to VCC +0.5 V
IIK Input Diode Current −20 mA
IOK Output Diode Current $20 mA
IOUT DC Output Current, per Pin $25 mA
ICC DC Supply Current, VCC and GND Pins $75 mA
PD Power Dissipation in Still Air SOIC Package 200 mW
TSSOP 180
TSTG Storage Temperature Range −65 to +150 °C
VESD ESD Withstand Voltage Human Body Model (Note 1) >2000 V
Machine Model (Note 2) >200
Charged Device Model (Note 3) N/A
ILATCH−UP Latch−Up Performance Above VCC and Below GND at 125°C (Note 4) $300 mA
qJA Thermal Resistance, Junction to Ambient SOIC Package 143 °C/W
TSSOP 164
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS

Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
VIN DC Input Voltage 0 5.5 V
VOUT DC Output Voltage 0 VCC V
TA Operating Temperature Range, All Package Types −55 125 °C
tr, tf Input Rise or Fall Time VCC = 3.3 V + 0.3 V 0 100 ns/V
VCC = 5.0 V + 0.5 V 0 20
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74VHC00
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ TA = −40 to TA = −55 to
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
TA = 25°C 85°C +125°C
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V Min Typ Max Min Max Min Max Unit
VIH High−Level Input 2.0 1.50 1.50 1.50 V
Voltage 3.0 to VCC x VCC x VCC x
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 5.5 0.7 0.7 0.7
VIL Low−Level Input 2.0 0.50 0.50 0.50 V
Voltage 3.0 to VCC x VCC x VCC x
5.5 0.3 0.3 0.3
VOH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
High−Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL
Output Voltage IOH = − 50 mA
2.0
3.0
1.9
2.9
2.0
3.0
1.9
2.9
1.9
2.9
V
4.5 4.4 4.5 4.4 4.4
Vin = VIH or VIL
IOH = − 4 mA 3.0 2.58 2.48 2.40
IOH = − 8 mA 4.5 3.94 3.80 3.70
VOL Low−Level Vin = VIH or VIL 2.0 0.0 0.1 0.1 0.1 V
Output Voltage IOL = 50 mA 3.0 0.0 0.1 0.1 0.1
4.5 0.0 0.1 0.1 0.1
Vin = VIH or VIL
IOL = 4 mA 3.0 0.36 0.44 0.55
IOL = 8 mA 4.5 0.36 0.44 0.55
$0.1 $1.0 $2.0 mA
Iin Input Leakage Vin = 5.5 V or GND 0 to 5.5
Current
ICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VCC or GND
Current
5.5 2.0 20 40
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
mA
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
TA = −40 to TA = −55 to
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = 25°C 85°C +125°C
Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit
tPLH, Propagation VCC = 3.3 ± 0.3 V CL = 15 pF 5.5 7.9 1.0 9.5 1.0 10 ns
tPHL Delay, A or B to Y CL = 50 pF 8.0 11.4 1.0 13.0 1.0 14.5
VCC = 5.0 ± 0.5 V CL = 15 pF 3.7 5.5 1.0 6.5 1.0 7.0
Î ÎÎ
CL = 50 pF 5.2 7.5 1.0 8.5 1.0 9.5
Cin Input 4.0 10 10 10 pF
Capacitance
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Note 5) 19 pF

5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, Measured in SOIC Package)
TA = 25°C
Symbol Characteristic Typ Max Unit

VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V
VOLV Quiet Output Minimum Dynamic VOL − 0.3 − 0.8 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V
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3
MC74VHC00
TEST POINT
A or B VCC
50% OUTPUT
GND DEVICE
UNDER
tPLH tPHL CL*
TEST
Y 50% VCC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
ORDERING INFORMATION
Device Package Shipping†
MC74VHC00DR2G SOIC−14 2500 / Tape & Reel
(Pb−Free)
MC74VHC00DTG TSSOP−14* 96 Units / Rail

(Pb−Free)
MC74VHC00DTR2G TSSOP−14* 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE
GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW
XXXXX = Specific Device Code

1.27
WL = Wafer Lot
PITCH
Y = Year
WW = Work Week
G = Pb−Free Package
14X
*This information is generic. Please refer to
0.58
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOIC−14 NB PAGE 1 OF 2
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COMMON CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. ANODE/CATHODE 2. ANODE 2. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
14. COMMON ANODE 14. COMMON CATHODE 14. COMMON ANODE
STYLE 5: STYLE 6: STYLE 7: STYLE 8:

PIN 1. COMMON CATHODE PIN 1. CATHODE PIN 1. ANODE/CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE 2. CATHODE 2. COMMON ANODE 2. ANODE/CATHODE
3. ANODE/CATHODE 3. CATHODE 3. COMMON CATHODE 3. ANODE/CATHODE
4. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE 4. NO CONNECTION
5. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE 5. ANODE/CATHODE
6. NO CONNECTION 6. CATHODE 6. ANODE/CATHODE 6. ANODE/CATHODE
7. COMMON ANODE 7. CATHODE 7. ANODE/CATHODE 7. COMMON ANODE
8. COMMON CATHODE 8. ANODE 8. ANODE/CATHODE 8. COMMON ANODE
9. ANODE/CATHODE 9. ANODE 9. ANODE/CATHODE 9. ANODE/CATHODE
10. ANODE/CATHODE 10. ANODE 10. ANODE/CATHODE 10. ANODE/CATHODE
11. ANODE/CATHODE 11. ANODE 11. COMMON CATHODE 11. NO CONNECTION
12. ANODE/CATHODE 12. ANODE 12. COMMON ANODE 12. ANODE/CATHODE
13. NO CONNECTION 13. ANODE 13. ANODE/CATHODE 13. ANODE/CATHODE
14. COMMON ANODE 14. ANODE 14. ANODE/CATHODE 14. COMMON CATHODE
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOIC−14 NB PAGE 2 OF 2
rights of others.

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1
ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X device data sheet for actual part marking.
14X
0.36 Pb−Free indicator, “G” or microdot “ G”,
1.26 may or may not be present.
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1
rights of others.

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MC74VHC00MEL MC74VHC00MELG NLV74VHC00DTR2G

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MC74VHC00

Quad 2-Input NAND Gate

• Power Down Protection Provided on Inputs

Figure 1. Pinout: 14−Lead Packages

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

Figure 2. Logic Diagram

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 5.5 0.7 0.7 0.7

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Note 5) 19 pF

Symbol Characteristic Typ Max Unit

*Includes all probe and jig capacitance

Figure 3. Switching Waveforms Figure 4. Test Circuit

Figure 5. Input Equivalent Circuit

MC74VHC00DTG TSSOP−14* 96 Units / Rail

MC74VHC00DTR2G TSSOP−14* 2500 / Tape & Reel

XXXXX = Specific Device Code

DESCRIPTION: SOIC−14 NB PAGE 1 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

STYLE 5: STYLE 6: STYLE 7: STYLE 8:

DESCRIPTION: SOIC−14 NB PAGE 2 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

PUBLICATION ORDERING INFORMATION

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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