دفتر لوجيك م.سامر

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Sequential Logic Circuits
 The output of a sequential logic circuit is dependent not only on the present inputs, but
also on the past sequence of the inputs.
 A sequential logic circuit must “remember” the past history of the inputs.
 It does this using basic memory elements.
– Latches
– Flip-Flops
Basic Memory Elements

● Latch
– Clock input is level sensitive.
– Output can change multiple times during a clock cycle.
– Output changes while clock is active.
● Flip-Flop
– Clock input is edge sensitive.
– Output can change only once during a clock cycle.
– Output changes on clock transition.
Both latches and flip-flops use feedback to achieve “memory”.

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Digital logic design Samer A.Hamed

Latches
Set-Reset (SR) Latch
● A Set-Reset Latch has two inputs

– Set (S) input
– Reset (R) input
● It can be constructed from two cross-coupled NOR gates or two cross-coupled NAND gates.
● It has three modes of operation
– Set: Latch output set to 1 (Q+ = 1)
– Reset: Latch output reset to 0 (Q+ = 0)
– Store: Latch output does not change (Q+ = Q)
SR Latch: using NOR gates
SR Latch: Behavior
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SR Latch: Symbol
SR Latch: Timing Diagram

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SR Latch: Characteristic Equation
Characteristic Equation: Q+ = S + R'.Q (S.R = 0)

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SR Latch: using NAND gates
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Gated D Latch
A Gated D Latch has two inputs
– Gate (G) input
– Data (D) input
● It can be constructed from an SR Latch and additional logic gates.
● It has the following behavior
– G = 1: D is passed to Q (Q+ = D)
– G = 0: Q remains unchanged (Q+ = Q)
● Also referred to as a transparent latch.
Gated D Latch: Circuit and Timing
Gated D Latch: Symbol and Truth Table

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Characteristic Equation: Q+ = G'.Q + G.D
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Flip-Flops
D Flip-Flop
● A D Flip-Flop has two inputs
– Clock (Ck) --- denoted by the small arrowhead
– Data (D)
● The output of the D Flip-Flop changes in response to the clock input only.
– not in response to a change in the D input
● The D Flip-Flop is edge-triggered not level-sensitive
– Positive (or rising) edge-triggered: 0 _ 1
– Negative (or falling) edge-triggered: 1 _ 0
Characteristic Equation: Q+ = D
D Flip-Flop: Timing Diagram

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SR Flip-Flop
● The SR Flip-Flop has three inputs:

– Set (S) and Reset (R)
● Similar to an SR Latch
– S = 1 sets the flip-flop (Q+ = 1)
– R = 1 resets the flip-flop (Q+ = 0)
● Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active
clock edge.
– Positive edge-triggered
– Negative edge-triggered
SR Flip-Flop
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JK Flip-Flop
Characteristic Equation:
Q+ = J.Q' + K'.Q
T Flip-Flop
The Toggle (T) Flip-Flop has two inputs
– Toggle (T)
● The T input controls the state change
– when T = 0, the state does not change (Q+ = Q)
– when T = 1, the state changes following an active clock edge (Q+ = Q')
● T Flip-Flops are often used in the design of counters.
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Characteristic Equation: Q+ = T.Q' + T'.Q = T xor Q
Building a T Flip-Flop
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Counters
 A counter is a sequential circuit that cycles through a fixed sequence of states.
 The state of the counter is stored in Flip-Flops.
 An n-bit counter
– has n Flip-Flops
– can cycle through at most 2n states.
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Procedure to Design Synchronous Counters
The procedure to design a synchronous counter is listed here.
• Obtain the truth table of the logic sequence for intended counter to be
designed. Alternatively obtain the state diagram of the counter.
• Determine the number and type of flip-flop to be used.
• From the excitation table of the flip-flop, determine the next state logic.
• From the output state, use Karnaugh map for simplification to derive the circuit output
functions and the flip-flop output functions.
• Draw the logic circuit diagram.
• Simulate the circuit using software.
• Build the circuit.

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Design a 3 bit up counter using T flip flop
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J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0
Design a counter that goes through the sequence: 0, 3, 2, 4, 1, 5, 7 and repeat.

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Analysis of Clocked Sequential Circuits
x
D Q A
D Q B
CLK Q
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
=Ax+Bx
B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = *A(t)+ B(t)+ x’(t)

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= (A + B) x’
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 State Table (Transition Table)
Present state input Next state output

A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
 State Diagram
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Analysis of Clocked Sequential Circuits ( JK FLIP FLOP )
J Q A
x K Q
J Q B JA = B KA = B x’
JB = x’ KB = A  x
K Q
CLK
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
Present Next
input Flip Flop inputs
state state
A B X A B JA KA JB KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
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Derive the state table and the state diagram of the sequential shown circuit.
Explain the function that the circuit performs
TA = A + B
TB = A’ + B
Q(next)= T’Q+TQ’
A(next) = TAA + TAA

= (A + B)A + (A + B)A= ABA + AA+ AB= 0 + 0 + AB= AB
B(next) = TBB + TBB= (A+ B)B + (A+ B)B= ABB + AB+ BB

= 0 + AB+ 0= AB
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
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Example
A sequential circuit with two D flip-flops, A and B, two inputs, x and y, and one output
z, is specified by the next state and output equations:
A(t+1) = x’y + xA
B(t+1) = x’B + xA
z=B
a) Draw the logic diagram of the circuit
b) List the state table for the sequential circuit
c) Draw the corresponding state diagram

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Basic Memory Elements

– Output can change multiple times during a clock cycle.

– Output changes while clock is active.

– Output can change only once during a clock cycle.

– Output changes on clock transition.

Both latches and flip-flops use feedback to achieve “memory”.

Digital logic design Samer A.Hamed

● A Set-Reset Latch has two inputs

SR Latch: using NOR gates

Digital logic design Samer A.Hamed

SR Latch: Timing Diagram

Digital logic design Samer A.Hamed

Characteristic Equation: Q+ = S + R'.Q (S.R = 0)

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Gated D Latch: Circuit and Timing

Gated D Latch: Symbol and Truth Table

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

D Flip-Flop: Timing Diagram

Digital logic design Samer A.Hamed

● The SR Flip-Flop has three inputs:

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

The procedure to design a synchronous counter is listed here.

designed. Alternatively obtain the state diagram of the counter.

• Determine the number and type of flip-flop to be used.

• Draw the logic circuit diagram.

• Simulate the circuit using software.

• Build the circuit.

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Design a counter that goes through the sequence: 0, 3, 2, 4, 1, 5, 7 and repeat.

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

Digital logic design Samer A.Hamed

= A(t) x(t)+B(t) x(t)

y(t) = *A(t)+ B(t)+ x’(t)

Digital logic design Samer A.Hamed

Present state input Next state output

Digital logic design Samer A.Hamed

A(t+1) = JA Q’A + K’A QA

B(t+1) = JB Q’B + K’B QB

= B’x’ + ABx + A’Bx’

Digital logic design Samer A.Hamed

A(next) = TAA + TAA

Digital logic design Samer A.Hamed

a) Draw the logic diagram of the circuit

b) List the state table for the sequential circuit

c) Draw the corresponding state diagram

Digital logic design Samer A.Hamed

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