EE213 Topic01 Transistor

EE213
Digital Integrated Circuits II
Topic 01: Transistor Models

- What do digital IC designers need to know?
Prof. Pingqiang Zhou
ShanghaiTech University
School of Information Science and Technology
EE213-Topic01-Transistor.1 ShanghaiTech University

From Device/Wire to Circuit
 (Device) Transistor models (for manual analysis)
• Threshold voltage
• Static V-I model
• Dynamic R/C models
 Wire models
• Resistance
• Capacitance
• RC delay models
 (Circuit) Inverter
• Static response (VTC)
• Dynamic response (delay)
• Power/energy

Materials were Taken From
 UC Berkeley EECS
• EE141: Digital Integrated Circuits
• EE241: Advanced Digital Integrated Circuits
Chapter 2
Chapter 3
Chapter 4
A Good Reference Book
https://people.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-
Slides-download.html
Transistor Models

Transistor Models (for Manual Analysis)
 What is transistor?
 Why modeling?
 Threshold voltage
 Static behavior: I-V characteristics
 Dynamic behavior: R/C-V characteristics

https://en.wikipedia.org/wiki/Front_end_of_line
ShanghaiTech University
https://en.wikipedia.org/wiki/Back_end_of_line
[IBM]
[Intel]
EE213-Topic01-Transistor.7
Semiconductor Materials

Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
• Group V: extra electron (n-type)
• Group III: missing electron, called hole (p-type)

p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode
 Current flows only in one direction

Transistor Types – BJT
 Bipolar transistors
• n-p-n or p-n-p silicon structure
• Small current into very thin base layer
controls large currents between emitter
and collector
• Base currents limit integration density
NPN BJT with forward-biased E–B junction Simplified cross section of a planar
and reverse-biased B–C junction NPN bipolar junction transistor
https://en.wikipedia.org/wiki/Bipolar_junction_transistor#PNP
https://en.wikipedia.org/wiki/Transistor
Transistor Types – MOSFET
 Metal Oxide Semiconductor (MOS) Field Effect Transistors
• nMOS and pMOS MOSFETS
• Voltage applied to insulated gate controls current between source and
drain
• Low power allows very high integration
https://en.wikipedia.org/wiki/Field-effect_transistor
https://en.wikipedia.org/wiki/Transistor
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal – oxide – semiconductor (MOS) capacitor
Polysilicon Aluminum

Review: FinFET and GAA

nMOS Operation (1)
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF
Source Gate Drain

Polysilicon
SiO2
0
n+ n+
S D
p bulk Si

nMOS Operation (2)
 When the gate is at a high voltage:
• Positive charge on gate of MOS capacitor
• Negative charge attracted to surface
• Inverts a channel under gate to n-type
- Now current can flow through n-type silicon from source through
channel to drain, transistor is ON
Source Gate Drain

Polysilicon
SiO2
1
n+ n+
S D
p bulk Si

pMOS Transistor
 Similar, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low: transistor ON
• Gate high: transistor OFF
• Bubble indicates inverted behavior

Transistors as Switches
 We can view MOS transistors as electrically controlled
switches
 Voltage at gate controls path from source to drain
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s

Cross-Section of Inverter Layout
VDD
A Y
GND
Want to know how to fabricate such complex things?

Read “device manufacturing” on the course page!

Layout of Two Chained Inverters
VDD VDD
M2
M4
Vin Vout Vout2
M1 M3
A
GND VDD
Y
n+ n+ p+ p+
n well
p substrate
nMOS transistor pMOS transistor
See http://www.vlsi-expert.com/2014/11/cmos-layout-design.html

 Why modeling?

Switch Model of an MOS Transistor

Dynamic Analysis of CMOS Inverter
VDD
A Y
GND

Analysis of More Complex Inverter Chain
 Sizing for
• Area
• Delay
• Energy

Transistor I-V Modeling
 BSIM http://bsim.berkeley.edu/models/bsim4/
• Superthreshold and subthreshold models
• Need smoothening between two regions
 EKV/PSP https://en.wikipedia.org/wiki/Transistor_model
• One continuous model based on channel surface potential

 Why modeling?

Threshold Voltage: Concept

Threshold Voltage: Physical Components
Four physical components:

1. Flat Band voltage V1 = VFB between
the gate and the channel
2. Change the surface potential at

inversion: V2 = s =
𝑘𝑇
,∅ =
𝑞
3. Offset the depletion region charge

(i.e., V3 = Qd/Cox)
4. Offset the fixed positive charges Qox
(due to imperfections) in the gate
oxide and in the silicon-oxide
interface (i.e., V4 = Qox/Cox)
Generalized Threshold Voltage ( )
Substrate-Bias
(or Body-Effect) coefficient

Effect of Body-Bias on Threshold Voltage
Figure 3-14
Dynamic Body Biasing
 Increase Vt during sleep

A Triple-Well Structure
 P-well allows to use different body voltages for the NMOS
gates

Exercise

 Why modeling?

Transistor in Linear Mode
 In Linear region, Ids depends on

1. How much charge is in the channel
2. How fast is the charge moving

Channel Charge (Electrons for nMOS!)
 MOS structure looks like parallel plate capacitor while
operating in inversions
• Gate – oxide – channel
gate
Vg
+ +
source Vgs Cg Vgd drain
Vs - - Vd
channel
n+ - + n+
Vds
p-type body
 Qchannel = C V
C = Cg = eox/tox WL= Cox WL
Not the depletion capacitor! Vox(y) = Vgc(y) – Vt

(Vgs + Vgd)/2 – Vt
= (Vgs – Vds/2) – Vt
Carrier Velocity
 Charge is carried by e-, propelled by the lateral electric

field between source and drain
• E = Vds/L
 Carrier velocity v proportional to lateral E-field

• v = m E, m called mobility
 Time for carrier to cross channel:

• t = L/v

I-V in Linear Mode
gate
 Now we know +
Vg
+
• How much charge in the channel source Vgs Cg Vgd drain
Vs - - Vd
channel
• How much time to cross channel n+ - + n+
Vds
p-type body

Another Derivation: Charge Density along the Channel
 The channel potential varies with position along the channel
Areal inversion charge density

[in C/cm2]:
 The current flowing in channel:

I-V Summary
 Shockley 1st order transistor models
Vdsat Vgs – Vt

I-V Relations: An Ideal Transistor
𝐼
0 𝑉 <𝑉 cutoff
𝑉
𝛽 𝑉 −𝑉 − 𝑉 𝑉 <𝑉 linear
= 2
𝛽
𝑉 −𝑉 𝑉 >𝑉 saturation
2

Simulated 32nm Transistor
6.0E-04
L = 32nm
5.0E-04
4.0E-04
IDS[A] 3.0E-04 ~ Linear

2.0E-04
1.0E-04
0.0E+00
0.2 0.4 0.6 0.8 1.0
VDS[V]

 Why modeling?

Primary Performance Metric of Logic Gates: Delay
input Vin
waveform Vin Vout
t
output
waveform Vout
t
Delay Definitions
Vin Vout
Vin Propagation delay

tp = (tpHL + tpLH)/2
input 50%
waveform
t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr

Review: Dynamic Analysis of Logic Gates

48 [Courtesy: UC Berkeley]
MOS Transistor as a Switch
Discharging a capacitor
vGS +
iDS vDS
- C
𝑖 =𝑖 𝑣 ,𝑣
,

Modeling Propagation Delay
 Model circuit as first-order RC network
VDD
Vin Vout
In Out
GND
R
vout vout (t) = (1 – e–t/)VDD,  = RC
C
Time to reach 50% point is
VDD t = ln(2)  = 0.69 
Time to reach 90% point is
t = ln(9)  = 2.2 
How to find equivalent R and C?

How to Find R?
Calculating MOS resistance:
[Rabaey, Ch 3.3]

Method One: By Integration
Traversed path

Method Two: Average
Averaging resistances:

Ron vs. VDD (Simulation Results)
or
EE213-Topic01-Transistor.54 [Rabaey, Ch 3.3] ShanghaiTech University

Exercise: Switching Trajectory (nMOS)
6.0E-04
5.0E-04
4.0E-04
IDS[A]
3.0E-04
2.0E-04
1.0E-04
0.0E+00
0.2 0.4 0.6 0.8 1.0
VDS[V]
MOS Capacitance

Component #1: Gate Capacitance
Lateral diffusion
(gate-drain overlap)
e ox Cap./unit area
Cox 
tox
Thickness of oxide
e ox
CG  WL
tox

Transistor in Cutoff
 When the transistor is off, no carriers in channel to form

the other side of the capacitor
• Substrate acts as the other capacitor terminal
• Capacitance becomes series combination of gate oxide and
depletion capacitance
- from gate -> body -> source/drain

Transistor in Linear Region
 Channel is formed and acts as the other terminal

• CGCB drops to zero (shielded by channel)
 Model by splitting oxide cap equally between source and

drain

Transistor in Saturation Region
 Changing source voltage doesn’t change VGC uniformly

– E.g. VGC at pinch off point still Vt
 Bottom line: CGCS ≈ 2/3·W·L·Cox
 Drain voltage no longer affects channel charge
• Set by source and VDS_sat
• If change in charge is 0, CGCD = 0

Component #1.1: Gate-to-Channel Capacitance
Operation CGCB CGCS CGCD CGC

Region
Cutoff CoxWLeff 0 0 CoxWLeff
Linear 0 CoxWLeff/2 CoxWLeff/2 CoxWLeff
Saturation 0 (2/3)CoxWLeff 0 (2/3)CoxWLeff
 Most important regions in digital design: Cutoff and Sat.

Gate-Channel Capacitance
Region of interest
VT
CGC as a function of VGS CGC as a function of the

(with VDS =0) degree of saturation

Exercise
An inverter (not shown in the figure) drives a PMOS device whose source, drain,
and body terminals are tied together. The PMOS is connected to the ground
through an ideal capacitor.
• Assume that the PMOS device has a sub-threshold swing S of 2×0.026×ln10
[V/dec] and a |Vt| of 0.5V. Ignore the gate-to-source and gate-to-drain overlap
capacitances. The supply voltage of the inverter is 1.0V.
• When VN is initialized to 0V and a low-to-high input signal is applied to the
inverter, VN is boosted down to -0.5V via the capacitive coupling effect.
What would be the VN voltage after the boosting if the initial VN voltage is 1.0V
instead of 0V?
Hint: For a MOS transistor working in the subthreshold regime, its sub-threshold
swing S can be approximated as S = 0.026×ln10×(1 + Cd/Cox) [V/dec], where Cd
is the deletion region capacitance, and Cox is the gate oxide capacitance.

Component #1.2: Gate Overlap Capacitance
OFF/LIN/SAT

Component #1.3: Gate Fringe Capacitance
 COV not just from metallurgic overlap – get fringing

fields too
 Typical value: ~0.2fF·W(in µm)/edge

Question: How to Measure the Gate Capacitance?

Component #2: Diffusion/Junction Capacitance
[Neil’s book, Ch. 2.3.1]

Junction Capacitance

Capacitance Model Summary

BSIM4 4.8.1 MOSFET Model (Released@2017/2/15)

Transistor Models

Ideal vs. Simulated nMOS I-V Plot
𝐼
 65 nm IBM process, VDD = 1.0 V 0 𝑉 <𝑉 cutoff
𝑉
𝛽 𝑉 −𝑉 − 𝑉 𝑉 <𝑉 linear
= 2
𝛽
𝑉 −𝑉 𝑉 >𝑉 saturation
2

ON/OFF Current
gate
Vg
+ +
Vs - - Vd
channel
n+ - + n+
Vds
p-type body
 Ion = Ids @ Vgs = Vds = VDD

• Saturation
 Ioff = Ids @ Vgs = 0, Vds = VDD

• Cutoff

A Modern Sub-100nm Look of an MOS

Non-ideal Transistor Behaviors
 #1: High Field Effects
• Mobility Degradation
• Velocity Saturation
 #2: Channel Length Modulation

 #3: Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
 #4: Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
 #5: Process and Environmental Variations

Issue #1: Electric Fields Effects
gate
Vg
+ +
Vs - - Vd
channel
n+ - + n+
Vds
p-type body
 Vertical electric field: (max) Evert = Vgs/tox

• Attracts carriers into channel
• Long channel: Qchannel  Evert How about
 Lateral electric field: Elat = Vds/L short channel?
• Accelerates carriers from drain to source
• Long channel: v = mElat
Mobility Degradation
 High Evert effectively reduces mobility
• Collisions with oxide interface
K. Chen, C. Hu, P. Fang, M. R. Lin and D. L. Wollesen, "Predicting CMOS speed with gate oxide and
voltage scaling and interconnect loading effects," in IEEE Transactions on Electron Devices, vol. 44,
no. 11, pp. 1951-1957, Nov 1997.
Velocity Saturation
 At high Elat, carrier velocity rolls off
• Carriers scatter off atoms in silicon lattice
• Velocity reaches vsat
- Electrons: 107 cm/s
- Holes: 8 x 106 cm/s
 Velocity model (nonlinear!)
/
/
when

Simple Model for Velocity Sat.
 Approximate velocity (n = 1):
Integrate current again (in linear region)
In deep submicron, there are four regions of operation:

(1) cut off, (2) linear, (3) velocity sat., (4) current sat.

Region I: Linear 𝑫𝑺 𝑫𝑺𝑨𝑻
Region II: Velocity Saturation

I II
(VDS 𝑫𝑺𝑨𝑻 )
𝑫𝑺𝑨𝑻
𝐼 =𝑣 ⋅𝐶 ⋅ 𝑊 ⋅ [𝑉 − 𝑉 − 𝑉’ ]
C. G. Sodini, P.-K. Ko and J. L. Moll, "The effect of high fields on MOS device and
circuit performance," in IEEE Transactions on Electron Devices, vol. 31, no. 10,
pp. 1386-1393, Oct 1984.
 We re-define the saturation voltage VDSAT to be 𝑫𝑺𝑨𝑻 , the drain

voltage at which the carriers at drain become velocity saturated
• Corresponds to the point at which the lateral electric field at the drain
end of the channel becomes equal to the critical field EC.
Region I: Linear 𝑫𝑺 𝑫𝑺𝑨𝑻
Region II: Velocity Saturation

I II
(VDS 𝑫𝑺𝑨𝑻 )
𝑫𝑺𝑨𝑻
𝐼 =𝑣 ⋅𝐶 ⋅ 𝑊 ⋅ [𝑉 − 𝑉 − 𝑉’ ]
 Continuity at VDS = V’DSAT
’
’ ’
<1
’ < VGS - Vt
Velocity Sat. vs. Current Sat.
 Velocity saturation always occurs at LOWER VDS than
current saturation

Long Channel vs. Short Channel
L = 2.5 mm L = 0.25 mm
 Short channel transistors: early saturation, less VDS for

same VGS.

vs.
 Qquadratic relation for long channel transistors
 Linear relation for short channel transistors

a-Power Model
𝛽
𝐼 =𝑃 𝑉 −𝑉
2
/
𝑉 =𝑃 𝑉 −𝑉
[Neil, p78] [Sakurai, Newton, JSSC 1990]

Issue #2: Channel Length Modulation (CLM)
 For Sub-micron transistors, we cannot neglect the pinch-off
region (L) any more - effective channel length changes!
 Since L < L,
Why?
 Modified I-V characteristics with CLM

Issue #3: Threshold Voltage Effects
 Vt = Vgs @which the channel starts to invert
 Ideal models assume Vt to be constant
 Really depends (weakly) on almost everything else:
• Body voltage: Body Effect
• Drain voltage: Drain-Induced Barrier Lowering (DIBL)
• Channel: Short/Narrow Channel Effect (ref. to Neil’s book)
- Vt varies with channel length and width

DIBL
 Drain-Induced Barrier Lowering (DIBL)
• High drain voltage causes current to increase

[Chenming Hu, Ch07]
Narain Arora. Mosfet Modeling for VLSI Simulation: Theory and Practice. World Scientific. pp.197, 2007.
Exercise: How to Extract ?
A. Ortiz-Conde et al., A review of recent MOSFET threshold voltage extraction

methods, Microelectronics Reliability, vol. 42, no. 4–5, pp. 583-596, 2002.

Issue #4: Leakage
 What about current in cutoff region?
• Current doesn’t go to 0 in cutoff!

Leakage Components
• : Weak inversion (sub-threshold)
• : Drain-induced barrier lowering
(DIBL)
• : Narrow width effect
• : Gate oxide tunneling
• : Hot carrier injection
• : pn junction reverse bias current
• : Gate-induced drain leakage
(GIDL)
• : Punchthrough
.35μm node, .25μm , W=20μm

Issue #5: Temperature Sensitivity
 Increasing temperature
• Reduces mobility
• Reduces Vt
 ION normally decreases with temperature

 IOFF increases with temperature
I ds
increasing
temperature
Vgs

Next Lecture
 Wire models
Chapter 4

Further Reading

EE213-Topic01-Transistor.97 [Chenming Hu, Ch05] ShanghaiTech University
[Chenming Hu, Ch05]
Another Derivation: Charge Density along the Channel
 The channel potential varies with position along the channel
Areal inversion charge density

[in C/cm2]:
 The current flowing in channel:

 The carrier drift velocity at position , , is
mn is the electron mobility

Drain Current ID (for VDS<VGS-Vt)
Integrating from source to drain:

Transistor in Saturation
 If Vgd < Vt, channel pinches off near drain
• When Vds > Vdsat Vgs – Vt
• Under the influence of the lateral electric field E, carriers drift from
the source (through the inversion layer channel) toward the drain

Switching Trajectory [Contd.]
IL = IDS(VGS=VDD/2, VDS=VDD)
Define Ieff = (IH + IL)/2,
IH = IDS(VGS=VDD, VDS=VDD/2)
M. H. Na, et al., “The effective drive current in CMOS inverters”, IEDM 2002.
Transistors Never in Linear Region During Switching?
 At this given particular snapshot, all series transistors are
in the linear region！
Klaus Von Arnim et al., “An effective switching current methodology to predict
the performance of complex digital circuits”, IEDM 2007.

Velocity Saturation I-V Effects
 Ideal transistor ON current increases with V2DD
 Velocity-saturated ON current increases with VDD
 Real transistors are partially velocity saturated

• Approximate with a-power law model
• Ids  VDDa
• 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)

Short-Channel MOSFET ID-VDS
P. Bai et al. (Intel Corp.),

Int’l Electron Devices Meeting, 2004.
 ID,sat is proportional to VGS-Vt rather than (VGS-Vt)2

 VD,sat is smaller than VGS-Vt

Subthreshold Leakage (I2) + DIBL (I3)
 Exponential subthreshold leakage with Vgs
•n is process dependent
‒ typically 1.3-1.7
 Rewrite relative to Ioff on log scale
• S ≈ 100 mV/decade @ room temperature

• Lower bound: 60 mV/decade @ room temperature
EE213-Topic01-Transistor.106 [Chapter 2.4.4 in Neil’s book] ShanghaiTech University

Gate (Direct) Tunneling Leakage (I7)
 Carriers tunnel through thin gate oxides
• FN tunneling: at high voltage/moderate 𝑡
• Direct tunneling: at low voltage/small 𝑡
 Exponentially sensitive to tox and VDD
• A and B are tech. constants

• Greater for electrons
- So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)

 Critically important at 65 nm and below
(tox ≈ 10.5 Å)
From [Song01]

Junction Leakage (I1, I5, I4)
 Reverse-biased p-n junctions have some leakage
• Ordinary diode leakage (I1)
• Band-to-band tunneling (BTBT, I5)
• Gate-induced drain leakage (GIDL, I4)
Xj: sidewall junction depth

Eg: bandgap voltage

I4 : Gate-Induced Drain Leakage (GIDL)
 Occurs at overlap between gate and drain
• Most pronounced when drain is at VDD, gate is at a negative
voltage
• Thwarts efforts to reduce subthreshold leakage using a negative
gate voltage

Physical Limits in Scaling Si MOSFET
Net result: Bulk-Si CMOS device performance increase

commensurate with size scaling is unlikely beyond 65nm
generation.
[Source: Stanford, EE410, 2009] ShanghaiTech University
Lg scaling
10 10000
Nominal feature size
1 250nm 1000
0.7X every 2
180nm
years
130nm nm
mm
90nm
Gate Length 65nm
45nm
0.1 100
32nm
70nm
22nm
50nm
35nm
~30nm
0.01 10
1970 1980 1990 2000 2010 2020
 With scaling L, need to scale up doping - scale junction

depth (control leakage) – S/D resistance goes up
 External resistance limits current

Parasitic Capacitance Scaling
Reality: Overlap + fringe can be 50% of Cchannel in 32nm

EE213-Topic01-Transistor.112 S. Thompson, Materials Today, 2006. ShanghaiTech University
Problems in Scaling of Gate Oxide
Source: Stanford, EE410, 2009 ShanghaiTech University
Where Performance Comes From

Mobility Enhancements in Strained-Si MOSFETs
Hi-k/Metal gate
K. Mistry, IEDM’07
Replacement gate technology (Intel)
S. Natarajan, IEDM’08

New Structures/Materials for Nanoscale MOSFETs
Non-Classical Scaling
EE213-Topic01-Transistor.118 [Intel, Bohar] ShanghaiTech University

Silicon on Insulator (SOI)
Advantages:
• Elimination of the capacitance between
source/drain regions and body, leading
to higher speed.
• Lower threshold voltage due to smaller
carrier concentration n
Drawback:
• Floating body -> time dependent threshold
variations

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EE213

Digital Integrated Circuits II

Topic 01: Transistor Models

EE213-Topic01-Transistor.1 ShanghaiTech University

EE213-Topic01-Transistor.2 ShanghaiTech University

EE213-Topic01-Transistor.5 ShanghaiTech University

EE213-Topic01-Transistor.6 ShanghaiTech University

EE213-Topic01-Transistor.8 ShanghaiTech University

EE213-Topic01-Transistor.9 ShanghaiTech University

EE213-Topic01-Transistor.10 ShanghaiTech University

EE213-Topic01-Transistor.13 ShanghaiTech University

EE213-Topic01-Transistor.14 ShanghaiTech University

Source Gate Drain

EE213-Topic01-Transistor.15 ShanghaiTech University

Source Gate Drain

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EE213-Topic01-Transistor.17 ShanghaiTech University

EE213-Topic01-Transistor.18 ShanghaiTech University

Want to know how to fabricate such complex things?

EE213-Topic01-Transistor.19 ShanghaiTech University

Vin Vout Vout2

nMOS transistor pMOS transistor

EE213-Topic01-Transistor.20 ShanghaiTech University

EE213-Topic01-Transistor.21 ShanghaiTech University

EE213-Topic01-Transistor.22 ShanghaiTech University

EE213-Topic01-Transistor.23 ShanghaiTech University

EE213-Topic01-Transistor.24 ShanghaiTech University

• One continuous model based on channel surface potential

EE213-Topic01-Transistor.26 ShanghaiTech University

EE213-Topic01-Transistor.27 ShanghaiTech University

Four physical components:

2. Change the surface potential at

3. Offset the depletion region charge

EE213-Topic01-Transistor.29 ShanghaiTech University

EE213-Topic01-Transistor.31 ShanghaiTech University

EE213-Topic01-Transistor.32 ShanghaiTech University

EE213-Topic01-Transistor.33 ShanghaiTech University

EE213-Topic01-Transistor.34 ShanghaiTech University

 In Linear region, Ids depends on

EE213-Topic01-Transistor.36 ShanghaiTech University

C = Cg = eox/tox WL= Cox WL

Not the depletion capacitor! Vox(y) = Vgc(y) – Vt

 Charge is carried by e-, propelled by the lateral electric

 Carrier velocity v proportional to lateral E-field

 Time for carrier to cross channel:

EE213-Topic01-Transistor.38 ShanghaiTech University

EE213-Topic01-Transistor.39 ShanghaiTech University

Areal inversion charge density

 The current flowing in channel:

EE213-Topic01-Transistor.40 ShanghaiTech University

EE213-Topic01-Transistor.41 ShanghaiTech University

EE213-Topic01-Transistor.42 ShanghaiTech University

IDS[A] 3.0E-04 ~ Linear

EE213-Topic01-Transistor.43 ShanghaiTech University

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Vin Propagation delay

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