Manual QuartusII

Compiler User Guide
Intel® Quartus® Prime Pro Edition
Updated for Intel® Quartus® Prime Design Suite: 18.0
Subscribe UG-20132 | 2018.08.15

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Contents
Contents
1. Design Compilation......................................................................................................... 4
1.1. Compilation Overview............................................................................................ 5
1.1.1. Compilation Flows......................................................................................6
1.1.2. Design Synthesis....................................................................................... 6
1.1.3. Design Place and Route.............................................................................. 7
1.1.4. Compilation Hierarchy................................................................................ 8
1.1.5. Reducing Compilation Time......................................................................... 9
1.1.6. Programming File Generation...................................................................... 9
1.2. Running Full Compilation........................................................................................ 9
1.2.1. Concurrent Analysis During Synthesis or Fitting........................................... 10
1.3. Running Synthesis............................................................................................... 11
1.3.1. Preserve Registers During Synthesis........................................................... 12
1.3.2. Enabling Timing-Driven Synthesis.............................................................. 12
1.3.3. Enabling Multi-Processor Compilation..........................................................13
1.3.4. Synthesis Reports.................................................................................... 14
1.4. Running the Fitter................................................................................................ 15
1.4.1. Fitter Stage Commands............................................................................ 16
1.4.2. Incremental Optimization Flow...................................................................16
1.4.3. Analyzing Fitter Snapshots........................................................................ 18
1.4.4. Enabling Physical Synthesis Optimization.................................................... 25
1.4.5. Viewing Fitter Reports.............................................................................. 25
1.5. Running the Hyper-Aware Design Flow....................................................................29
1.5.1. Step 1: Run Register Retiming................................................................... 32
1.5.2. Step 2: Review Retiming Results................................................................ 33
1.5.3. Step 3: Run Fast Forward Compile and Hyper-Retiming................................. 35
1.5.4. Step 4: Review Hyper-Retiming Results...................................................... 37
1.5.5. Step 5: Implement Fast Forward Recommendations......................................40
1.6. Running Rapid Recompile...................................................................................... 42
1.7. Generating Programming Files............................................................................... 43
1.8. Synthesis Language Support................................................................................. 45
1.8.1. Verilog and SystemVerilog Synthesis Support...............................................45
1.8.2. VHDL Synthesis Support........................................................................... 48
1.9. Synthesis Settings Reference.................................................................................50
1.9.1. Optimization Modes..................................................................................50
1.9.2. Prevent Register Retiming......................................................................... 51
1.9.3. Advanced Synthesis Settings..................................................................... 51
1.10. Fitter Settings Reference..................................................................................... 57
1.11. Design Compilation Revision History..................................................................... 63
2. Reducing Compilation Time...........................................................................................65
2.1. Compilation Time Advisor......................................................................................65
2.2. Strategies to Reduce the Overall Compilation Time................................................... 65
2.2.1. Running Rapid Recompile.......................................................................... 65
2.2.2. Enabling Multi-Processor Compilation..........................................................66
2.2.3. Using Block-Based Compilation.................................................................. 67
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time.............................. 68
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time.....68
Compiler User Guide Intel® Quartus® Prime Pro Edition

2
Contents
2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time................................68

2.4. Reducing Placement Time..................................................................................... 68
2.4.1. Placement Effort Multiplier Settings............................................................ 69
2.5. Reducing Routing Time......................................................................................... 69
2.5.1. Identifying Routing Congestion with the Chip Planner....................................69
2.6. Reducing Static Timing Analysis Time..................................................................... 70
2.7. Setting Process Priority.........................................................................................70
2.8. Reducing Compilation Time Revision History............................................................ 71
A. Intel Quartus Prime Pro Edition User Guides................................................................ 72

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1. Design Compilation
The Intel® Quartus® Prime Compiler synthesizes, places, and routes your design
before ultimately generating a device programming file. The Compiler supports a
variety of high-level, HDL, and schematic design entry. The modules of the Compiler
include IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.
Figure 1. Intel Arria® 10 Design in Compilation Dashboard
Runs Module(s)
Opens Settings
Full Compilation
Modules
Enables Optional
Module
Reports
and Analysis
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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The Intel Quartus Prime Pro Edition Compiler supports these advanced features:
• Latest compilation support for Intel Arria® 10, Intel Cyclone® 10 GX, and Intel
Stratix® 10 devices.
• Incremental Fitter optimization—analyze the design and optimize after Fitter each
stage to maximize performance and shorten total compilation time.
• Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for
the highest performance in Intel Stratix 10 devices.
• Partial Reconfiguration—supports dynamic reconfiguration of a portion of the
FPGA, while the remaining FPGA continues to function.
• Block-Based Design Flows—enables preservation of design blocks within a project,
and reuse of those design blocks in other projects.
1.1. Compilation Overview

The Compiler is modular, allowing you to run only the process that you need. Each
Compiler module performs a specific function in the full compilation process. When
you run any module, the Compiler runs any prerequisite modules automatically. The
Compiler generates detailed reports and preserves a "snapshot" of the compilation
results of each stage.
Table 1. Compilation Modules

Compilation Process Description
IP Generation Identifies the status and version IP components in the project.
Analysis & Synthesis Synthesizes, optimizes, minimizes, and maps design logic to device resources.
Analysis & Elaboration is a stage of Analysis & Synthesis. This stage checks for design file
and project errors.
Fitter (Place & Route) Assigns the placement and routing of the design to specific device resources, while
honoring timing and placement constraints. The Fitter includes the following stages:
• Plan—places all periphery elements (such as I/Os and PLLs) and determines a legal
clock plan, without core placement or routing.
• Early Place—places all core elements in an approximate location to facilitate design
planning. Finalizes clock planning for Intel Stratix 10 designs.
• Place—places all core elements in a legal location.
• Route—creates all routing between the elements in the design.
• Retime—moves (retimes) existing registers into Hyper-Registers for fine-grained
performance improvement.(1)
• Finalize—for Intel Arria 10 and Intel Cyclone 10 devices, converts unnecessary tiles to
High-Speed or Low-Power. For Intel Stratix 10 devices, performs post-Route fix-up.
Fast Forward Timing Closure Generates detailed reports that estimate performance gains achievable by making specific
Recommendations RTL modifications.
Timing Analyzer Analyzes and validates the timing performance of all design logic.
Power Analysis Optional module that estimates device power consumption. Specify the electrical standard
on each I/O cell and the board trace model on each I/O standard in your design.
Assembler Converts the Fitter's placement and routing assignments into a programming image for
the FPGA device.
EDA Netlist Writer Generates output files for use in other EDA tools.
(1) Retiming and Fast Forward compilation available only for Intel Stratix 10 devices.

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1.1.1. Compilation Flows

The Intel Quartus Prime Pro Edition Compiler supports a variety of flows to help you
maximize performance and minimize compilation processing time. The modular
Compiler is flexible and efficient, allowing you to run all modules in sequence with a
single command, or to run and optimize each stage of compilation separately.
As you develop and optimize your design, run only the Compiler stages that you need,
rather than waiting for full compilation. Run full compilation only when your design is
complete and you are ready to run all Compiler modules and generate a device
programming image.
Table 2. Compilation Flows

Compiler Flow Function
Early Place Flow Places all core elements in an approximate location to facilitate design planning. Run Early
Place to review initial high-level placement of design elements in the Chip Planner or to
debug and fine-tune timing constraints. This information is useful to guide your floorplanning
decisions.
Implement Flow Runs the Plan, Early Place, Place, Route, and Retime stages. Run this flow when you are
ready to implement placement, routing, and retiming. If successful, you can now perform
the Finalize, Timing Analysis, and Assembler stages. (2)
Incremental Optimization Incremental optimization allows you to stop processing after each stage, analyze the results,
Flow and adjust settings or RTL before proceeding to the next compilation stage. This iterative
flow optimizes at each stage, without waiting for full compilation results.
Hyper-Aware Design Flow Combines automated register retiming (Hyper-Retiming), with implementation of targeted
timing closure recommendations (Fast Forward Compilation), to maximize use of Hyper-
Registers and drive the highest performance in Intel Stratix 10 devices.
Full Compilation Flow Launches all Compiler modules in sequence to synthesize, fit, analyze final timing, and
generate a device programming file.
Partial Reconfiguration Reconfigures a portion of the FPGA dynamically, while the remaining FPGA design continues
to function.
Block-Based Design Flows Supports preservation and reuse of design blocks in one or more projects. You can reuse
synthesized, placed, or routed design blocks within the same project, or export the block to
other projects. Reusable design blocks can include device core or periphery resources.
Related Information
• Incremental Optimization Flow on page 16
• Partial Reconfiguration User Guide
• Block-Based Design User Guide
• Intel Stratix 10 High Performance Design Handbook
1.1.2. Design Synthesis

Design synthesis is the process that translates design source files into an atom netlist
for mapping to device resources. The Intel Quartus Prime Compiler synthesizes
standards-compliant Verilog HDL (.v), VHDL (.vhd), and SystemVerilog (.sv). The
Compiler also synthesizes Block Design File (.bdf) schematic files, and the Verilog
Quartus Mapping (.vqm) files generated by other EDA tools.
(2) Retiming and Hyper-Aware design flow only for Intel Stratix 10 devices.

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Synthesis examines the logical completeness and consistency of the design, and
checks for boundary connectivity and syntax errors. Synthesis also minimizes and
optimizes design logic. For example, synthesis infers D flip flops, latches, and state
machines from "behavioral" languages, such as Verilog HDL, VHDL, and
SystemVerilog. Synthesis may replace operators, such as + or –, with modules from
the Intel Quartus Prime IP library, when advantageous. During synthesis, the Compiler
may change or remove user logic and design nodes. Intel Quartus Prime synthesis
minimizes gate count, removes redundant logic, and ensures efficient use of device
resources.
Figure 2. Design Synthesis

Verilog HDL VHDL Schematic Third Party
(.v or .sv) (.vhd) (.bdf) (.vqm)
Synthesis
Logic Cells I/O DFFs RAM DSP Atom Connections
At the end of synthesis, the Compiler generates an atom netlist. Atom refers to the
most basic hardware resource in the FPGA device. Atoms include logic cells organized
into look-up tables, D flip flops, I/O pins, block memory resources, DSP blocks, and
the connections between the atoms. The atom netlist is a database of the atom
elements that design synthesis requires to implement the design in silicon.
The Analysis & Synthesis module of the Compiler synthesizes design files and creates
one or more project databases for each design partition. You can specify various
settings that affect synthesis processing.
The Compiler preserves the results of Analysis & Synthesis in the synthesis snapshot.
1.1.3. Design Place and Route

The Compiler's Fitter module (quartus_fit) performs design placement and routing.
During place and route, the Fitter determines the best placement and routing of logic
in the target FPGA device, while respecting any Fitter settings or constraints that you
specify.
By default, the Fitter selects appropriate resources, interconnection paths, and pin
locations. If you assign logic to specific device resources, the Fitter attempts to match
those requirements, and then fits and optimizes any remaining unconstrained design
logic. If the Fitter cannot fit the design in the current target device, the Fitter
terminates compilation and issues an error message.

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The Intel Quartus Prime Pro Edition Fitter introduces a hybrid placement technique
that combines analytical and annealing placement techniques. Analytical placement
determines an initial mathematical starting placement. The annealing technique then
fine-tunes logic block placement in high resource utilization scenarios.
The Intel Quartus Prime Pro Edition Compiler allows control and optimization of each
individual Fitter stage, including the Plan, Early Place, Place, and Route stages. After
running a Fitter stage, view detailed report data and analyze the timing of that stage.
The Compiler preserves the results of Fitter stages in the planned, early placed,
placed, routed, retimed, and final snapshots.
Related Information
• Running the Fitter on page 15
• Viewing Fitter Reports on page 25
1.1.4. Compilation Hierarchy

The Intel Quartus Prime Pro Edition Compiler generates a hierarchical project structure
that isolates results of each compilation stage, for each design entity. For example,
the synthesized directory contains a snapshot of the Analysis & Synthesis stage. If
you use design partitions, such as in block-based design, the Compiler also isolates
the results for each design partition. The Compiler fully preserves routing and
placement within a partition. Changes to other portions of the design hierarchy do not
impact the partition. This hierarchical structure allows you to optimize specific design
elements without impacting placement and routing in other partitions. The hierarchical
project structure also supports distributed work groups and compilation processing
across multiple machines.
Figure 3. Hierarchical Project Structure (Intel Stratix 10 Design)

<My_Project> - top-level project directory
qdb - Intel Quartus project database
_compiler - compilation database
<revision_name> - compilation database for revision
_flat - flat design compilation database
<version> - software version
synthesized - synthesis stage compilation snapshot
planned - Plan stage compilation snapshot
early placed - Early Place stage compilation snapshot
placed - Place stage compilation snapshot
routed - Route stage compilation snapshot
retimed - Retime stage compilation snapshot
final - Final stage compilation snapshot
root_partition - Root partition compilation database
- (same subdirectories as _flat partition)
<user_partition> - User partition compilation database
- (same subdirectories as _flat partition)
output_files - reports and other Compiler-generated files

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1.1.5. Reducing Compilation Time

The Intel Quartus Prime Pro Edition software supports various strategies to reduce
overall design compilation time. Running a full compilation including all Compiler
modules on a large design can be time consuming. Use any the following techniques
to reduce the overall compilation times of your design:
• Parallel compilation—the Compiler detects and uses multiple processors to reduce
compilation time (for systems with multiple processor cores).
• Incremental optimization—breaks compilation into separate stages, allowing
iterative analysis of results and optimization of settings at various compilation
stages, prior to running a full compilation.
• Rapid Recompile of changed blocks—the Compiler reuses previous compilation
results and does not reprocess unchanged design blocks. This flow is
recommended for making small design changes in HDL or for adding or changing
Signal Tap debug logic.
1.1.6. Programming File Generation

The Compiler's Assembler module generates files for device programming. Run the
Assembler automatically as part of a full compilation, or run the Assembler module
independently after design place and route. After running the Assembler, use the
Programmer to download configuration data to a device. The Assembler generates one
or more of the following files according to your specification in the Device & Pin
Options dialog box.
Table 3. Assembler Generated Programming Files

Programming File Description
SRAM Object Files (.sof) A binary file containing the data for configuring all SRAM-based Intel FPGA devices.
Programmer Object Files (.pof) A binary file containing the data for programming an EEPROM-based Intel
configuration device. For example, the EPCS16 and EPCS64 devices, which
configure SRAM-based Intel FPGA devices.
Hexadecimal (Intel-Format) Output Contains configuration data that you can program into a parallel data source, such
Files (.hexout) as an EPROM or a mass storage device, which configures an SRAM-based Intel
FPGA device.
Raw Binary Files (.rbf) Contains configuration data that an intelligent external controller uses to configure
an SRAM-based Intel FPGA device.
Tabular Text Files (.ttf) Contains configuration data that an intelligent external controller uses to configure
an SRAM-based Intel FPGA device.
Serial Vector Format File (.svf) Note: Generation of these files not available for Intel Stratix 10 designs.
Related Information
Generating Programming Files on page 43
1.2. Running Full Compilation

Use these steps to run a full compilation of an Intel Quartus Prime project. A full
compilation includes IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and
any optional modules you enable.
1. Before running a full compilation, specify any of the following project settings:

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• To specify the target FPGA device or development kit, click Assignments ➤

Device.
• To specify device and pin options for the target FPGA device, click
Assignments ➤ Device ➤ Device and Pin Options.
• To specify options that affect compilation processing time and netlist
preservation, click Assignments ➤ Settings ➤ Compilation Process
Settings.
• To specify synthesis algorithm and other Advanced Settings for synthesis
and fitting, click Assignments ➤ Settings ➤ Compiler Settings.
• To specify required timing conditions for proper operation of your design, click
Tools ➤ Timing Analyzer.
2. To run full compilation, click Processing ➤ Start Compilation.
Note: Early Place does not run during full compilation by default. To enable Early
Place during full compilation, click Assignments ➤ Settings ➤ Compiler
Settings ➤ Advanced Settings (Fitter) to modify the Run Early Place
during compilation option.
Related Information
• Interface Planning
• The Timing Analyzer
• Managing Device I/O Pins
1.2.1. Concurrent Analysis During Synthesis or Fitting

If you run Analysis & Synthesis, or the Fitter, you can access results while downstream
Fitter stages are still running. Once the Concurrent Analysis icon resolves in the
dashboard, you can use the specific function without interrupting compilation.
During Analysis & Synthesis, you can click the Concurrent Analysis icons on the
Dashboard to view reports, the RTL Viewer, or the Technology Map Viewer. While the
Fitter is processing, you can analyze timing during the stages displaying the Timing
Analyzer icon, and view Technology Map Viewer snapshots during Fitter stages. You
should not modify timing constraints during concurrent analysis, because it affects the
results of the underlying compile. However, you can halt a compile at any time, modify
the .sdc constraints in your source file, and then click the Timing Analyzer icon to
restart analysis with the modified constraints.

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Figure 4. Concurrent Analysis Options
Report Icon
RTL Viewer Icon
Timing Analysis Icon
Technology Map
Viewer Icons
1.3. Running Synthesis

Run design synthesis as part of a full compilation, or as an independent process.
Before running synthesis, specify settings that control synthesis processing. The
Messages window dynamically displays processing information, warnings, or errors.
Following Analysis and Synthesis processing, the Synthesis report provides detailed
information about the synthesis of each design partition.
To run synthesis:
1. Create or open an Intel Quartus Prime project with valid design files for
compilation.
2. Before running synthesis, specify any of the following settings and constraints that
impact synthesis:

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• To specify options for the synthesis of Verilog HDL input files, click
Assignments ➤ Settings ➤ Verilog HDL Input.
• To specify options for the synthesis of VHDL input files, click Assignments ➤
Settings ➤ VHDL Input.
• To specify options that affect compilation processing time, click Assignments
➤ Settings ➤ Compilation Process Settings.
• To specify advanced synthesis settings, click Assignments ➤ Settings ➤
Compiler Settings, and then click Advanced Settings (Synthesis).
Optionally, enable Timing-Driven Synthesis to account for timing constraints
during synthesis.
3. To run synthesis, click Synthesis on the Compilation Dashboard.
Related Information
• Synthesis Settings Reference on page 50
• Concurrent Analysis During Synthesis or Fitting on page 10
1.3.1. Preserve Registers During Synthesis

Intel Quartus Prime synthesis minimizes gate count, merges redundant logic, and
ensures efficient use of device resources. If you need to preserve specific registers
through synthesis processing, you can specify any of the following entity-level
assignments. Use Preserve Resisters in Synthesis or Preserve Fan-Out Free
Register Node to allow Fitter optimization of the preserved registers. Preserve
Resisters restricts Fitter optimization of the preserved registers. Specify synthesis
preservation assignments by clicking Assignments ➤ Assignment Editor, by
modifying the .qsf file, or by specifying synthesis attributes in your RTL.
Table 4. Synthesis Preserve Options

Assignment Description Allows Fitter Assignment Syntax
Optimization?
Preserve Prevents removal of registers during Yes • PRESERVE_REGISTER_SYN_ONLY ON|Off

Registers in synthesis. This settings does not -to <entity> (.qsf)
Synthesis affect retiming or other
• preserve_syn_only or
optimizations in the Fitter.
syn_preservesyn_only (synthesis
attributes)
Preserve Prevents removal of assigned Yes • PRESERVE_REGISTER_FANOUT_FREE_NODE

Fan-Out Free registers without fan-out during ON|Off -to <entity> (.qsf)
Register synthesis.
• no_prune on (synthesis attribute)
Node
Preserve Prevents removal and sequential No • PRESERVE_REGISTER ON|Off -to

Resisters optimization of assigned registers <entity> (.qsf)
during synthesis. Sequential netlist
• preserve, syn_preserve, or keep on
optimizations can eliminate
(synthesis attributes)
redundant registers and registers
with constant drivers.
1.3.2. Enabling Timing-Driven Synthesis

Timing-driven synthesis directs the Compiler to account for your timing constraints
during synthesis. Timing-driven synthesis runs initial timing analysis to obtain netlist
timing information. Synthesis then focuses performance efforts on timing-critical
design elements, while optimizing non-timing-critical portions for area.

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Timing-driven synthesis preserves timing constraints, and does not perform

optimizations that conflict with timing constraints. Timing-driven synthesis may
increase the number of required device resources. Specifically, the number of adaptive
look-up tables (ALUTs) and registers may increase. The overall area can increase or
decrease. Runtime and peak memory use increases slightly.
Intel Quartus Prime Pro Edition runs timing-driven synthesis by default. To enable or
disable this option manually, click Assignments ➤ Settings ➤ Compiler Settings ➤
Advanced Settings (Synthesis).
Related Information
• Running Synthesis on page 11
• Synthesis Language Support on page 45
1.3.3. Enabling Multi-Processor Compilation

The Compiler can detect and use multiple processors to reduce total compilation time.
You specify the number of processors the Compiler uses. The Intel Quartus Prime
software can use up to 16 processors to run algorithms in parallel. The Compiler uses
parallel compilation by default. To reserve some processors for other tasks, specify a
maximum number of processors that the software uses.
This technique reduces the compilation time by up to 10% on systems with two
processing cores, and by up to 20% on systems with four cores. When running timing
analysis independently, two processors reduce the timing analysis time by an average
of 10%. This reduction reaches an average of 15% when using four processors.
The Intel Quartus Prime software does not necessarily use all the processors that you
specify during a given compilation. Additionally, the software never uses more than
the specified number of processors. This fact enables you to work on other tasks
without slowing down your computer. The use of multiple processors does not affect
the quality of the fit. For a given Fitter seed, and given Maximum processors
allowed setting on a specific design, the fit is exactly the same and deterministic.
This remains true, regardless of the target machine, and the number of available
processors. Different Maximum processors allowed specifications produce different
results of the same quality. The impact is similar to changing the Fitter seed setting.
To enable multiprocessor compilation, follow these steps:

1. Open or create an Intel Quartus Prime project.
2. To enable multiprocessor compilation, click Assignments ➤ Settings ➤
Compilation Process Settings.
3. Under Parallel compilation, specify options for the number of processors the
Compiler uses.
4. View detailed information about processor in the Parallel Compilation report
following compilation.
To specify the number of processors for compilation at the command line, use the
following Tcl command in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS <value>
In this case, <value> is an integer from 1 to 16.

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If you want the Intel Quartus Prime software to detect the number of processors
and use all the processors for the compilation, include the following Tcl command
in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
Note: The Compiler detects Intel Hyper-Threading as a single processor. If your

system includes a single processor with Intel Hyper-Threading, set the
number of processors to one. Do not use the Intel Hyper-Threading feature
for Intel Quartus Prime compilations.
1.3.4. Synthesis Reports

The Compilation Report window opens automatically during compilation processing.
The Report window displays detailed synthesis results for each partition in the current
project revision.
Figure 5. Synthesis Reports
Selected
Report
Synthesis
Reports
Table 5. Synthesis Reports (Design Dependent)

Generated Report Description
Summary Shows summary information about synthesis, such as the status, date, software
version, entity name, device family, timing model status, and various types of logic
utilization.
Synthesis Settings Lists the values of all synthesis settings during design processing.
Parallel Compilation Lists specifications for any use of parallel processing during synthesis.
Resource Utilization By Entity Lists the quantity of all types of logic usage for each entity in design synthesis.
Multiplexer Restructuring Provides statistics for the amount of multiplexer restructuring that synthesis performs.
Statistics
continued...

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Generated Report Description
IP Cores Summary Lists details about each IP core instance in design synthesis. Details include IP core
name, vendor, version, license type, entity instance, and IP include file.
Synthesis Source Files Read Lists details about all source files in design synthesis. Details include file path, file type,
and any library information.
Resource Usage Summary for Lists the quantity of all types of logic usage for each design partition in design synthesis.
Partition
RAM Summary for Partition Lists RAM usage details for each design partition in design synthesis. Details include the
name, type, mode, and density.
Register Statistics Lists the number of registers using various types of global signals.
Synthesis Messages Lists all information, warning, and error messages that report conditions observed
during the Analysis & Synthesis process.
1.4. Running the Fitter

The Compiler's Fitter module performs all stages of design place and route, including
the Plan, Early Place, Place, Route and Retime stages. Run all stages of the Fitter as
part of a full design compilation, or run any Fitter stage independently after design
synthesis. You can analyze the results of some Fitter stages, while downstream stages
are still running. Before running the Fitter, you specify settings that tailor placement
and routing results for your requirements.
1. Specify initial Fitter constraints:
a. To assign device I/O pins, click Assignments ➤ Pin Planner.
b. To assign device periphery, clocks, and I/O interfaces, click Tools ➤
Interface Planner.
c. To constrain logic placement regions, click Tools ➤ Chip Planner.
d. To specify general performance, power, or logic usage focus for fitting, click
Assignments ➤ Settings ➤ Compiler Settings.
e. To fine-tune place and route with advanced Fitter options, click Assignments
➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter)
2. To run one or more stages of the Fitter, click any of the following commands on
the Compilation Dashboard:
• To begin device periphery placement and routing, click Plan.
• To run early placement, click Early Place.
• To fully place design logic, click Place.
• To fully route the design, click Route.
• To retime ALM registers into Hyper-Registers, click Retime.(3)
• To run the Implement flow (Plan, Place, Route, and Retime stages), click
Fitter (Implement).
• To run the Finalize flow (Plan, Early Place, Place, Route, Retime, and Finalize
stages), click Fitter (Finalize).
• To run all Fitter stages in sequence, click Fitter.
(3) Retime available for Intel Stratix 10 devices only.

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Related Information
• Fitter Settings Reference on page 57
• Step 2: Review Retiming Results on page 33
1.4.1. Fitter Stage Commands

Launch Fitter processes from the Processing menu or Compilation Dashboard.
Table 6. Fitter Stage Commands

Command Description
Fitter (Implement) Runs the Plan, Early Place, Place, Route, and Retime stages.
Start Fitter (Plan) Loads synthesized periphery placement data and constraints, and assigns periphery
elements to device I/O resources. After this stage, you can run post-Plan timing
analysis to verify timing constraints, and validate cross-clock timing windows. View
the placement and properties of periphery (I/O) and perform clock planning for
Intel Arria 10 and Intel Cyclone 10 designs. This command creates the planned
snapshot.
Start Fitter (Early Place) Places all core elements in an approximate location to facilitate design planning.
After this stage, the Chip Planner displays initial high-level placement of design
elements. The Compilation reports identifies high fan-out signals that increase
placement complexity. Use this information to guide your floorplanning decisions.
For Intel Stratix 10 designs, you can also do early clock planning after this stage.
This command creates the early placed snapshot. Early Place does not run during
the full compilation flow by default, but you can enable by default or run directly
from the Compilation Dashboard.
Start Fitter (Place) Places all core elements in a legal location. This command creates the placed
snapshot.
Start Fitter (Route) Creates all routing between the elements in the design. After this stage, validate
delay chain settings and analyze routing resources. Perform detailed setup and hold
timing closure in the Timing Analyzer and view routing congestion via the Chip
Planner. This command creates the routed snapshot.
Start Fitter (Retime) Performs register retiming and moves existing registers into Hyper-Registers to
increase performance by removing retiming restrictions and eliminating critical
paths. The Compiler may report hold violations for short paths following the Retime
stage. The Fitter identifies and corrects the short paths with hold violations during
the Fitter (Finalize) stage by adding routing wire along the paths. This command
creates the retimed snapshot.
Start Fitter (Finalize) Performs post-routing optimization on the design. This stage converts unneeded
tiles from High Speed to Low Power. This command creates the final snapshot. For
Intel Stratix 10 designs, the Fitter also runs post-route fix-up to correct any short
path hold violations remaining from retiming.
Related Information
Concurrent Analysis During Synthesis or Fitting on page 10
1.4.2. Incremental Optimization Flow

Intel Quartus Prime Pro Edition supports incremental optimization at each stage of
design compilation. In incremental optimization, you run and optimize each
compilation stage independently before running the next compilation module in
sequence. The Compiler preserves the results of each stage as a snapshot for
analysis. When you make changes to your design or constraints, the Compiler only
runs stages impacted by the change. Following synthesis or any Fitter stage, view
results and perform timing analysis. Modify design RTL or Compiler settings, as

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needed. Then, re-run synthesis or the Fitter and evaluate the results of these
changes. Repeat this process until the module performance meets requirements. This
flow maximizes the results at each stage, without waiting for full compilation results.
Figure 6. Incremental Optimization Flow

optimize optimize optimize optimize optimize
Plan Early Place Route Retime

Place
Table 7. Incremental Optimization at Fitter Stages
Fitter Stage Incremental Optimization
Plan After this stage, you can run post-Plan timing analysis to verify timing constraints, and
validate cross-clock timing windows. View the placement and properties of periphery (I/O)
and perform clock planning for Intel Arria 10 and Intel Cyclone 10 designs.
Early Place After this stage, the Chip Planner can display initial high-level placement of design
elements. Use this information to guide your floorplanning decisions. For Intel Stratix 10
designs, you can also review and modify clock assignments after performing this stage.
Place After this stage, validate resource and logic utilization in the Compilation Reports, and
review placement of design elements in the Chip Planner.
Route After this stage, perform detailed setup and hold timing closure in the Timing Analyzer, and
view routing congestion via the Chip Planner.
Retime After this stage, review the Retiming results in the Fitter report and correct any restrictions
limiting further retiming optimization.(4)
1.4.2.1. Early Place Flow

Early Place begins assigning core logic to device resources. Run Early Place to quickly
view the effect of iterative floorplanning changes, without waiting for full placement or
full compilation. The Compiler preserves a snapshot of the Early Place results.
Following Early Place, click the Timing Analyzer icon to validate your .sdc constraints.
Do not use the Early Place timing results to compare with Final timing results, as
timing between early snapshots and the final snapshot are not well correlated.
Early Place runs automatically during Fitter processing if you enable the Early Place
stage on the compilation dashboard, or by enabling Settings ➤ Compiler Settings ➤
Fitter Settings (Advanced) ➤ Run Early Place During Compilation.
1.4.2.2. Running late_place After Early Place

After running the Early Place stage, you can run late_place, rather than the full
Place stage, to reduce total compilation time. late_place skips the placements that
Early Place makes. The Place stage includes the Early Place and late_place stages.
The is no GUI support for the Fitter's late_place option. The late_place option is
(4) Retiming available only for Intel Stratix 10 devices.

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only available at the command line, after running the Early Place stage from the GUI
or command-line. Running late_place generates the placed snapshot. Access
command-line help to display details about the late_place argument.
Note: Type quartus_fit –help=late_place for command-line help on this argument.
To run late_place after Early Place:

1. To run the Early Place stage and generate the Early Place snapshot, perform one
of the following:
• To run Early Place in the GUI, click Early Place on the Compilation
Dashboard. The Compiler runs any required prerequisite stages.
• To run Early Place (and prerequisite stages) at the command-line, run the
following commands. The "-" character equals double hyphens:
quartus_ipgenerate <design_name>
quartus_syn <design name>
quartus_fit -plan <design name>
quartus_fit -early_place <design name>
Note: You must generate the early placed snapshot before running late_place,
or the Fitter reports an error.
2. View Early Place results in the Early Placed Fitter reports of the Compilation
Report, and in the Chip Planner (Tools ➤ Chip Planner).
3. When satisfied with the Early Place results, type one of the following commands to
continue to the late_place stage and beyond. View late_place results and
processing messages in the <design name>.fit.place.rpt file.
• quartus_fit –late_place <design name>
(runs late_place)
• quartus_fit –late_place –route <design name>

(runs late_place and route)
• quartus_fit –late_place –route –finalize <design name>

(runs late_place and finalize)
1.4.3. Analyzing Fitter Snapshots

Analyze the results of Fitter stages to evaluate your design before running the next
stage, or before running a full compilation. Use this technique to isolate potential
problems and reduce the overall time you spend running design compilation. The
following topics describe typical use cases for analyzing Fitter snapshots.
1.4.3.1. Validating SDC Constraints after the Plan Stage

The Fitter's Plan stage performs initial validation of your project's .sdc constraints.
The Compiler generates messages during the plan stage that warn you about any
possible invalid .sdc constraints. Stop compilation following the Plan stage to validate
and make any necessary changes to .sdc constraints, before moving on to the next
Fitter stage. To validate .sdc constraints after the Plan stage, follow these steps:

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1. To run the Fitter's Plan stage, click Plan on the Compilation Dashboard. The
Compiler automatically runs prerequisite compilation stages, if necessary.
2. On the Compilation Dashboard, click the Timing Analyzer icon adjacent to the
Fitter stage. The Create Timing Netlist dialog box appears and loads the
corresponding stage snapshot.
Figure 7. Plan Stage Timing Analyzer Icon in Compilation Dashboard

Access to Reports,
Analysis, and Debugging for Stage
3. In the Create Timing Netlist dialog box, click OK. The planned database loads in
the Timing Analyzer.

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Figure 8. Planned Snapshot in Create Timing Netlist Dialog Box

Loads the Planned Snapshot
for Timing Analysis
4. On the Tasks pane, click Read SDC File. The Timing Analyzer reads and
processes any .sdc files. For multiple .sdc files, the report also includes
the .sdc processing sequence.
Figure 9. Read SDC File Command

Click to Load .sdc Files
5. To report the .sdc constraints that apply to the project, click Report SDC under
the Diagnostic folder, in the Tasks pane.

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Figure 10. SDC File List Report
6. Conversely, to report the constraints in the .sdc files that the Timing Analyzer
ignores, click Report Ignored Constraints under the Diagnostic folder, in the
Tasks pane.
7. To report all paths in your design that have no constraints, click Report
Unconstrained Paths under the Diagnostic folder, in the Tasks pane.
Figure 11. Unconstrained Paths Summary
The Compilation Report displays the Timing Analysis that you run for each stage.
Figure 12. Plan and Retime Stage Timing Analysis Reports in Compilation Report
Compilation Report Lists

Timing Analyses Run
for Each Stage

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1.4.3.2. Validating Periphery (I/O) after the Plan Stage

The Compiler begins periphery placement during the plan stage, and reports data
about periphery elements, such as I/O pins and PLLs. After the Plan stage, view the
Compilation Report to evaluate the placement of periphery elements before
proceeding to the next compilation stage.
Figure 13. Plan Stage Periphery Placement Message
1. In the Compilation Dashboard, click the Plan stage.

2. In the Compilation Report, under the Plan Stage folder, click the Input Pins,
Output Pins, I/O Bank Usage, PLL Usage Summary, or other reports. Verify
attributes of the I/O pins, such as the physical pin location, I/O standards, and PLL
placement.
Figure 14. Input Pins Report
3. For Intel Arria 10 and Intel Cyclone 10 designs, click Global & Other Fast
Signals Summary report to verify which clocks the Compiler promotes to global
clocks. Clock planning occurs after the Early Place stage for Intel Stratix 10
designs.

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Figure 15. Global & Other Fast Signals Report Shows Clock Promotion (Intel Arria 10
and Intel Cyclone 10)
1.4.3.3. Clock Planning after Early Place (Intel Stratix 10 only)

Intel Stratix 10 devices support clock planning after the Early Place stage, rather than
after the Plan stage. After running Early Place, view the Global & Other Fast Signals
report to view details and plan the clocks in your project. To view clock details after
Early Place, follow these steps:
1. In the Compilation Dashboard, click the Early Place stage.
2. In the Compilation Report, under the Early Place Stage folder, click the Global &
Other Fast Signals Details or Global & Other Fast Signals Summary report.
Figure 16. Global & Other Fast Signal Details Report
The report provides clock tree path length and depth. The shortest path length
from clock source to clock tree, and the smallest clock tree depth, results in the
best clock performance.
3. To visualize the clock path length and clock tree depth, click Tools ➤ Chip
Planner.
4. In the Chip Planner Tasks pane, click Report Clock Details under the Clock
Reports folder.
5. In the Report Clock Details dialog box, click OK. The Report pane lists all the
clocks in the design.
6. In the Report pane, select one or more clocks to highlight the clock elements in
Chip Planner.

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Figure 17. Visualizing Clocks in Chip Planner
After running the Early Place stage, you can run late_place, rather than the full
Place stage, to reduce total compilation time.
Related Information
Use CLOCK_REGION to Optimize Clock Constraints, Design Recommendations User
Guide
1.4.3.4. Identifying High Fan-Out Signals after Early Place

High fan-out signals increase placement difficulty. After Early Place, identify and
consider moving high fan-out signals to global resources.
1. In the Compilation Dashboard, click the Early Place stage.
2. In the Compilation Report, under the Early Place Stage folder, click the Non-
Global High Fan-Out Signals report. The report lists the number of fan-outs for
each signal.
Figure 18. Non-Global High Fan-Out Signals Report
3. To visualize the clock fan-out, right-click the signal name in the report, and then
click Locate Node ➤ Locate in Chip Planner.

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Figure 19. Non-Global High Fan-Out Signal in Chip Planner
4. To place those high fan-out signals on global resources, click Assignments ➤

Assignment Editor, and then assign the high fan-out signal to a global signal
before re-starting compilation.
1.4.4. Enabling Physical Synthesis Optimization

Physical synthesis optimization improves circuit performance by performing
combinational and sequential optimization and register duplication.
To enable physical synthesis options:

1. Click Assignments ➤ Settings ➤ Compiler Settings.
2. To enable retiming, combinational optimization, and register duplication, click
Advanced Settings (Fitter). Next, enable Physical Synthesis.
3. View physical synthesis results in the Netlist Optimizations report.
1.4.5. Viewing Fitter Reports

The Fitter generates detailed reports and messages for each stage of place and route.
The Fitter Summary reports basic information about the Fitter run, such as date,
software version, device family, timing model, and logic utilization.
1.4.5.1. Plan Stage Reports

The Plan stage reports describe the I/O, interface, and control signals discovered
during the periphery planning stage of the Fitter.

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Figure 20. Plan Stage Reports (Intel Arria 10 and Intel Cyclone 10 GX Designs)
For Intel Arria 10 and Intel Cyclone 10 designs, the Plan stage includes the Global &
Other Fast Signals Summary report that allows you to verify which clocks the
Compiler promotes to global clocks. Clock planning occurs after the Early Place stage
for Intel Stratix 10 designs.
1.4.5.2. Early Place Stage Reports

During Early Place the Fitter begins assigning core design logic to device resources.
For Intel Stratix 10 designs, the Early Place stage reports include the Global & Other
Fast Signals Summary and Global & Other Fast Signals Details reports. Use
these reports to verify which clocks the Compiler promotes to global clocks. Clock
planning occurs after the Plan stage for Intel Arria 10 and Intel Cyclone 10 designs.
Figure 21. Early Place Stage Reports (Intel Stratix 10 Design)
1.4.5.3. Place Stage Reports

The Place stage reports describe all device resources the Fitter allocates during logic
placement. The report details include the type, number, and overall percentage of
each resource type.

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Figure 22. Place Stage Reports
1.4.5.4. Route Stage Reports

The Route stage reports describe all device resources that the Fitter allocates during
routing. Details include the type, number, and overall percentage of each resource
type. The Route stage also reports delay chain summary information.
Figure 23. Route Stage Reports
1.4.5.5. Retime Stage Reports

The Fitter generates detailed reports showing the results of the Retime stage,
including the Retiming Limit Details report. This report lists the limiting reason, along
with the critical chain and recommendations for the critical chain for each clock
transfer.

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Figure 24. Retiming Limit Details

Retiming Limit Condition
Right-click to locate in viewer Details of Critical Chain
1.4.5.6. Finalize Stage Reports

The Finalize stage reports describe final placement and routing operations, including:
• HSLP Summary. For Intel Arria 10 designs, the Compiler converts unnecessary
tiles to High-Speed or Low-Power (HSLP) tiles.
• Post-route hold fix-up data. For Intel Stratix 10 designs, the Compiler reports hold
violations for short paths following the Retime stage. The Fitter identifies and
corrects the short paths with hold violations during the Fitter (Finalize) stage by
adding routing wire along the paths.

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Figure 25. Finalize Stage Reports (Intel Stratix 10 Design)
Related Information
Step 2: Review Retiming Results on page 33
For information on Retiming and Fast Forward compilation reports
1.5. Running the Hyper-Aware Design Flow

The Intel Quartus Prime Pro Edition Compiler helps you to take full advantage of the
Intel Stratix 10 Intel Hyperflex™ architecture. Use the Hyper-Aware design flow to
shorten design cycles and optimize performance.
The Hyper-Aware design flow combines automated register retiming (Hyper-Retiming),

with implementation of targeted timing closure recommendations (Fast Forward
compilation), to maximize use of Hyper-Registers and drive the highest performance
for Intel Stratix 10 designs.

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Figure 26. Hyper-Aware Design Flow

optimize optimize optimize optimize optimize optimize
Synthesis Plan Early Place Route Retime* Finalize

Place (Hold Fixup)
Fast Forward*
RTL (Hyper-Retiming)
*Intel Stratix 10
Devices Only
Hyper-Retiming
A key innovation of the Intel Stratix 10 architecture is the addition of multiple Hyper-
Registers in every routing segment and block input. Maximizing the use of Hyper-
Registers improves design performance. The prevalence of Hyper-Registers improves
balance of time delays between registers and mitigates critical path delays. Hyper-
Retiming moves registers out of ALMs and retimes them into Hyper-Registers,
wherever advantageous. Hyper-Retiming runs automatically during fitting, requires
minimal effort, and can result in significant performance improvement.
Figure 27. Hyper-Register Architecture

ALM ALM
Hyper-Register Detail
ALM ALM clk Configuration

CRAM
Potential routing path

New Hyper-Registers throughout the core fabric
Fast Forward Compilation
If you require optimization beyond Hyper-Retiming, run Fast Forward compilation to

generate timing closure recommendations that break key performance bottlenecks.
Fast Forward compilation shows precisely where to make the most impact with RTL
changes, and reports the performance benefits you can expect from each change. The
Fitter does not automatically retime registers across RAM and DSP blocks. However,
Fast Forward analysis shows the potential performance benefit from this optimization.
Fast-Forward compilation identifies the best location to add pipeline stages (Hyper-
Pipelining), and the expected performance benefit in each case. After you modify the
RTL to place pipeline stages at the boundaries of each clock domain, the Hyper-
Retimer automatically places the registers within the clock domain at the optimal
locations to maximize performance. Implement the recommendations in RTL to
achieve similar results. After implementing any changes, re-run the Hyper-Retimer

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until the results meet performance and timing requirements. Fast Forward compilation
does not run automatically as part of a full compilation. Enable or run Fast Forward
compilation in the Compilation Dashboard.
Table 8. HyperFlex Optimization Steps

Optimization Step Technique Description
Step 1 Hyper-Retiming Retimer moves existing registers into Hyper-Registers.
Step 2 Fast Forward Compile Compiler generates design-specific timing closure recommendations
and predicts performance improvement.
Step 3 Hyper-Pipelining Use Fast Forward compilation to identify where to add new registers
and pipeline stages in RTL.
Step 4 Hyper-Optimization Design optimization beyond Hyper-Retiming and Hyper-Pipelining,

such as restructuring loops, removing control logic limits, and
reducing the delay along long paths.
The Hyper-Aware design flow includes the following high-level steps this chapter
covers in detail:
1. Run the Retime stage during the Fitter to automatically retime ALM registers into
Hyper-Registers.
2. Review Retiming Results in the Compilation Report.
3. If you require further performance optimization, run Fast Forward compilation.
4. Review Fast Forward timing closure recommendations.
5. Implement appropriate Fast Forward recommendations in your RTL.
6. Recompile the design through the Retime stage.
Figure 28. Hyper-Aware Design Flow

Register Retiming
Run Design Synthesis
Run Fitter with Retime Stage
Review Retiming Results
Fast Forward Compile

No
Performance Run Fast Forward Compile
Met?
Yes Review Recommendations
Modify RTL
Recompile the Design
Yes Performance No
Met?
Analyze Fitter
Timing Finalize

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1.5.1. Step 1: Run Register Retiming

Register retiming improves design performance by moving registers out of ALMs and
retimes them into Hyper-Registers in the Intel Stratix 10 device interconnect.
The Fitter runs the Retime stage automatically following place and route when you
target an Intel Stratix 10 device. Alternatively, start or stop the individual Retime
stage in the Compilation Dashboard. After running register retiming, view the Fitter
reports to optimize remaining critical paths.
To run register retiming:

1. Create or open an Intel Quartus Prime project that is ready for design synthesis
and fitting.
2. To run register retiming, click Retime on the Compilation Dashboard. The
Compiler runs prerequisite stages automatically, as needed. The Compiler
generates detailed reports and timing analysis data for each stage. Click the
Report or Timing Analyzer icons to review results of each stage. Rerun any
stage to apply any setting or design changes.
3. If register retiming achieves all performance goals for your design, proceed to
Fitter (Finalize) and timing analysis stages of compilation. If your design requires
further optimization, run Fast Forward Timing Closure Recommendations.
Figure 29. Retiming Stage in Compilation Dashboard

Click to Open
Stage Reports
Click to
Run Flow

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1.5.2. Step 2: Review Retiming Results

The Fitter generates detailed reports showing the results of the Retime stage. Follow
these steps to review the results and make additional performance improvements with
register retiming.
1. To open the Retiming Limit Details report, click the Report icon for the Retime
stage in the Compilation Dashboard. The Retiming Limit Details lists the
number of registers moved, their paths, and the limiting reason preventing further
retiming.
2. To further optimize, resolve any Limiting Reason in your design, and then rerun
the Retime stage, as necessary.
3. If register retiming achieves all performance goals for your design, proceed to
Fitter (Finalize) and Timing Analysis stages of compilation.
4. If your design requires further optimization, run Fast Forward Timing Closure
Recommendations.
Table 9. Retiming Limit Details Report Data

Report Data Description
Clock Transfer Lists each clock domain in your design. Click the domain to display data about each entry.
Limiting Reason Specifies any design condition that prevent further register retiming improvement, such as
any of the following conditions:
• Insufficient Registers—indicates insufficient quantity of registers at either end of the
chain for retiming. Adding more registers can improve performance.
• Short Path/Long Path—indicates that the critical chain has dependent paths with
conflicting characteristics. For example, one path improves performance with more
registers, and another path has no place for additional registers.
• Path Limit—indicates that there are no further Hyper-Register locations available on the
critical path, or the design reached a performance limit of the current place and route.
• Loops—indicates a feedback path in a circuit. When the critical chain includes a feedback
loop, retiming cannot change the number of registers in the loop without changing
functionality. The Compiler can retime around the loop without changing functionality.
However, the Compiler cannot place additional registers in the loop.
Critical Chain Details Lists register timing path associated with the retiming limitations. Right-click any path to
Locate Critical Chain in Technology Map Viewer.
Figure 30. Retiming Limit Details

Retiming Limit Condition
Right-click to locate in viewer Details of Critical Chain

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Note: The Compiler reports any hold violations for short paths following the
Retime stage. The Fitter identifies and corrects the short paths with hold
violations during the Fitter (Finalize) stage by adding routing wire along the
paths.
1.5.2.1. Locate Critical Chains

The Retiming Limit Details reports the design paths that limit further register
retiming. Right-click any path to locate to the path in the Technology Map Viewer -
Post-fitting view. This viewer displays a schematic representation of the complete
design after place, route, and register retiming. To view the retimed netlist in the
Technology Map Viewer, follow these steps:
1. To open the Retiming Limit Details report, click the Report icon next to the
Retime stage in the Compilation Dashboard.
2. Right-click any path in the Retiming Limit Details report and click Locate
Critical Chain in Technology Map Viewer. The netlist displays as a schematic
in the Technology Map Viewer.
Figure 31. Technology Map Viewer

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Figure 32. Post-Fit Viewer After Retiming

Bypassed ALM Registers Hyper-Register
Used ALM Register
1.5.3. Step 3: Run Fast Forward Compile and Hyper-Retiming

When you run Fast Forward compilation, the Compiler predictively removes signals
from registers to allow mobility within in the netlist for subsequent retiming. Fast
Forward compilation generates design-specific timing closure recommendations, and
predicts maximum performance with removal of all timing restrictions. After you
complete Fast Forward explorations, determine which recommendations you can
implement to provide the most benefit. Implement appropriate recommendations in
your RTL, and recompile the design to realize the performance levels that Fast Forward
reports.
To generate Fast Forward timing closure recommendations, follow these steps:

1. On the Compilation Dashboard, click Fast Forward Timing Closure
Recommendations. The Compiler runs prerequisite synthesis or Fitter stages
automatically, as needed, and generates timing closure recommendations in the
Compilation Report.
2. View timing closure recommendations in the Compilation Report to evaluate
design performance and implement key RTL performance improvements.
3. Optionally, specify any of the following any of the following options if you want to
automate or refine Fast Forward analysis:
• If you want to run Fast Forward compilation during each full compilation, click
Assignments ➤ Settings ➤ Compiler Settings ➤ HyperFlex and enable
Run Fast Forward Timing Closure Recommendations during
compilation.
• If you want to modify how Fast Forward compilation interprets specific I/O and
block types, click Assignments ➤ Settings ➤ Compiler Settings ➤
HyperFlex ➤ Advanced Settings.

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Figure 33. Running Fast Forward Compilation
Fast Forward
Flow
Figure 34. HyperFlex Settings

Run Fast Forward
During Compilation
Fast Forward
Advanced Options

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1.5.3.1. Advanced HyperFlex Settings

The Advanced HyperFlex Settings control how Fast Forward Compilation analyzes
and reports results for specific logical structures in the Intel Hyperflex architecture of
the Intel Stratix 10 FPGA. To access the settings, click Assignments ➤ Settings ➤
HyperFlex ➤ Advanced Settings.
Table 10. Advanced HyperFlex Settings

Option Description
Fast Forward Compile Specifies how Fast Forward analysis accounts for registers with asynchronous clear signals.
Asynchronous Clears The options are:
• Auto—the Compiler identifies asynchronous clears as asynchronous until they limit
timing performance during Fast Forward Compilation, at which point the Compiler
identifies the asynchronous clears as removed.
• Preserve—the Compiler never assumes removal or conversion of asynchronous clears
for Fast Forward analysis.
Fast Forward Compile Specifies how Fast Forward analysis accounts for DSP blocks that limit performance. Enable
Fully Registered DSP this option to generate results as if all DSP blocks are fully registered.
Blocks
Fast Forward Compile Specifies how Fast Forward analysis accounts for RAM blocks that limit performance. Enable
Fully Registered RAM this option to analyze the blocks as fully registered.
Blocks
Fast Forward Compile Specifies the maximum number of pipeline stages that Fast Forward compilation explores.
Maximum Additional
Pipeline Stages
Fast Forward Compile Specifies how Fast Forward compilation accounts for restrictions from user-preserve
User Preserve Directives directives.
1.5.4. Step 4: Review Hyper-Retiming Results

After running Fast Forward Compilation, review the reports in the Fast Forward Timing
Closure Recommendations folder of the Compilation Report to determine which
recommendations are appropriate and practical for your design functionality and
performance goals.
1.5.4.1. Clock Fmax Summary Report

The Clock Fmax Summary in the Fast Forward Timing Closure Recommendations folder
reports the current fmax and potential performance achievable for each clock domain
after Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization steps. Review the
Clock Fmax Summary data to determine whether each potential performance
improvement warrants further investigation and potential optimization of design RTL.
Figure 35. Current and Potential Performance in Clock Fmax Summary

Predicts Optimized Performance After
Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization

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1.5.4.2. Fast Forward Details Report

The Fast Forward Details report recommends the design modifications necessary to
achieve Fast Forward compilation performance levels. Some recommendations may be
functionally impossible or impractical for your design. Consider which
recommendations you can implement in RTL to achieve similar performance
improvement. Click any optimization Step to view the implementation details and
performance calculations for that step.
Table 11. Fast Forward Details Report Data

Report Field Description
Step Displays the pre-optimized Base Performance fMAX, the recommended Fast
Forward optimization steps, and the Fast Forward Limit critical path that
prevents further optimization.
Fast Forward Optimizations Analyzed Summarizes the optimizations necessary to implement each optimization
step.
Estimated Fmax Specifies the potential fMAX performance if you implement all Fast Forward
optimization steps.
Optimizations Analyzed For Fast Lists design recommendations hierarchically for the selected Step. Click the
Forward Step text to expand the report and view the clock domain, the affected module,
and the bus and bits that require modification.
Optimizations Analyzed (Cumulative) Accumulated list of all design changes necessary to reach the selected Step.
Critical Chain at Fast Forward Limit Displays information about any path that continues to limit Hyper-Retiming
even after application of all Fast Forward steps. The critical chain is any path
that limits further Hyper-Retiming. Click the Fast Forward Limit step to
display this field.
Recommendations for Critical Chain Lists register timing path associated with the retiming limitations. Right-click
any path to Locate Critical Chain in Fast Forward Viewer.
Figure 36. Fast-Forward Details Report
Right-click any path to locate to the critical chain in the Fast Forward Viewer. The Fast
Forward Viewer displays a predictive representation of the complete design, after
implementation of all Fast Forward recommendations.

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Figure 37. Recommendations for Critical Chain
Figure 38. Locate Critical Chain in Fast Forward Viewer

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Figure 39. Fast Forward Viewer Shows Predictive Results
1.5.5. Step 5: Implement Fast Forward Recommendations

Implement the Fast Forward timing closure recommendations in your design RTL and
rerun the Retime stage to realize the predictive performance gains. The amount and
type of changes that you implement depends on your performance goals. For
example, if you can achieve the target fMAX with simple asynchronous clear removal or
conversion, you can stop design optimization after making those changes. However, if
you require additional performance, implement more Fast Forward recommendations,
such as any of the following techniques:
• Remove limitations of control logic, such as long feedback loops and state
machines.
• Restructure logic to use functionally equivalent feed-forward or pre-compute
paths, rather than long combinatorial feedback path.
• Reduce the delay of ‘Long Paths’ in the chain. Use standard timing closure
techniques to reduce delay. Excessive combinational logic, sub-optimal placement,
and routing congestion cause delay on paths.
• Insert more pipeline stages in ‘Long Paths’ in the chain. Long paths have the most
delay between registers in the critical chain.
• Increase the delay (or add pipeline stages to ‘Short Paths’ in the chain).
• Explore performance and implement the RTL changes to your code until you reach
the desired performance target.
1.5.5.1. Retiming Restrictions and Workarounds

The Compiler identifies the register chains in your design that limit further
optimization through Hyper-Retiming. The Compiler refers to these related register-to-
register paths as a critical chain. The fMAX of the critical chain and its associated clock
domain is limited by the average delay of a register-to-register path, and quantization
delays of indivisible circuit elements like routing wires. There are a variety of
situations that cause retiming restrictions. Retiming restrictions exist because of
hardware characteristics, software behavior, or are inherent to the design. The
Retiming Limit Details report the limiting reasons preventing further retiming, and

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the registers and combinational nodes that comprise the chain. The Fast Forward
recommendations list the steps you can take to remove critical chains and enable
additional register retiming.
Figure 40. Sample Critical Chain

In this figure the red line represents a same critical chain. Timing restrictions prevent register A from retiming
forward. Timing restrictions also prevent register B from retiming backwards. A loop occurs when register A
and register B are the same register.
A B
Fast Forward recommendations for the critical chain include:
• Reduce the delay of ‘Long Paths’ in the chain. Use standard timing closure
techniques to reduce delay. Combinational logic, sub-optimal placement, and
routing congestion, are among the reasons for path delay..
• Insert more pipeline stages in ‘Long Paths’ in the chain. Long paths are the parts
of the critical chain that have the most delay between registers.
• Increase the delay (or add pipeline stages to ‘Short Paths’ in the chain).
Particular registers in critical chains can limit performance for many other reasons.
The Compiler classifies the following types of reasons that limit further optimization by
retiming:
• Insufficient Registers
• Loop
• Short path/long path
• Path limit
After understanding why a particular critical chain limits your design’s performance,
you can then make RTL changes to eliminate that bottleneck and increase
performance.
Table 12. Hyper-Register Support for Various Design Conditions

Design Condition Hyper-Register Support
Initial conditions that cannot be preserved Hyper-Registers do have initial condition support. However, you cannot
perform some retiming operations while preserving the initial condition stage
of all registers (that is, the merging and duplicating of Hyper-Registers). If
this condition occurs in the design, the Fitter does not retime those registers.
This retiming limit ensures that the register retiming does not affect design
functionality.
Register has an asynchronous clear Hyper-Registers support only data and clock inputs. Hyper-Registers do not
have control signals such as asynchronous clears, presets, or enables. The
Fitter cannot retime any register that has an asynchronous clear. Use
asynchronous clears only when necessary, such as state machines or control
logic. Often, you can avoid or remove asynchronous clears from large parts
of a datapath.
Register drives an asynchronous signal This design condition is inherent to any design that uses asynchronous
resets. Focus on reducing the number of registers that are reset with an
asynchronous clear.
continued...

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Design Condition Hyper-Register Support
Register has don’t touch or preserve The Compiler does not retime registers with these attributes. If you use the
attributes preserve attribute to manage register duplication for high fan-out signals, try
removing the preserve attribute. The Compiler may be able to retime the
high fan-out register along each of the routing paths to its destinations.
Alternatively, use the dont_merge attribute. The Compiler retimes registers
in ALMs, DDIOs, single port RAMs, and DSP blocks.
Register is a clock source This design condition is uncommon, especially for performance-critical parts
of a design. If this retiming restriction prevents you from achieving the
required performance, consider whether a PLL can generate the clock, rather
than a register.
Register is a partition boundary This condition is inherent to any design that uses design partitions. If this
retiming restriction prevents you from achieving the required performance,
add additional registers inside the partition boundary for Hyper-Retiming.
Register is a block type modified by an This restriction is uncommon. Avoid the restriction by making the functional
ECO operation change in the design source and recompiling, rather than performing an
ECO.
Register location is an unknown block This restriction is uncommon. You can often work around this condition by
adding extra registers adjacent to the specified block type.
Register is described in the RTL as a latch Hyper-Registers cannot implement latches. The Compiler infers latches
because of RTL coding issues, such as incomplete assignments. If you do not
intend to implement a latch, change the RTL.
Register location is at an I/O boundary All designs contain I/O, but you can add additional pipeline stages next to
the I/O boundary for Hyper-Retiming.
Combinational node is fed by a special This condition is uncommon, especially for performance-critical parts of a
source design.
Register is driven by a locally routed clock Only the dedicated clock network clocks Hyper-Registers. Using the routing
fabric to distribute clock signals is uncommon, especially for performance-
critical parts of a design. Consider implementing a small clock region instead.
Register is a timing exception end-point The Compiler does not retime registers that are sources or destinations
of .sdc constraints.
Register with inverted input or output This condition is uncommon.
Register is part of a synchronizer chain The Fitter optimizes synchronizer chains to increase the mean time between
failure (MTBF), and the Compiler does not retime registers that are detected
or marked as part of a synchronizer chain. Add more pipeline stages at the
clock domain boundary adjacent to the synchronizer chain to provide
flexibility for the retiming.
Register with multiple period requirements This situation occurs at any cross-clock boundary, where a register latches
for paths that start or end at the register data on a clock at one frequency, and fans out to registers running at
(cross-clock boundary) another frequency. The Compiler does not retime registers at cross-clock
boundaries. Consider adding additional pipeline stages at one side of the
clock domain boundary, or the other, to provide flexibility for retiming.
The following topics describes RTL design techniques that you can use to remove
retiming restrictions.
1.6. Running Rapid Recompile

During Rapid Recompile the Compiler reuses previous synthesis and fitting results
whenever possible, and does not reprocess unchanged design blocks. Use Rapid
Recompile to reduce timing variations and the total recompilation time after making
small design changes.

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Figure 41. Rapid Recompile

E
A Changed
J
B G
y
C x z
D
Unchanged
Regular Compile
Rapid
Recompile
To run Rapid Recompile, follow these steps:

1. To start Rapid Recompile following an initial compilation (or after running the
Route stage of the Fitter), click Processing ➤ Start ➤ Start Rapid Recompile.
Rapid Recompile implements the following types of design changes without full
recompilation:
• Changes to nodes tapped by the Signal Tap Logic Analyzer
• Changes to combinational logic functions
• Changes to state machine logic (for example, new states, state transition
changes)
• Changes to signal or bus latency or addition of pipeline registers
• Changes to coefficients of an adder or multiplier
• Changes register packing behavior of DSP, RAM, or I/O
• Removal of unnecessary logic
• Changes to synthesis directives
2. Click the Rapid Recompile Preservation Summary report to view detailed
information about the percentage of preserved compilation results.
Figure 42. Rapid Recompile Preservation Summary
1.7. Generating Programming Files

The Compiler's Assembler module generates device programming files. Run the
Assembler to generate device programming files following successful design place and
route.

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1. Before running the Assembler, specify settings to customize programming file

generation. Click Assignments ➤ Device ➤ Device & Pin Options to enable or
disable generation of optional programming files.
2. To generate device programming files, click Processing ➤ Start ➤ Start
Assembler, or click Assembler on the Compilation Dashboard. The Compiler
confirms that prerequisite modules are complete, and launches the Assembler
module to generate the programming files that you specify. The Messages window
dynamically displays processing information, warnings, or errors. After Assembler
processing,
After running the Assembler, the Compilation report provides detailed information
about programming file generation, including programming file Summary and
Encrypted IP information.
Figure 43. Assembler Reports
Figure 44. Device & Pin Options

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Related Information
Programming Intel FPGA Devices
1.8. Synthesis Language Support

The Intel Quartus Prime software synthesizes standard Verilog HDL, VHDL, and
SystemVerilog design files.
1.8.1. Verilog and SystemVerilog Synthesis Support

Intel Quartus Prime synthesis supports the following Verilog HDL language standards:
• Verilog-1995 (IEEE Standard 1364-1995)
• Verilog-2001 (IEEE Standard 1364-2001)
• SystemVerilog-2005 (IEEE Standard 1800-2005)
• SystemVerilog-2009 (IEEE Standard 1800-2009)
The following important guidelines apply to Intel Quartus Prime synthesis of Verilog
HDL and SystemVerilog:
• The Compiler uses the Verilog-2001 standard by default for files with an extension
of .v, and the SystemVerilog standard for files with the extension of .sv.
• If you use scripts to add design files, you can use the -HDL_VERSION command
to specify the HDL version for each design file.
• Compiler support for Verilog HDL is case sensitive in accordance with the Verilog
HDL standard.
• The Compiler supports the compiler directive `define, in accordance with the
Verilog HDL standard.
• The Compiler supports the include compiler directive to include files with
absolute paths (with either “/” or “\” as the separator), or relative paths.
• When searching for a relative path, the Compiler initially searches relative to the
project directory. If the Compiler cannot find the file, the Compiler next searches
relative to all user libraries. Finally, the Compiler searches relative to the current
file's directory location.
• Intel Quartus Prime Pro Edition synthesis searches for all modules or entities
earlier in the synthesis process than other Quartus software tools. This earlier
search produces earlier syntax errors for undefined entities than other Quartus
software tools.
Related Information
• The Quartus Prime Timing Analyzer
• Recommended Design Practices
• Recommended HDL Coding Styles
1.8.1.1. Verilog HDL Input Settings (Settings Dialog Box)

Click Assignments ➤ Settings ➤ Verilog HDL Input to specify options for the
synthesis of Verilog HDL input files.

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Figure 45. Verilog HDL Input Settings Dialog Box
Table 13. Verilog HDL Input Settings

Setting Description
Verilog Version Directs synthesis to process Verilog HDL input design files using the specified standard.
You can select any of the supported language standards to match your Verilog HDL files
or SystemVerilog design files.
Library Mapping File Allows you to optionally specify a provided Library Mapping File (.lmf) for use in
synthesizing Verilog HDL files that contain non-Intel FPGA functions mapped to IP
cores. You can specify the full path name of the LMF in the File name box.
Verilog HDL Macro Verilog HDL macros are pre-compiler directives which can be added to Verilog HDL files
to define constants, flags, or other features by Name and Setting. Macros that you
add appear in the Existing Verilog HDL macro settings list.
1.8.1.2. Design Libraries

By default, the Compiler processes all design files into one or more libraries.
• When compiling a design instance, the Compiler initially searches for the entity in
the library associated with the instance (which is the work library if you do not
specify any library).
• If the Compiler cannot locate the entity definition, the Compiler searches for a
unique entity definition in all design libraries.
• If the Compiler finds more than one entity with the same name, the Compiler
generates an error. If your design uses multiple entities with the same name, you
must compile the entities into separate libraries.
1.8.1.3. Verilog HDL Configuration

Verilog HDL configuration is a set of rules that specify the source code for particular
instances. Verilog HDL configuration allows you to perform the following tasks:

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• Specify a library search order for resolving cell instances (as does a library
mapping file).
• Specify overrides to the logical library search order for specified instances.
• Specify overrides to the logical library search order for all instances of specified
cells.
1.8.1.3.1. Hierarchical Design Configurations

A design can have more than one configuration. For example, you can define a
configuration that specifies the source code you use in particular instances in a sub-
hierarchy, and then define a configuration for a higher level of the design.
For example, suppose a subhierarchy of a design is an eight-bit adder, and the RTL
Verilog code describes the adder in a logical library named rtllib. The gate-level
code describes the adder in the gatelib logical library. If you want to use the gate-
level code for the 0 (zero) bit of the adder and the RTL level code for the other seven
bits, the configuration might appear as follows:
Example 1. Gate-level code for the 0 (zero) bit of the adder

config cfg1;
design aLib.eight_adder;
default liblist rtllib;
instance adder.fulladd0 liblist gatelib;
endconfig
If you are instantiating this eight-bit adder eight times to create a 64-bit adder, use
configuration cfg1 for the first instance of the eight-bit adder, but not in any other
instance. A configuration that performs this function is shown below:
Example 2. Use configuration cfg1 for first instance of eight-bit adder

config cfg2;
design bLib.64_adder;
default liblist bLib;
instance top.64add0 use work.cfg1:config;
endconfig
Note: The name of the unbound module may be different from the name of the cell that is
bounded to the instance.
1.8.1.4. Initial Constructs and Memory System Tasks

The Intel Quartus Prime software infers power-up conditions from the Verilog HDL
initial constructs. The Intel Quartus Prime software also creates power-up settings
for variables, including RAM blocks. If the Intel Quartus Prime software encounters
non-synthesizable constructs in an initial block, it generates an error.
To avoid such errors, enclose non-synthesizable constructs (such as those intended

only for simulation) in translate_off and translate_on synthesis directives.
Synthesis of initial constructs enables the power-up state of the synthesized design to
match the power-up state of the original HDL code in simulation.
Note: Initial blocks do not infer power-up conditions in some third-party EDA synthesis tools.
If you convert between synthesis tools, you must set your power-up conditions
correctly.

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Intel Quartus Prime synthesis supports the $readmemb and $readmemh system tasks
to initialize memories.
Example 3. Verilog HDL Code: Initializing RAM with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
When creating a text file to use for memory initialization, specify the address using
the format @<location> on a new line, and then specify the memory word such as
110101 or abcde on the next line.
The following example shows a portion of a Memory Initialization File (.mif) for the
RAM.
Example 4. Text File Format: Initializing RAM with the readmemb Command
@0
00000000
@1
00000001
@2
00000010
…
@e
00001110
@f
00001111
1.8.1.5. Verilog HDL Macros

The Intel Quartus Prime software fully supports Verilog HDL macros, which you can
define with the 'define compiler directive in your source code. You can also define
macros in the Intel Quartus Prime software or on the command line.
To set Verilog HDL macros at the command line for the Intel Quartus Prime Pro Edition
synthesis (quartus_syn) executable, use the following format:
quartus_syn <PROJECT_NAME> --set=VERILOG_MACRO=a=2
This command adds the following new line to the project .qsf file:
set_global_assignment -name VERILOG_MACRO "a=2"
To avoid adding this line to the project .qsf, add this option to the quartus_syn
command:
--write_settings_files=off
1.8.2. VHDL Synthesis Support

Intel Quartus Prime synthesis supports the following VHDL language standards.
• VHDL 1987 (IEEE Standard 1076-1987)

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The Intel Quartus Prime Compiler uses the VHDL 1993 standard by default for files
that have the extension .vhdl or .vhd.
Note: The VHDL code samples follow the VHDL 1993 standard.
Related Information
Migrating to Quartus Prime Pro Edition
1.8.2.1. VHDL Input Settings (Settings Dialog Box)

Click Assignments ➤ Settings ➤ VHDL Input to specify options for the synthesis of
VHDL input files.
Table 14. VHDL Input Settings

Setting Description
VHDL Version Specifies the VHDL standard for use during synthesis of VHDL input design files. Select
the language standards that corresponds with the VHDL files.
Library Mapping File Specifies a Library Mapping File (.lmf) for use in synthesizing VHDL files that contain
IP cores. Specify the full path name of the LMF in the File name box.
Figure 46. VHDL Input Settings Dialog Box
1.8.2.2. VHDL Standard Libraries and Packages

The Intel Quartus Prime software includes the standard IEEE libraries and several
vendor-specific VHDL libraries. The IEEE library includes the standard VHDL packages
std_logic_1164, numeric_std, numeric_bit, and math_real.

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The STD library is part of the VHDL language standard and includes the packages
standard (included in every project by default) and textio. For compatibility with
older designs, the Intel Quartus Prime software also supports the following vendor-
specific packages and libraries:
• Synopsys packages such as std_logic_arith and std_logic_unsigned in
the IEEE library.
• Mentor Graphics* packages such as std_logic_arith in the ARITHMETIC
library.
• Primitive packages altera_primitives_components (for primitives such as
GLOBAL and DFFE) and maxplus2 in the ALTERA library.
• IP core packages altera_mf_components in the ALTERA_MF library for specific
IP cores including LCELL. In addition, lpm_components in the LPM library for
library of parameterized modules (LPM) functions.
Note: Import component declarations for primitives such as GLOBAL and DFFE from the
altera_primitives_components package and not the altera_mf_components
package.
1.8.2.3. VHDL wait Constructs

The Intel Quartus Prime software supports one VHDL wait until statement per
process block. However, the Intel Quartus Prime software does not support other
VHDL wait constructs, such as wait for and wait on statements, or processes with
multiple wait statements.
Example 5. VHDL wait until construct example

architecture dff_arch of ls_dff is
begin
output: process begin
wait until (CLK'event and CLK='1');
Q <= D;
Qbar <= not D;
end process output;
end dff_arch;
1.9. Synthesis Settings Reference

This section provides a reference to all synthesis settings. Use these settings to
customize synthesis processing for your design goals.
1.9.1. Optimization Modes

The following options direct the focus of Compiler optimization efforts during
synthesis. The settings affect synthesis and fitting.

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Table 15. Optimization Modes (Compiler Settings Page)

Optimization Mode Description
Balanced (Normal Flow) Optimizes synthesis for balanced implementation that respects timing constraints.
Performance (High effort - Makes high effort to optimize synthesis for speed performance. High effort increases
increases runtime) synthesis run time.
Performance (Aggressive - Makes aggressive effort to optimize synthesis for speed performance. Aggressive effort
increases runtime and area) increases synthesis run time and device resource use.
Power (High effort - increases Makes high effort to optimize synthesis for low power. High effort increases synthesis
runtime) run time.
Power (Aggressive - Makes aggressive effort to optimize synthesis for low power. Aggressive effort
increases runtime, reduces increases synthesis time and reduces speed performance.
performance)
Area (Aggressive - reduces Makes aggressive effort to reduce the device area required to implement the design.
performance)
Compile Time (Aggressive - Reduces the compile time required to implement the design with reduced effort and
reduces performance) fewer performance optimizations. This option also disables some detailed reporting
functions.
Note: Turning on Aggressive Compile Time mode enables Intel Quartus Prime
Settings File (.qsf) settings which cannot be overridden by other .qsf
settings.
1.9.2. Prevent Register Retiming

The Prevent Register Retiming option controls whether or not to globally disable
retiming. When set to disabled, the Compiler automatically performs register
retiming optimizations, moving registers through combinational logic. When set to
enabled, the Compiler prevents any retiming optimizations on a global scale.
Optionally, assign Allow Register Retiming to any design entity or instance to
override Prevent Register Retiming for specific portions of the design. Click
Assignments ➤ Assignment Editor to specify entity- and instance-level
assignments, or use the following syntax to make the assignment in the .qsf directly.
Example 6. Disable register retiming for entity abc

set_global_assignment –name ALLOW_REGISTER_RETIMING ON
set_instance_assignment –name ALLOW_REGISTER_RETIMING OFF –to “abc|”
set_instance_assignment –name ALLOW_REGISTER_RETIMING ON –to “abc|def|”
Example 7. Disable register retiming for the whole design, except for registers in entity
abc
set_global_assignment –name ALLOW_REGISTER_RETIMING OFF
set_instance_assignment –name ALLOW_REGISTER_RETIMING ON –to “abc|”
set_instance_assignment –name ALLOW_REGISTER_RETIMING OFF –to “abc|def|”
1.9.3. Advanced Synthesis Settings

The following section is a quick reference of all Advanced Synthesis Settings. Click
Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings
(Synthesis) to modify these settings.

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Table 16. Advanced Synthesis Settings (1 of 13)

Option Description
Allow Any RAM Size for Allows the Compiler to infer RAMs of any size, even if the RAMs do not meet the current
Recognition minimum requirements.
Allow Any ROM Size for Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's
Recognition current minimum size requirements.
Allow Any Shift Register Allows the Compiler to infer shift registers of any size even if they do not meet the
Size for Recognition design's current minimum size requirements.
Allow Register Duplication Controls whether the Compiler duplicates registers to improve design performance.
When enabled, the Compiler performs optimization that creates a second copy of a
register and move a portion of its fan-out to this new node. This technique improves
routability and reduces the total routing wire required to route a net with many fan-
outs. If you disable this option, retiming of registers is also disabled.
Note: Not available for Intel Stratix 10 devices.
Allow Register Merging Controls whether the Compiler removes (merges) identical registers. When enabled, in
cases where two registers generate the same logic, the Compiler may delete one
register and fan-out the remaining register to the deleted register's destinations. This
option is useful if you want to prevent the Compiler from removing duplicate registers
that you have used deliberately. When disabled, retiming optimizations are also
disabled.
Allow Shift Register Merging Allows the Compiler to take shift registers from different hierarchies of the design and
Across Hierarchies put the registers in the same RAM.
Allow Synchronous Control Allows the Compiler to utilize synchronous clear and synchronous load signals in normal
Signals mode logic cells. Turning on this option helps to reduce the total number of logic cells
used in the design, but can negatively impact the fitting. This negative impact occurs
because all the logic cells in a LAB share synchronous control signals.

Option Description
Analysis & Synthesis Specifies the type of Analysis & Synthesis messages the Compiler display. Low displays
Message Level only the most important Analysis & Synthesis messages. Medium displays most
messages, but hides the detailed messages. High displays all messages.
Auto Carry Chains Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers
into the design. The Carry Chain Length option controls the length of the chains. When
this option is off, the Compiler ignores CARRY buffers, but CARRY_SUM buffers are
unaffected. The Compiler ignores the Auto Carry Chains option if you select Product
Term or ROM as the setting for the Technology Mapper option.
Auto Clock Enable Allows the Compiler to locate logic that feeds a register and move the logic to the
Replacement register's clock enable input port.
Auto DSP Block Allows the Compiler to find a multiply-accumulate function or a multiply-add function
Replacement that can be replaced with a DSP block.
Auto Gated Clock Conversion Automatically converts gated clocks to use clock enable pins. Clock gating logic can
contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use
and overall run time. You must use the Timing Analyzer for timing analysis, and you
must define all base clocks in Synopsys Design Constraints (.sdc) format.

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Option Description
Auto Open-Drain Pins Allows the Compiler to automatically convert a tri-state buffer with a strong low data
input into the equivalent open-drain buffer.
Auto RAM Replacement Allows the Compiler to identify sets of registers and logic that it can replace with the
altsyncram or the lpm_ram_dp IP core. Turning on this option may change the
functionality of the design.
Auto ROM Replacement Allows the Compiler to identify logic that it can replace with the altsyncram or the
lpm_rom IP core. Turning on this option may change the power-up state of the design.
Auto Resource Sharing Allows the Compiler to share hardware resources among many similar, but mutually
exclusive, operations in your HDL source code. If you enable this option, the Compiler
merges compatible addition, subtraction, and multiplication operations. Merging
operations may reduce the area your design requires. Because resource sharing
introduces extra muxing and control logic on each shared resource, it may negatively
impact the final fMAX of your design.
Auto Shift Register Allows the Compiler to find a group of shift registers of the same length that are
Placement replaceable with the altshift_taps IP core. The shift registers must all use the same clock
and clock enable signals. The registers must not have any other secondary signals. The
registers must have equally spaced taps that are at least three registers apart.
Automatic Parallel Synthesis Option to enable/disable automatic parallel synthesis. Use this option to speed up
synthesis compile time by using multiple processors when available.

Option Description
Block Design Naming Specifies the naming scheme for the block design. The Compiler ignores the option if
you assign the option to anything other than a design entity.
Carry Chain Length Specifies the maximum allowable length of a chain for CARRY_SUM buffers, including
those that you or the Compiler instantiate. The Compiler breaks carry chains that
exceed this length into separate chains.
Clock MUX Protection Causes the multiplexers in the clock network to decompose to 2-to-1 multiplexer trees.
The Compiler protects these trees from merging with, or transferring to, other logic. This
option helps the Timing Analyzer to analyze clock behavior.
Create Debugging Nodes for Makes certain nodes (for example, important registers, pins, and state machines) visible
IP Cores for all the IP cores in a design. Use IP core nodes to effectively debug the IP core. This
technique is effective when using the IP core with the Signal Tap Logic Analyzer. The
Node Finder, using Signal Tap Logic Analyzer filters, displays all the nodes that Analysis
& Synthesis makes visible. When making the debugging nodes visible, Analysis &
Synthesis can change the fMAX and number of logic cells in IP cores.
DSP Block Balancing Allows you to control the conversion of certain DSP block slices during DSP block
balancing.

Option Description
Disable DSP Negate Allows you to specify whether to use the negate port on an inferred DSP block.
Inferencing
Disable Register Merging Specifies whether the Compiler allows merging of registers that are in different
Across Hierarchies hierarchies if their inputs are the same.
Enable State Machines Allows the Compiler to infer state machines from VHDL or Verilog HDL design files. The
Inference Compiler optimizes state machines to reduce area and improve performance. If set to
Off, the Compiler extracts and optimizes state machines in VHDL or Verilog HDL design
files as regular logic.
continued...

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Option Description
Force Use of Synchronous Forces the Compiler to utilize synchronous clear signals in normal mode logic cells.
Clear Signals Enabling this option helps to reduce the total number of logic cells in the design, but can
negatively impact the fitting. All the logic cells in a LAB share synchronous control
signals.
HDL Message Level Specifies the type of HDL messages you want to view, including messages that display
processing errors in the HDL source code. Level1 displays only the most important HDL
messages. Level2 displays most HDL messages, including warning and information
based messages. Level3 displays all HDL messages, including warning and information
based messages and alerts about potential design problems or lint errors.
Ignore CARRY Buffers Ignores CARRY_SUM buffers in the design. The Compiler ignores this option if you apply
the option to anything other than an individual CARRY_SUM buffer, or to a design entity
containing CARRY_SUM buffers.
Ignore CASCADE Buffers Ignores CASCADE buffers that are instantiated in the design. The Compiler ignores this
option if you apply the option to anything other than an individual CASCADE buffer, or a
design entity containing CASCADE buffers.

Option Description
Ignore GLOBAL Buffers Ignores GLOBAL buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual GLOBAL buffer, or a design entity containing
GLOBAL buffers.
Ignore LCELL Buffers Ignores LCELL buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual LCELL buffer, or a design entity containing
LCELL buffers.
Ignore Maximum Fan-Out Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity,
Assignments or the whole design.
Ignore ROW GLOBAL Buffers Ignores ROW GLOBAL buffers in the design. The Compiler ignores this option if you apply
the option to anything other than an individual GLOBAL buffer or a design entity
containing GLOBAL buffers.
Ignore SOFT Buffers Ignores SOFT buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual SOFT buffer or a design entity containing
SOFT buffers.

Option Description
Ignore translate_off and Ignores all translate_off/synthesis_off synthesis directives in Verilog HDL and
synthesis_off Directives VHDL design files. Use this option to disable these synthesis directives and include
previously ignored code during elaboration.
Infer RAMs from Raw Logic Infers RAM from registers and multiplexers. The Compiler initially converts some HDL
patterns differing from RAM templates into logic. However, these structures function as
RAM. As a result, when you enable this option, the Compiler may substitute the
altsyncram IP core instance for them at a later stage. When you enable this assignment,
the Compiler may use more device RAM resources and fewer LABs.
Iteration Limit for Constant Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-
Verilog Loops time constants on each loop iteration. This limit exists primarily to identify potential
infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Iteration Limit for non- Defines the iteration limit for Verilog HDL loops with loop conditions that do not evaluate
Constant Verilog Loops to compile-time constants on each loop iteration. This limit exists primarily to identify
potential infinite loops before they exhaust memory or trap the software in an actual
infinite loop.

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Option Description
Limit AHDL integers to 32 Specifies whether an AHDL-based design must have a limit on integer size of 32 bits.
Bits The Compiler provides this option for backward compatibility with pre-2000.09 releases
of the Intel Quartus Prime software. Such registers do not support integers larger than
32 bits in AHDL.
Maximum DSP Block Usage Specifies the maximum number of DSP blocks that the DSP block balancer assumes
exist in the current device for each partition. This option overrides the usual method of
using the maximum number of DSP blocks the current device supports.
Maximum Number of LABs Specifies the maximum number of LABs that Analysis & Synthesis should try to utilize
for a device. This option overrides the usual method of using the maximum number of
LABs the current device supports, when the value is non-negative and is less than the
maximum number of LABs available on the current device.
Maximum Number of Specifies the maximum number of M4K, M9K, M20K, or M10K memory blocks that the
M4K/M9K/M20K/M10K Compiler may use for a device. This option overrides the usual method of using the
Memory Blocks maximum number of M4K, M9K, M20K, or M10K memory blocks the current device
supports, when the value is non-negative and is less than the maximum number of M4K,
M9K, M20K, or M10K memory blocks available on the current device.

Option Description
Maximum Number of Specifies the maximum number of registers that Analysis & Synthesis uses for
Registers Created from conversion of uninferred RAMs. Use this option as a project-wide option or on a specific
Uninferred RAMs partition by setting the assignment on the instance name of the partition root. The
assignment on a partition overrides the global assignment (if any) for that particular
partition. This option prevents synthesis from causing long compilations and running out
of memory when many registers are used for uninferred RAMs. Instead of continuing the
compilation, the Intel Quartus Prime software issues an error and exits.
NOT Gate Push-Back Allows the Compiler to push an inversion (that is, a NOT gate) back through a register
and implement it on that register's data input if it is necessary to implement the design.
When this option is on, a register may power-up to an active-high state, and may need
explicit clear during initial operation of the device. The Compiler ignores this option if
you apply it to anything other than an individual register or a design entity containing
registers. When you apply this option to an output pin that is directly fed by a register,
the assignment automatically transfers to that register.
Number of Inverted Specifies the maximum number of inverted registers that the Synthesis report displays.
Registers Reported in
Synthesis Report
Number of Protected Specifies the maximum number of protected registers that the Synthesis Report
Registers Reported in displays.
Synthesis Report
Number of Removed Specifies the maximum number of rows that the Synthesis Migration Check report
Registers Reported in displays.
Synthesis Migration Checks
Number of Swept Nodes Specifies the maximum number of swept nodes that the Synthesis Report displays. A
Reported in Synthesis swept node is any node which was eliminated from your design because the Compiler
Report found the node to be unnecessary.
Number of Rows Reported in Specifies the maximum number of rows that the Synthesis report displays.
Synthesis Report Note: Not available for Intel Stratix 10 devices.
Optimization Technique Specifies an overall optimization goal for Analysis & Synthesis. The Compiler can
maximize synthesis processing for performance, minimize logic usage, or balance high
performance with minimal logic usage.

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Option Description
Perform WYSIWYG Primitive Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This
Resynthesis option uses the setting specified in the Optimization Technique logic option.
Power-Up Don't Care Causes registers that do not have a Power-Up Level logic option setting to power-up
with a do not care logic level (X). When the Power-Up Don't Care option is on, the
Compiler determines when it is beneficial to change the power-up level of a register to
minimize the area of the design. The Compiler maintains a power-up state of zero,
unless there is an immediate area advantage.
Power Optimization During Controls the power-driven compilation setting of Analysis & Synthesis. This option
Synthesis determines how aggressively Analysis & Synthesis optimizes the design for power. When
this option is Off, the Compiler does not perform any power optimizations. Normal
compilation performs power optimizations provided that they are not expected to
reduce design performance. Extra effort performs additional power optimizations which
may reduce design performance.

Option Description
Remove Duplicate Registers Removes a register if it is identical to another register. If two registers generate the
same logic, the Compiler deletes the duplicate. The first instance fans-out to the
duplicates destinations. Also, if the deleted register contains different logic option
assignments, the Compiler ignores the options. This option is useful if you want to
prevent the Compiler from removing intentionally duplicate registers. The Compiler
ignores this option if you apply it to anything other than an individual register or a
design entity containing registers.
Remove Redundant Logic Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on
Cells optimizes a circuit for area and speed. The Compiler ignores this option if you apply it to
anything other than a design entity.
Report Connectivity Checks Specifies whether the Synthesis report includes reports under the Connectivity Checks
folder.
Report Parameter Settings Specifies whether the Synthesis report includes the reports in the Parameter Settings
by Entity Instance folder.
Report Source Assignments Specifies whether the Synthesis report includes reports in the Source Assignments
folder.

Option Description
Resource Aware Inference Specifies whether RAM, ROM, and shift-register inference should take the design and
for Block RAM device resources into account.
Restructure Multiplexers Reduces the number of logic elements synthesis requires to implement multiplexers in a
design. This option is useful if your design contains buses of fragmented multiplexers.
This option repacks multiplexers more efficiently for area, allowing the design to
implement multiplexers with a reduced number of logic elements:
• On—minimizes your design area, but may negatively affect design clock speed
(fMAX).
• Off—disables multiplexer restructuring; it does not decrease logic element usage and
does not affect design clock speed (fMAX).
• Auto—allows the Intel Quartus Prime software to determine whether multiplexer
restructuring should be enabled. The Auto setting decreases logic element usage,
but may negatively affect design clock speed (fMAX).
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Option Description
SDC Constraint Protection Verifies.sdc constraints in register merging. This option helps to maintain the validity
of .sdc constraints through compilation.
Safe State Machine Directs the Compiler to implement state machines that can recover from an illegal state.
Shift Register Replacement Allows the Compiler to find a group of shift registers of the same length that can be
– Allow Asynchronous Clear replaced with the altshift_taps IP core. The shift registers must all use the same aclr
Signal signals, must not have any other secondary signals, and must have equally spaced taps
that are at least three registers apart. To use this option, you must turn on the Auto
Shift Register Replacement logic option.

Option Description
State Machine Processing Specifies the processing style the Compiler uses to process a state machine. You can use
your own User-Encoded style, or select One-Hot, Minimal Bits, Gray, Johnson,
Sequential, or Auto (Compiler-selected) encoding.
Strict RAM Replacement When this option is On, the Compiler replace RAM only if the hardware matches the
design exactly.
Synchronization Register Specifies the maximum number of registers in a row that the Compiler considers as a
Chain Length synchronization chain. Synchronization chains are sequences of registers with the same
clock and no fan-out in between, such that the first register is fed by a pin, or by logic in
another clock domain. The Compiler considers these registers for metastability analysis.
The Compiler prevents optimizations of these registers, such as retiming. When gate-
level retiming is enabled, the Compiler does not remove these registers. The default
length is set to two.
Synthesis Effort Controls the synthesis trade-off between compilation speed, performance, and area. The
default is Auto. You can select Fast for faster compilation speed at the cost of
performance and area.
Synthesis Migration Check Enables synthesis checks on Intel Arria 10 to Intel Stratix 10 design migration.
for Stratix 10
Timing-Driven Synthesis Allows synthesis to use timing information to better optimize the design. The Timing-
Driven Synthesis logic option impacts the following Optimization Technique options:
• Optimization Technique Speed—optimizes timing-critical portions of your design
for performance at the cost of increasing area (logic and register utilization)
• Optimization Technique Balanced—also optimizes the timing-critical portions of
your design for performance, but the option allows only limited area increase
• Optimization Technique Area—optimizes your design only for area
1.10. Fitter Settings Reference

Use Fitter settings to customize the place and route of your design. Click
Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) to
access Fitter settings.
Table 29. Advanced Fitter Settings (1 of 8)

Option Description
ALM Register Packing Effort Guides aggressiveness of the Fitter in packing ALMs during register placement. Use this
option to increase secondary register locations. Increasing ALM packing density may
lower the number of ALMs needed to fit the design, but it may also reduce routing
flexibility and timing performance.
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Option Description
• Low—the Fitter avoids ALM packing configurations that combine LUTs and registers
which have no direct connectivity. Avoiding these configurations may improve timing
performance but increases the number of ALMs to implement the design.
• Medium—the Fitter allows some configurations that combine unconnected LUTs and
registers to be implemented in ALM locations. The Fitter makes more use of
secondary register locations within the ALM.
• High—the Fitter enables all legal and desired ALM packing configurations. In dense
designs, the Fitter automatically increases the ALM register packing effort as required
to enable the design to fit.
Allow Register Duplication Allows the Compiler to duplicate registers to improve design performance. When you
enable this option, the Compiler copies registers and moves some fan-out to this new
node. This optimization improves routability and can reduce the total routing wire in nets
with many fan-outs. If you disable this option, this disables optimizations that retime
registers.
Allow Register Merging Allows the Compiler to remove registers that are identical to other registers in the
design. When you enable this option, in cases where two registers generate the same
logic, the Compiler deletes one register, and the remaining registers fan-out to the
deleted register's destinations. This option is useful if you want to prevent the Compiler
from removing intentional use of duplicate registers.
If you disable register merging, the Compiler disables optimizations that retime registers.
Allow Delay Chains Allows the Fitter to choose the optimal delay chain to meet tSU and tCO timing
requirements for all I/O elements. Enabling this option may reduce the number of tSU
violations, while introducing a minimal number of tH violations. Enabling this option does
not override delay chain settings on individual nodes.
Auto Delay Chains for High Allows the Fitter to choose how to optimize the delay chains for high fan-out input pins.
Fanout Input Pins You must enable Auto Delay Chains to enable this option. Enabling this option may
reduce the number of tSU violations, but the compile time increases significantly, as the
Fitter tries to optimize the settings for all fan-outs.
Auto Fit Effort Desired Slack Specifies the default worst-case slack margin the Fitter maintains for. If the design is
Margin likely to have at least this much slack on every path, the Fitter reduces optimization
effort to reduce compilation time.

Option Description
Auto Global Clock Allows the Compiler to choose the global clock signal. The Compiler chooses the signal
that feeds the most clock inputs to flip-flops. This signal is available throughout the
device on the global routing paths. To prevent the Compiler from automatically selecting
a particular signal as global clock, set the Global Signal option to Off on that signal.
Auto Global Register Allows the Compiler to choose global register control signals. The Compiler chooses
Control Signals signals that feed the most control signal inputs to flip-flops (excluding clock signals) as
the global signals. These global signals are available throughout the device on the global
routing paths. Depending on the target device family, these control signals can include
asynchronous clear and load, synchronous clear and load, clock enable, and preset
signals. If you want to prevent the Compiler from automatically selecting a particular
signal as a global register control signal, set the Global Signal option to Off on that
signal.
Auto Packed Registers Allows the Compiler to combine a register and a combinational function, or to implement
registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option
controls how aggressively the Fitter combines registers with other function blocks to
reduce the area of the design. Generally, the Auto or Sparse Auto settings are
appropriate.
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Option Description
The other settings limit the flexibility of the Fitter to combine registers with other
function blocks and can result in no fits.
• Auto—the Fitter attempts to achieve the best performance with good area. If
necessary, the Fitter combines additional logic to reduce the area of the design to
within the current device.
• Sparse Auto—the Fitter attempts to achieve the highest performance, but may
increase device usage without exceeding the device logic capacity.
• Off—the Fitter does not combine registers with other functions. The Off setting
severely increases the area of the design and may cause a no fit.
• Sparse—the Fitter combines functions in a way which improves performance for
many designs.
• Normal—the Fitter combines functions that are expected to maximize design
performance and reduce area.
• Minimize Area—the Fitter aggressively combines unrelated functions to reduce the
area required for placing the design, at the expense of performance.
• Minimize Area with Chains—the Fitter even more aggressively combines functions
that are part of register cascade chains or can be converted to register cascade
chains.
If this option is set to any value but Off, registers combine with I/O cells to improve I/O
timing. This remains true provided that the Optimize IOC Register Placement For
Timing option is enabled.
Auto RAM to MLAB Specifies whether the Fitter converts RAMs of Auto block type to use LAB locations. If
Conversion this option is set to Off, only MLAB cells or RAM cells with a block type setting of MLAB
use LAB locations to implement memory.
Auto Register Duplication Allows the Fitter to automatically duplicate registers within a LAB that contains empty
logic cells. This option does not alter the functionality of the design. The Compiler
ignores the Auto Register Duplication option if you select OFF as the setting for the
Logic Cell Insertion -- Logic Duplication logic option. Turning on this option allows
the Logic Cell Insertion -- Logic Duplication logic option to improve a design's
routability, but can make formal verification of a design more difficult.

Option Description
Enable Bus-Hold Circuitry Enables bus-hold circuitry during device operation. When this option is On, a pin retains
its last logic level when it is not driven, and does not go to a high impedance logic level.
Do not use this option at the same time as the Weak Pull-Up Resistor option. The
Compiler ignores this option if you apply it to anything other than a pin.
Enable Critical Chain For Intel Stratix 10 designs, enables location to the Critical Chain Viewer from the Fast
Viewer Forward Timing Closure Recommendations report. Use the Critical Chain Viewer to
visualize the critical chains limiting further performance improvement.
Equivalent RAM and MLAB Specifies whether RAMs implemented in MLAB cells must have equivalent paused read
Paused Read Capabilities capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep
around the last read value when reading is disabled. Allowing differences in paused read
capabilities provides the Fitter more flexibility in implementing RAMs using MLAB cells.
To allow the Fitter the most flexibility in deciding which RAMs are implemented using
MLAB cells, set this option to Don't Care. The following options are available:
• Don't Care—the Fitter can convert RAMs to MLAB cells, even if they do not have
equivalent paused read capabilities to a block RAM implementation. The Fitter
generates an information message about RAMs with different paused read capabilities.
• Care—the Fitter does not convert RAMs to MLAB cells unless they have the equivalent
paused read capabilities to a block RAM implementation.
Equivalent RAM and MLAB Specifies whether RAMs implemented in MLAB cells must have equivalent power-up
Power Up conditions as RAMs implemented in block RAM. Power-up conditions occur when the
device powers-up or globally resets. Allowing non-equivalent power-up conditions
provides the Fitter more flexibility in implementing RAMs using MLAB cells.
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Option Description
To allow the Fitter the most flexibility in deciding which RAMs are implemented using
MLAB cells, set this option to Auto or Don't Care. The following options are available:
• Auto—the Fitter may convert RAMs to MLAB cells, even if the MLAB cells lack
equivalent power-up conditions to a block RAM implementation. The Fitter also
outputs a warning message about RAMs with non-equivalent power up conditions.
• Don't Care—the same behavior as Auto applies, but the message is an information
message.
• Care—the Fitter does not convert RAMs to MLAB cells unless they have equivalent
power up conditions to a block RAM implementation.
Final Placement Specifies whether the Fitter performs final placement optimizations. Performing final
Optimizations placement optimizations may improve timing and routability, but may also require longer
compilation time.
Fitter Aggressive Specifies whether the Fitter aggressively optimizes for routability. Performing aggressive
Routability Optimizations routability optimizations may decrease design speed, but may also reduce routing wire
usage and routing time. The Automatically setting allows the Fitter to decide whether
aggressive routability is beneficial.

Option Description
Fitter Effort Specifies the level of physical synthesis optimization during fitting:
• Auto—adjusts the Fitter optimization effort to minimize compilation time, while still
achieving the design timing requirements. Use the Auto Fit Effort Desired Slack
Margin option to apply sufficient optimization effort to achieve additional timing
margin.
• Standard—uses maximum effort regardless of the design's requirements, leading to
higher compilation time and more margin on easier designs. For difficult designs, Auto
and Standard both use maximum effort.
Fitter Initial Placement Specifies the seed for the current design. The value can be any non-negative integer
Seed value. By default, the Fitter uses a seed of 1.
The Fitter uses the seed as the initial placement configuration when optimizing design
placement to meet timing requirements fMAX. Because each different seed value results in
a somewhat different fit, you can try several different seeds to attempt to obtain superior
fitting results.
The seeds that lead to the best fits for a design may change if the design changes. Also,
changing the seed may or may not result in a better fit. Therefore, specify a seed only if
the Fitter is not meeting timing requirements by a small amount.
Note: You can also use the Design Space Explorer II (DSEII) to sweep complex flow
parameters, including the seed, in the Intel Quartus Prime software to optimize
design performance.
Logic Cell Insertion Allows the Fitter to automatically insert buffer logic cells between two nodes without
altering the functionality of the design. The Compiler creates buffer logic cells from unused
logic cells in the device. This option also allows the Fitter to duplicate a logic cell within a
LAB when there are unused logic cells available in a LAB. Using this option can increase
compilation time. The default setting of Auto allows these operations to run when the
design requires them to fit the design.
MLAB Add Timing Specifies whether the Timing Analyzer evaluates timing constraints between the write and
Constraints for Mixed-Port the read operations of the MLAB memory block. Performing a write and read operation
Feed-Through Mode simultaneously at the same address might result in metastability issues because no timing
Setting Don't Care constraints between those operations exist by default. Turning on this option introduces
timing constraints between the write and read operations on the MLAB memory block and
thereby avoids metastability issues. However, turning on this option degrades the
performance of the MLAB memory blocks. If your design does not perform write and read
operations simultaneously at the same address, you do not need to set this option.

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Option Description
Optimize Design for This setting improves the reliability of the design by increasing its Mean Time Between
Metastability Failures (MTBF). When you enable this setting, the Fitter increases the output setup slacks
of synchronizer registers in the design. This slack can exponentially increase the design
MTBF. This option only applies when using the Timing Analyzer for timing-driven
compilation. Use the Timing Analyzer report_metastability command to review the
synchronizers detected in your design and to produce MTBF estimates.
Optimize Hold Timing Directs the Fitter to optimize hold time within a device to meet timing requirements and
assignments. The following settings are available:
• I/O Paths and Minimum TPD Paths—directs the Fitter to meet the following timing
requirements and assignments:
— tH from I/O pins to registers.
— Minimum tCO from registers to I/O pins.
— Minimum tPD from I/O pins or registers to I/O pins or registers.
• All Paths—directs the Fitter to meet the following timing requirements and
assignments:
— tH from I/O pins to registers.
— Minimum tCO from registers to I/O pins.
— Minimum tPD from I/O pins or registers to I/O pins or registers.
When you disable the Optimize Timing logic option, the Optimize Hold Timing option is
not available.
Optimize IOC Register Specifies whether the Fitter optimizes I/O pin timing by automatically packing registers into
Placement for Timing I/Os to minimize delays.
• Normal—the Fitter opportunistically packs registers into I/Os that should improve I/O
timing.
• Pack All I/O Registers— the Fitter aggressively packs any registers connected to
input, output, or output enable pins into I/Os, unless prevented by your constraints or
other legality restrictions.
• Off—performs no periphery to core optimization.
Optimize Multi-Corner Directs the Fitter to consider all timing corners during optimization to meet timing
Timing requirements. These timing delay corners include both fast-corner timing and slow-corner
timing. By default, this option is On, and the Fitter optimizes designs considering multi-
corner delays in addition to slow-corner delays. When this option is Off, the Fitter
optimizes designs considering only slow-corner delays from the slow-corner timing model
(slowest manufactured device for a given speed grade, operating in low-voltage
conditions). Turning this option On typically creates a more robust design implementation
across process, temperature, and voltage variations.
When you turn Off the Optimize Timing option, the Optimize Multi-Corner Timing
option is not available.
Optimize Timing Specifies whether the Fitter optimizes to meet the maximum delay timing requirements
(for example, clock cycle time). By default, this option is set to Normal compilation.
Turning this option Off helps fit designs that with extremely high interconnect
requirements. Turning this option Off can also reduce compilation time at the expense of
timing performance (because the Fitter ignores the design's timing requirements). If this
option is Off, other Fitter timing optimization options have no effect (such as Optimize
Hold Timing).

Option Description
Optimize Timing for ECOs Controls whether the Fitter optimizes to meet your maximum delay timing requirements
(for example, clock cycle time, tSU, tCO) during ECO compiles. By default, this option is set
to Off. Turning it On can improve timing performance at the cost of compilation time.
Perform Clocking Directs the Fitter to perform an analysis of the design's clocking topology and adjust the
Topology Analysis During optimization approach on paths with significant clock skew. Enabling this option may
Routing improve hold timing at the cost of increased compile time.
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Option Description
Periphery to Core Specifies whether the Fitter should perform targeted placement and routing optimization on
Placement and Routing direct connections between periphery logic and registers in the FPGA core. The following
Optimization options are available:
• Auto—the Fitter automatically identifies transfers with tight timing windows, places the
core registers, and routes all connections to or from the periphery. The Fitter performs
these placement and routing decisions before the rest of core placement and routing.
This sequence ensures that these timing-critical connections meet timing, and also
avoids routing congestion.
• On— the Fitter optimizes all transfers between the periphery and core registers,
regardless of timing requirements. Do not set this option to On globally. Instead, use
the Assignment Editor to assign optimization to a targeted set of nodes or entities.
• Off—the Fitter performs no periphery to core optimization.
Physical Synthesis Increases circuit performance by performing combinational and sequential optimization
during fitting.
Placement Effort Specifies the relative time the Fitter spends in placement. The default value is 1.0, and legal
Multiplier values must be greater than 0. Specifying a floating-point number allows you to control the
placement effort. A higher value increases CPU time but may improve placement quality.
For example, a value of '4' increases fitting time by approximately 2 to 4 times but may
increase quality.
Power Optimization Directs the Fitter to perform optimizations targeted at reducing the total power devices
During Fitting consume. The available settings for power-optimized fitting are:
• Off—performs no power optimizations.
• Normal compilation—performs power optimizations that are unlikely to adversely
affect compilation time or design performance.
• Extra effort—performs additional power optimizations that might affect design
performance or result in longer compilation time.

Option Description
Programmable Power Sets the upper limit on the fraction of the high-speed LAB tiles. Legal values must be
Maximum High-Speed between 0.0 and 1.0. The default value is 1.0. A value of 1.0 means that there is no
Fraction of Used LAB restriction on the number of high-speed tiles, and the Fitter uses the minimum number
Tiles needed to meet the timing requirements of your design. Specifying a value lower than 1.0
might degrade timing quality, because some timing critical resources might be forced into
low-power mode.
Programmable Power Controls how the Fitter configures tiles to operate in high-speed mode or low-power mode.
Technology Optimization The following options are available:
• Automatic—specifies that the Fitter minimizes power without sacrificing timing
performance.
• Minimize Power Only—specifies that the Fitter sets the maximum number of tiles to
operate in low-power mode.
• Force All Used Tiles to High Speed—specifies that the Fitter sets all used tiles to
operate in high-speed mode.
• Force All Tiles with Failing Timing Paths to High Speed—sets all failing paths to
high-speed mode. For designs that meet timing, the behavior of this setting is similar to
the Automatic setting.
For designs that fail timing, all paths with negative slack are put in high-speed mode. This
mode likely does not increase the speed of the design, and it may increase static power
consumption. This mode may assist in determining which logic paths need to be re-designed
to close timing.
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Option Description
Regenerate Full Fit Controls whether the Fitter report is regenerated during ECO compilation. By default, this
Reports During ECO option is set to Off. Turning it On regenerates the report at the cost of compilation time.
Compiles
Router Timing Controls how aggressively the router tries to meet timing requirements. Setting this option
Optimization Level to Maximum can increase design speed slightly, at the cost of increased compile time.
Setting this option to Minimum can reduce compile time, at the cost of slightly reduced
design speed. The default value is Normal.
Run Early Place during Enables the Early Place Fitter stage during full compilation. Turning on this setting may
compilation increase Fitter processing time.

Option Description
Synchronizer Specifies how the Compiler identifies synchronization register chain registers for metastability
Identification analysis. A synchronization register chain is a sequence of registers with the same clock with
no fan-out in between, which is driven by a pin or logic from another clock domain.
The following options are available:
• Off—the Timing Analyzer does not identify the specified registers, or the registers within
the specified entity, as synchronization registers.
• Auto—the Timing Analyzer identifies valid synchronization registers that are part of a
chain with more than one register that contains no combinational logic. Use the Auto
setting to generate a report of possible synchronization chains in your design.
• Forced if Asynchronous—the Timing Analyzer identifies synchronization register chains
if the software detects an asynchronous signal transfer, even if there is combinational logic
or only one register in the chain.
• Forced—the Timing Analyzer identifies the specified register, or all registers within the
specified entity, as synchronizers. Only apply the Forced option to the entire design.
Otherwise, all registers in the design identify as synchronizers.
The Fitter optimizes the registers that it identifies as synchronizers for improved Mean Time
Between Failure (MTBF), provided that you enable Optimize Design for Metastability.
If a synchronization register chain is identified with the Forced or Forced if Asynchronous
option, then the Timing Analyzer reports the metastability MTBF for the chain when it meets
the design timing requirements.
Treat Bidirectional Pin Specifies that the Fitter treats the bidirectional pin as an output pin, meaning that the input
as Output Pin path feeds back from the output path.
Weak Pull-Up Resistor Enables the weak pull-up resistor when the device is operating in user mode. This option pulls
a high-impedance bus signal to VCC. Do not enable this option simultaneously with the
Enable Bus-Hold Circuitry option. The Fitter ignores this option if you apply to anything
other than a pin.
1.11. Design Compilation Revision History

This document has the following revision history.
Document Version Intel Quartus Changes

Prime Version
2018.08.15 18.0.0 Corrected broken link.
2018.05.07 18.0.0 • Updated Optimization Modes topic to add Compile Time (Aggressive).
• Relocated concurrent analysis content from the Early Place Flow topic
to a new Concurrent Analysis During Synthesis or Fitting topic.
• Rapid Recompile now supports Intel Stratix 10 devices.
• Enhanced description of Retime Stage Reports.
• Enhanced description of Retime Stage to include classic register
retiming.

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Table 37. Document Revision History

Date Version Changes
2017.11.06 17.1.0 • Added support for Intel Stratix 10 Hyper-Aware design flow, Hyper-
Retiming, Fast Forward compilation, and Fast Forward Viewer.
• Added Advanced HyperFlex Settings topic.
• Added Retiming Restrictions and Workarounds topic.
• Added statement about Fast Forward compilation support for
retiming across RAM and DSP blocks.
• Added Concurrent Analysis topic.
• Added Analyzing Fitter Snapshots topic.
• Added Compilation Dashboard Early Place stage control image.
• Added Running late_place After Early Place topic.
• Updated for latest Intel naming conventions.
2017.05.08 17.0.0 • Added reference to initial compilation support for Cyclone 10 GX

devices.
• Described concurrent analysis following Early Place.
• Updated Compilation Dashboard images for Timing Analyzer,
Report, Setting, and Concurrent Analysis controls.
• Updated description for Auto DSP Block Replacement in Advanced
Synthesis Settings.
• Updated Advanced Fitter Settings for Allow Register Retiming, and
for removal of obsolete SSN Optimization option.
• Added Prevent Register Retiming topic.
• Added Preserve Registers During Synthesis topic.
• Removed limitation for Safe State Machine logic option.
• Added references to Partial Reconfiguration and Block-Based Design
Flows.
2016.10.31 16.1.0 • Implemented Intel re-branding.

• Described Compiler snapshots and added Analyzing Snapshot
Timing topic.
• Updated project directory structure diagram.
• Described new Fitter stage menu commands and reports.
• Added description of Early Place Flow, Implement Flow, and Finalize
Flow.
• Added description of Incremental Optimization in the Fitter.
• Reorganized order of topics in chapter.
• Removed deprecated Per-Stage Compilation (Beta) Compilation
Flow.
2016.05.03 16.0.0 • Added description of Fitter Plan, Place and Route stages, reporting,
and optimization.
• Added Per-Stage Compilation (Beta) Compilation Flow
• Added Compilation Dashboard information.
• Removed support for Safe State Machine logic option. Encode safe
states in RTL.
• Added Generating Dynamic Synthesis Reports topic.
• Updated Quartus project directory structure.
2015.11.02 15.1.0 • First version of document.
Related Information
Documentation Archive
For previous versions of the Intel Quartus Prime Handbook, search the
documentation archives.

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2. Reducing Compilation Time

You can employ various techniques to reduce to time required for synthesis and fitting
in the Intel Quartus Prime Compiler.
2.1. Compilation Time Advisor

A Compilation Time Advisor is available in the Intel Quartus Prime GUI by clicking
Tools ➤ Advisors ➤ Compilation Time Advisor. This chapter describes all the
compilation time optimizing techniques available in the Compilation Time Advisor.
2.2. Strategies to Reduce the Overall Compilation Time

You can use the following strategies to reduce the overall time required to compile
your design:
• Parallel compilation (for systems with multiple processor cores)
• Rapid Recompile and Smart Compilation reuse results from a previous compilation
to reduce overall compilation time
2.2.1. Running Rapid Recompile

During Rapid Recompile the Compiler reuses previous synthesis and fitting results
whenever possible, and does not reprocess unchanged design blocks. Use Rapid
Recompile to reduce timing variations and the total recompilation time after making
small design changes.
Figure 47. Rapid Recompile

E
A Changed
J
B G
y
C x z
D
Unchanged
Regular Compile
Rapid
Recompile
UG-20132 | 2018.08.15
To run Rapid Recompile, follow these steps:

1. To start Rapid Recompile following an initial compilation (or after running the
Route stage of the Fitter), click Processing ➤ Start ➤ Start Rapid Recompile.
Rapid Recompile implements the following types of design changes without full
recompilation:
• Changes to nodes tapped by the Signal Tap Logic Analyzer
• Changes to combinational logic functions
• Changes to state machine logic (for example, new states, state transition
changes)
• Changes to signal or bus latency or addition of pipeline registers
• Changes to coefficients of an adder or multiplier
• Changes register packing behavior of DSP, RAM, or I/O
• Removal of unnecessary logic
• Changes to synthesis directives
2. Click the Rapid Recompile Preservation Summary report to view detailed
information about the percentage of preserved compilation results.
Figure 48. Rapid Recompile Preservation Summary
2.2.2. Enabling Multi-Processor Compilation

The Compiler can detect and use multiple processors to reduce total compilation time.
You specify the number of processors the Compiler uses. The Intel Quartus Prime
software can use up to 16 processors to run algorithms in parallel. The Compiler uses
parallel compilation by default. To reserve some processors for other tasks, specify a
maximum number of processors that the software uses.
This technique reduces the compilation time by up to 10% on systems with two
processing cores, and by up to 20% on systems with four cores. When running timing
analysis independently, two processors reduce the timing analysis time by an average
of 10%. This reduction reaches an average of 15% when using four processors.
The Intel Quartus Prime software does not necessarily use all the processors that you
specify during a given compilation. Additionally, the software never uses more than
the specified number of processors. This fact enables you to work on other tasks
without slowing down your computer. The use of multiple processors does not affect
the quality of the fit. For a given Fitter seed, and given Maximum processors
allowed setting on a specific design, the fit is exactly the same and deterministic.
This remains true, regardless of the target machine, and the number of available
processors. Different Maximum processors allowed specifications produce different
results of the same quality. The impact is similar to changing the Fitter seed setting.

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To enable multiprocessor compilation, follow these steps:

1. Open or create an Intel Quartus Prime project.
2. To enable multiprocessor compilation, click Assignments ➤ Settings ➤
Compilation Process Settings.
3. Under Parallel compilation, specify options for the number of processors the
Compiler uses.
4. View detailed information about processor in the Parallel Compilation report
following compilation.
To specify the number of processors for compilation at the command line, use the
following Tcl command in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS <value>
In this case, <value> is an integer from 1 to 16.

If you want the Intel Quartus Prime software to detect the number of processors
and use all the processors for the compilation, include the following Tcl command
in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
Note: The Compiler detects Intel Hyper-Threading as a single processor. If your

system includes a single processor with Intel Hyper-Threading, set the
number of processors to one. Do not use the Intel Hyper-Threading feature
for Intel Quartus Prime compilations.
2.2.3. Using Block-Based Compilation

During the design process, you can isolate functional blocks that meet placement and
timing requirements from others still undergoing change and optimization. By isolating
functional blocks into partitions, you can apply optimization techniques to selected
areas only compile those areas.
To create partitions dividing functional blocks:

1. In the Design Partition Planner, identify blocks of a size suitable for partitioning.
In general, a partition represents roughly 15 to 20 percent of the total design size.
Use the information area below the bar at the top of each entity.
Figure 49. Entity representation in the Design Partition Planner
Percent of total design size
2. Extract and collapse entities as necessary to achieve stand-alone blocks

3. For each entity of the desired size containing related blocks of logic, right-click the
entity and click Create Design Partition to place that entity in its own partition.
The goal is to achieve partitions containing related blocks of logic.

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Related Information
Block-Based Design User Guide
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization

Time
You can reduce synthesis time without affecting the Fitter time by reducing your use
of netlist optimizations. For tips on reducing synthesis time when using third-party
EDA synthesis tools, refer to your synthesis software’s documentation.
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist

Optimization Time
Synthesis netlist and physical synthesis optimization settings can significantly increase
the overall compilation time for large designs. Refer to Analysis and Synthesis
messages to determine the length of optimization time.
If your design already meets performance requirements without synthesis netlist or

physical synthesis optimizations, turn off these options to reduce compilation time. If
you require synthesis netlist optimizations to meet performance, optimize partitions of
your design hierarchy separately to reduce the overall time spent in Analysis and
Synthesis.
2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time

Your HDL coding style can also affect the synthesis time. For example, if you want to
infer RAM blocks from your code, you must follow the guidelines for inferring RAMs. If
RAM blocks are not inferred properly, the software implements those blocks as
registers.
If you are trying to infer a large memory block, the software consumes more
resources in the FPGA. This can cause routing congestion and increasing compilation
time significantly. If you see high routing utilizations in certain blocks, it is a good idea
to review the code for such blocks.
Related Information
Recommended HDL Coding Styles
2.4. Reducing Placement Time

The time required to place a design depends on two factors: the number of ways the
logic in your design can be placed in the device, and the settings that control the
amount of effort required to find a good placement.
You can reduce the placement time by changing the settings for the placement
algorithm.
Sometimes there is a trade-off between placement time and routing time. Routing
time can increase if the placer does not run long enough to find a good placement.
When you reduce placement time, ensure that it does not increase routing time and
negate the overall time reduction.

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2.4.1. Placement Effort Multiplier Settings

You can control the amount of time the Fitter spends in placement by reducing with
the Placement Effort Multiplier option.
Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings

(Fitter) and specify a value for Placement Effort Multiplier. The default is 1.0. Legal
values must be greater than 0 and can be non-integer values. Numbers between 0
and 1 can reduce fitting time, but also can reduce placement quality and design
performance.
2.5. Reducing Routing Time

The routing time is usually not a significant amount of the compilation time. The time
required to route a design depends on three factors: the device architecture, the
placement of your design in the device, and the connectivity between different parts of
your design.
If your design requires a long time to route, perform one or more of the following
actions:
• Check for routing congestion.
• Turn off Fitter Aggressive Routability Optimization.
2.5.1. Identifying Routing Congestion with the Chip Planner

To identify areas of routing congestion in your design:
1. Click Tools ➤ Chip Planner.

2. To view the routing congestion in the Chip Planner, double-click the Report
Routing Utilization command in the Tasks list.
3. Click Preview in the Report Routing Utilization dialog box to preview the
default congestion display.
4. Change the Routing utilization type to display congestion for specific resources.
The default display uses dark blue for 0% congestion and red for 100%.
5. Adjust the slider for Threshold percentage to change the congestion threshold
level.
The Intel Quartus Prime compilation messages contain information about average and
peak interconnect usage. Peak interconnect usage over 75%, or average interconnect
usage over 60% indicate possible difficulties fitting your design. Similarly, peak
interconnect usage over 90%, or average interconnect usage over 75%, indicate a
high chance of not getting a valid fit.
2.5.1.1. Areas with Routing Congestion

Even if average congestion is not high, the design may have areas where congestion is
high in a specific type of routing. You can use the Chip Planner to identify areas of
high congestion for specific interconnect types.

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• You can change the connections in your design to reduce routing congestion
• If the area with routing congestion is in a Logic Lock (Standard) region or between
Logic Lock (Standard) regions, change or remove the Logic Lock (Standard)
regions and recompile your design.
— If the routing time remains the same, the time is a characteristic of your
design and the placement
— If the routing time decreases, consider changing the size, location, or contents
of Logic Lock (Standard) regions to reduce congestion and decrease routing
time.
Related Information
Analyzing and Optimizing the Design Floorplan
2.5.1.2. Congestion due to HDL Coding style

Sometimes, routing congestion may be a result of the HDL coding style used in your
design. After identifying congested areas using the Chip Planner, review the HDL code
for the blocks placed in those areas to determine whether you can reduce interconnect
usage by code changes.
Related Information
Recommended HDL Coding Styles
2.6. Reducing Static Timing Analysis Time

If you are performing timing-driven synthesis, the Intel Quartus Prime software runs
the Timing Analyzer during Analysis and Synthesis.
The Intel Quartus Prime Fitter also runs the Timing Analyzer during placement and
routing. If there are incorrect constraints in the Synopsys* Design Constraints File
(.sdc), the Intel Quartus Prime software may spend unnecessary time processing
constraints several times.
• If you do not specify false paths and multicycle paths in your design, the Timing
Analyzer may analyze paths that are not relevant to your design.
• If you redefine constraints in the .sdc files, the Timing Analyzer may spend
additional time processing them. To avoid this situation, look for indications that
Synopsis design constraints are being redefined in the compilation messages, and
update the .sdc file.
• Ensure that you provide the correct timing constraints to your design, because the
software cannot assume design intent, such as which paths to consider as false
paths or multicycle paths. When you specify these assignments correctly, the
Timing Analyzer skips analysis for those paths, and the Fitter does not spend
additional time optimizing those paths.
2.7. Setting Process Priority

It might be necessary to reduce the computing resources allocated to the compilation
at the expense of increased compilation time. It can be convenient to reduce the
resource allocation to the compilation with single processor machines if you must run
other tasks at the same time.

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Related Information
Processing Page (Options Dialog Box)
In Intel Quartus Prime Help.
2.8. Reducing Compilation Time Revision History

Document Version Intel Quartus Changes
Prime Version
2017.11.06 17.1.0 • Added topic: Using Block-Based Compilation.
Date Version Changes
2017.05.08 17.0.0 • Clarified impact of multiprocessor compilation on fit quality.

• Removed reference to deprecated Fitter Effort Logic Option.
• Removed section: Preserving Routing with Incremental Compilation.
2016.10.31 16.1.0 • Implemented Intel rebranding.
2016.05.02 16.0.0 • Corrected typo in Using Parallel Compilation with Multiple Processors.
• Removed information about deprecated physical synthesis options.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel Quartus Prime.
2014.12.15 14.1.0 • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical
Synthesis Optimizations to Compiler Settings.
• Added information about Rapid Recompile feature.
2014.08.18 14.0a10.0 Added restriction about smart compilation in Arria 10 devices.
June 2014 14.0.0 Updated format.
May 2013 13.0.0 Removed the “Limit to One Fitting Attempt”, “Using Early Timing Estimation”, “Final
Placement Optimizations”, and “Using Rapid Recompile” sections.
Updated “Placement Effort Multiplier Settings” section.
Updated “Identifying Routing Congestion in the Chip Planner” section.
General editorial changes throughout the chapter.
June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0 • Updated “Using Parallel Compilation with Multiple Processors”.
• Updated “Identifying Routing Congestion in the Chip Planner”.
• General editorial changes throughout the chapter.
December 2010 10.1.0 • Template update.

• Added details about peak and average interconnect usage.
• Added new section “Reducing Static Timing Analysis Time”.
• Minor changes throughout chapter.
July 2010 10.0.0 Initial release.
Related Information
Documentation Archive
For previous versions of the Intel Quartus Prime Handbook, search the
documentation archives.

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A. Intel Quartus Prime Pro Edition User Guides

Refer to the following user guides for comprehensive information on all phases of the
Intel Quartus Prime Pro Edition FPGA design flow.
Related Information
• Getting Started User Guide
Introduces the basic features, files, and design flow of the Intel Quartus Prime
Pro Edition software, including managing Intel Quartus Prime Pro Edition
projects and IP, initial design planning considerations, and project migration
from previous software versions.
• Platform Designer User Guide
Describes creating and optimizing systems using Platform Designer, a system
integration tool that simplifies integrating customized IP cores in your project.
Platform Designer automatically generates interconnect logic to connect
intellectual property (IP) functions and subsystems.
• Design Recommendations User Guide
Describes best design practices for designing FPGAs with the Intel Quartus
Prime Pro Edition software. HDL coding styles and synchronous design
practices can significantly impact design performance. Following recommended
HDL coding styles ensures that Intel Quartus Prime Pro Edition synthesis
optimally implements your design in hardware.
• Compiler User Guide
Describes set up, running, and optimization for all stages of the Intel Quartus
Prime Pro Edition Compiler. The Compiler synthesizes, places, and routes your
design before generating a device programming file.
• Design Optimization User Guide
Describes Intel Quartus Prime Pro Edition settings, tools, and techniques that
you can use to achieve the highest design performance in Intel FPGAs.
Techniques include optimizing the design netlist, addressing critical chains that
limit retiming and timing closure, and optimization of device resource usage.
• Programmer User Guide
Describes operation of the Intel Quartus Prime Pro Edition Programmer, which
allows you to configure Intel FPGA devices, and program CPLD and
configuration devices, via connection with an Intel FPGA download cable.
• Block-Based Design User Guide
Describes block-based design flows, also known as modular or hierarchical
design flows. These advanced flows enable preservation of design blocks (or
logic that comprises a hierarchical design instance) within a project, and reuse
of design blocks in other projects.
A. Intel Quartus Prime Pro Edition User Guides
UG-20132 | 2018.08.15
• Partial Reconfiguration User Guide

Describes Partial Reconfiguration, an advanced design flow that allows you to
reconfigure a portion of the FPGA dynamically, while the remaining FPGA
design continues to function. Define multiple personas for a particular design
region, without impacting operation in other areas.
• Third-party Simulation User Guide
Describes RTL- and gate-level design simulation support for third-party
simulation tools by Aldec*, Cadence*, Mentor Graphics, and Synopsys that
allow you to verify design behavior before device programming. Includes
simulator support, simulation flows, and simulating Intel FPGA IP.
• Third-party Synthesis User Guide
Describes support for optional synthesis of your design in third-party synthesis
tools by Mentor Graphics, and Synopsys. Includes design flow steps, generated
file descriptions, and synthesis guidelines.
• Debug Tools User Guide
Describes a portfolio of Intel Quartus Prime Pro Edition in-system design
debugging tools for real-time verification of your design. These tools provide
visibility by routing (or “tapping”) signals in your design to debugging logic.
These tools include System Console, Signal Tap logic analyzer, Transceiver
Toolkit, In-System Memory Content Editor, and In-System Sources and Probes
Editor.
• Timing Analyzer User Guide
Explains basic static timing analysis principals and use of the Intel Quartus
Prime Pro Edition Timing Analyzer, a powerful ASIC-style timing analysis tool
that validates the timing performance of all logic in your design using an
industry-standard constraint, analysis, and reporting methodology.
• Power Analysis and Optimization User Guide
Describes the Intel Quartus Prime Pro Edition Power Analysis tools that allow
accurate estimation of device power consumption. Estimate the power
consumption of a device to develop power budgets and design power supplies,
voltage regulators, heat sink, and cooling systems.
• Design Constraints User Guide
Describes timing and logic constraints that influence how the Compiler
implements your design, such as pin assignments, device options, logic
options, and timing constraints. Use the Interface Planner to prototype
interface implementations, plan clocks, and quickly define a legal device
floorplan. Use the Pin Planner to visualize, modify, and validate all I/O
assignments in a graphical representation of the target device.
• PCB Design Tools User Guide
Describes support for optional third-party PCB design tools by Mentor Graphics
and Cadence*. Also includes information about signal integrity analysis and
simulations with HSPICE and IBIS Models.
• Scripting User Guide
Describes use of Tcl and command line scripts to control the Intel Quartus
Prime Pro Edition software and to perform a wide range of functions, such as
managing projects, specifying constraints, running compilation or timing
analysis, or generating reports.

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Compiler User Guide

Intel® Quartus® Prime Pro Edition

Updated for Intel® Quartus® Prime Design Suite: 18.0

Subscribe UG-20132 | 2018.08.15

Compiler User Guide Intel® Quartus® Prime Pro Edition

2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time................................68

Compiler User Guide Intel® Quartus® Prime Pro Edition

Figure 1. Intel Arria® 10 Design in Compilation Dashboard

1.1. Compilation Overview

Table 1. Compilation Modules

IP Generation Identifies the status and version IP components in the project.

Compiler User Guide Intel® Quartus® Prime Pro Edition

1.1.1. Compilation Flows

Table 2. Compilation Flows

1.1.2. Design Synthesis

Compiler User Guide Intel® Quartus® Prime Pro Edition

Figure 2. Design Synthesis

Logic Cells I/O DFFs RAM DSP Atom Connections

1.1.3. Design Place and Route

Compiler User Guide Intel® Quartus® Prime Pro Edition

1.1.4. Compilation Hierarchy

Figure 3. Hierarchical Project Structure (Intel Stratix 10 Design)

Compiler User Guide Intel® Quartus® Prime Pro Edition

1.1.5. Reducing Compilation Time

1.1.6. Programming File Generation

Table 3. Assembler Generated Programming Files

1.2. Running Full Compilation

Compiler User Guide Intel® Quartus® Prime Pro Edition

• To specify the target FPGA device or development kit, click Assignments ➤

1.2.1. Concurrent Analysis During Synthesis or Fitting

Compiler User Guide Intel® Quartus® Prime Pro Edition

Figure 4. Concurrent Analysis Options

Timing Analysis Icon

1.3. Running Synthesis

Compiler User Guide Intel® Quartus® Prime Pro Edition

1.3.1. Preserve Registers During Synthesis

Table 4. Synthesis Preserve Options

Preserve Prevents removal of registers during Yes • PRESERVE_REGISTER_SYN_ONLY ON|Off

Preserve Prevents removal of assigned Yes • PRESERVE_REGISTER_FANOUT_FREE_NODE

Preserve Prevents removal and sequential No • PRESERVE_REGISTER ON|Off -to

1.3.2. Enabling Timing-Driven Synthesis

Compiler User Guide Intel® Quartus® Prime Pro Edition

Timing-driven synthesis preserves timing constraints, and does not perform

1.3.3. Enabling Multi-Processor Compilation

To enable multiprocessor compilation, follow these steps:

In this case, <value> is an integer from 1 to 16.

Compiler User Guide Intel® Quartus® Prime Pro Edition

Note: The Compiler detects Intel Hyper-Threading as a single processor. If your

1.3.4. Synthesis Reports

Figure 5. Synthesis Reports

Table 5. Synthesis Reports (Design Dependent)

Compiler User Guide Intel® Quartus® Prime Pro Edition

Generated Report Description

1.4. Running the Fitter

(3) Retime available for Intel Stratix 10 devices only.

Compiler User Guide Intel® Quartus® Prime Pro Edition

1.4.1. Fitter Stage Commands

Table 6. Fitter Stage Commands

1.4.2. Incremental Optimization Flow

Compiler User Guide Intel® Quartus® Prime Pro Edition