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    Cmos - Vlsi - Jan 2023

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    1ms21ec132
    This document provides instructions for a supplementary semester examination in CMOS VLSI Design. It lists 10 questions across 5 units. The questions cover topics like MOSFET device physics, VLSI design flow, logic gates, adders, dynamic and pseudo-NMOS logic, and clock skew effects. Students are instructed to answer one full question from each unit, with questions having between 4 to 12 marks each. Diagrams, derivations, explanations and implementations are required in the answers.

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    Cmos - Vlsi - Jan 2023

    Uploaded by

    1ms21ec132
    41 views2 pages
    This document provides instructions for a supplementary semester examination in CMOS VLSI Design. It lists 10 questions across 5 units. The questions cover topics like MOSFET device physics, VLSI design flow, logic gates, adders, dynamic and pseudo-NMOS logic, and clock skew effects. Students are instructed to answer one full question from each unit, with questions having between 4 to 12 marks each. Diagrams, derivations, explanations and implementations are required in the answers.

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    CMOS_VLSI_JAN 2023

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    This document provides instructions for a supplementary semester examination in CMOS VLSI Design. It lists 10 questions across 5 units. The questions cover topics like MOSFET device physics, VLSI design flow, logic gates, adders, dynamic and pseudo-NMOS logic, and clock skew effects. Students are instructed to answer one full question from each unit, with questions having between 4 to 12 marks each. Diagrams, derivations, explanations and implementations are required in the answers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    41 views2 pages

    Cmos - Vlsi - Jan 2023

    Uploaded by

    1ms21ec132
    This document provides instructions for a supplementary semester examination in CMOS VLSI Design. It lists 10 questions across 5 units. The questions cover topics like MOSFET device physics, VLSI design flow, logic gates, adders, dynamic and pseudo-NMOS logic, and clock skew effects. Students are instructed to answer one full question from each unit, with questions having between 4 to 12 marks each. Diagrams, derivations, explanations and implementations are required in the answers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    EC52/EC52(O)

    USN 1 M S
    (Autonomous Institute, Affiliated to VTU)
    (Approved by AICTE, New Delhi & Govt. of Karnataka)
    Accredited by NBA & NAAC with ‘A+’ Grade

    Created by trial version of DocuFreezer


    SUPPLEMENTARY SEMESTER EXAMINATIONS – JULY 2023
    B.E. – Electronics and Communication
    Program : Semester : V
    Engineering
    Course Name : CMOS VLSI Design Max. Marks : 100
    Course Code : EC52/EC52(O) Duration : 3 Hrs

    Instructions to the Candidates:


     Answer one full question from each unit.

    UNIT - I
    1. a) Draw the cross-section of the CMOS inverter in P-Well process with all CO1 (08)
    fabrication processing steps.
    b) Describe the following with respect to MOS device with equations CO1 (06)
    wherever necessary:-
    i. Body biasing Effects
    ii . Channel length modulation.
    c) Tabulate the gate and diffusion capacitance values for all 3 regions of CO1 (06)
    operation of MOSFET with diagrams.

    2. a) State and discuss: i. Moore’s law ii. Dennard’s law. CO1 (06)
    b) Explain the following fabrication steps with necessary diagrams where CO1 (06)
    ever applicable. i).Photolithography ii) Etching iii) Ion implantation.
    c) Discuss the steps in the VLSI Design flow with a flowchart. Elaborate on CO1 (08)
    physical design in VLSI.

    UNIT - II
    3. a) Draw the CMOS circuit and layout for the function f = (A+BCD)’. CO2 (08)
    b) Discus the following effects in MOS transistor: CO2 (06)
    i) Drain induced barrier lowering
    ii) Velocity Saturation
    iii) Channel length modulation.
    c) Discuss the DC transfer characteristics of an inverter and answer the CO2 (06)
    following:
    Which region in the VTC, maximum power is consumed?

    4. a) Derive the equation for the current flowing through a MOS transistor. CO2 (08)
    b) Derive an expression for the output voltage in each of the following CO2 (12)
    cases. Neglect body effect.

    Page 1 of 2
    EC52/EC52(O)
    UNIT - III
    5. a) Design a 16-bit carry look ahead adder with a PG logic diagram, show CO3 (10)
    the critical path and thereby the delay of the design.
    b) Use Booth encoding to multiply the following positive numbers: CO3 (10)

    Created by trial version of DocuFreezer


    (11111)2 x (11001)2.

    6. a) Design a 16-bit carry-skip adder with a PG logic diagram, show the CO3 (10)
    critical path and thereby the delay of the design.
    b) Draw the structure of a 16-bit Kogge-Stone adder and explain. CO3 (10)

    UNIT- IV
    7. a) A 3-input NAND gate sized similar to a unit inverter is supplying its CO4 (08)
    output to two identically sized 3-input NAND gates. Use the RC delay
    model to compute the delay.
    b) A new process is such that the unit pMOS transistors have three times CO4 (12)
    the resistance of unit nMOS transistors. Show a unit inverter in this
    technology. Calculate the logical effort of 2-input NAND gate and
    3-input NOR gate in this new process technology.

    8. a) CO4 (12)

    Fig.8(a) Fig.8(b)

    Consider two designs of a 6-input AND gate shown in Fig.8(a) & (b).
    Which design is fastest for (a) H = 1? (b) H = 5?
    b) An output pad contains a chain of successively larger inverters to drive CO4 (08)
    the off-chip capacitance. If the first inverter in the chain has an input
    capacitance of 20 fF and the off-chip load is 10 pF, how many inverters
    should be used to drive the load with least delay?

    UNIT - V
    9. a) Explain the dynamic logic circuit with precharging and evaluation. Also CO5 (08)
    implement F = using dynamic logic.
    b) Explain the concept of (i) Time borrowing (ii) Delay constraints. CO5 (08)
    c) Implement any boolean expression of your choice using CVSL. CO5 (04)

    10. a) Design a 3-input pseudo-nMOS NAND gate. Also, calculate its logical CO5 (06)
    effort and parasitic delay effort.
    b) Discuss the impact of clock skew and jitter on the performance of CO5 (06)
    digital circuits.
    c) Sketch HI-skew and LO-skew 3-input NAND and NOR gates. What are CO5 (08)
    the logical efforts of each gate on its critical transition?

    ********************************

    Page 2 of 2

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