LTC4420

18V Dual Input Micropower

PowerPath Prioritizer with
Backup Supply Monitoring
FEATURES DESCRIPTION
n Selects Highest Priority Valid Supply from Two The LTC®4420 is a dual input monolithic PowerPath™
Inputs prioritizer, with low operating current, that provides
n Wide 1.8V to 18V Operating Range backup switchover for keeping critical circuitry alive dur-
n Internal Dual 2Ω, 0.5A Switches ing brownout and power loss conditions. Unlike diode-OR
n Low 3.6µA Operating Current products, little current is drawn from the inactive supply
n Low 320nA V2 Current When V1 Connected to OUT even if its voltage is greater than the active supply.
n Blocks Reverse and Cross Conduction Currents Internal 2Ω, current limited PMOS switches provide
n Reverse Supply Protection to –15V power path selection from a primary input (V1) or a backup
n Built-In V2 Test with Optional V2 Disconnect input (V2) to the output. Two adjustable voltage monitors
n V2 Freshness Seal/Ship Mode set via external resistive dividers provide flexibility in set-
n ±1.5% Accurate Adjustable Switchover Threshold ting V1 to V2 switchover and V2 undervoltage thresholds.
n ±2.3% Accurate V2 Monitor and Comparator V1 is monitored continuously while V2 supply monitoring
n Overcurrent and Thermal Protection includes controllable low duty cycle UV monitoring. When
n Thermally Enhanced 12-Pin 3mm × 3mm primary input V1 drops, the ADJ monitor causes OUT to
DFN and 12-Lead Exposed Pad MSOP Packages be switched to V2. When V2 drops, it is disconnected from
OUT if V2DIS is low. Fast non-overlap switchover circuitry
APPLICATIONS prevents reverse and cross conduction while minimizing
output droop.
n Low Power Battery Backup
n Portable Equipment Auxiliary voltage monitor CMP1 provides flexible voltage
n Point-of-Sale (POS) Equipment monitoring and output V2OK provides V2 undervoltage
status. Freshness seal mode prevents V2 battery discharge
during storage or shipment.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners.

TYPICAL APPLICATION
Typical Switchover Waveforms
5V WALL
V1 OUT OUT
ADAPTER
1M 1M 1M
V2 MONITORING
10µF ADJ CMPOUT1 V1UV INTERVAL
237k V2
CMP1 V2OK V2OK 2V/DIV
121k SWITCHOVER
LTC4420 V1 THRESHOLD
2V/DIV V2 UNDERVOLTAGE
AND DISCONNECT
+ V2 V2DIS
7.4V
Li-Ion 4.02M
V2UV V2TEST OUT
COUT = 10µF
280k ILOAD = 100mA
TYPICAL VALUES:
GNDSW SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
20ms/DIV 4420 TA01b
GND V1UV THRESHOLD: V1 < 4.4V (V1 FALLING)
4420 TA01a
V2OK THRESHOLD: V2 < 6V (V2 FALLING)

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LTC4420
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)

Terminal Voltages Pin Currents (Note 2)

V1, V2.......................................................–15V to 24V ADJ, CMP1, V2UV, CMPOUT1, GNDSW..............–1mA
OUT........................................................ –0.3V to 24V V2TEST, V2DIS, V2OK .......................................–1mA
OUT – V2..................................................–24V to 39V Operating Ambient Temperature Range
OUT – V1..................................................–24V to 39V LTC4420C................................................. 0°C to 70°C
Input Voltages LTC4420I..............................................–40°C to 85°C
ADJ, CMP1, V2UV, V2TEST, V2DIS Junction Temperature (Notes 4, 5)......................... 125°C
(Note 3) ................................................. –0.3V to 24V Storage Temperature Range................... –65°C to 150°C
Output Voltages Lead Temperature (Soldering, 10 sec)
CMPOUT1, GNDSW, V2OK (Note 3) ....... –0.3V to 24V MSOP Package.................................................. 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW
V1 1 12 V2
V1 1 12 V2
V2TEST 2 11 V2DIS V2TEST 2 11 V2DIS
CMP1 3 13 10 V2UV CMP1 3 13 10 V2UV
ADJ 4 GND 9 OUT ADJ 4 GND 9 OUT
GND 5 8 V2OK
GND 5 8 V2OK
CMPOUT1 6 7 GNDSW
CMPOUT1 6 7 GNDSW
MSE PACKAGE
DD PACKAGE
12-LEAD PLASTIC MSOP
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W
TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION http://www.linear.com/product/LTC4420#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4420CDD#PBF LTC4420CDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4420IDD#PBF LTC4420IDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4420CMSE#PBF LTC4420CMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP 0°C to 70°C
LTC4420IMSE#PBF LTC4420IMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage and Currents
V1, V2 Operating Voltage Range l 1.8 18 V
IV1 V1 Current, V1 Powering OUT IOUT = 0, V1 = 8.4V, V2 = 3.6V l 3.6 6.3 µA
V1 Current, V2 Powering OUT V1 = 8.4V, V2 = 3.6V l 500 800 nA
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 LTC4420
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IV2 V2 Current, V2 Powering OUT IOUT = 0, V1 = 3.6V, V2 = 8.4V l 3.3 6 µA
V2 Current, V1 Powering OUT V1 = 3.6V, V2 = 8.4V l 320 650 nA
V2 Current in Freshness Seal Mode V1 = GND, V2 = 5V l 120 220 nA
RON Switch Resistance V1 = V2 = 5V, IOUT = –100mA l 1 2 5 Ω
tVALID(V1) Input Qualification Time V1 Rising, ADJ Rising l 34 64 94 ms
Input Comparators
VTHA ADJ Threshold ADJ Falling l 1.032 1.047 1.062 V
VHYSTA ADJ Comparator Hysteresis ADJ Rising l 30 50 70 mV
VTHC CMP1, V2UV Threshold CMP1, V2UV Falling l 0.378 0.387 0.396 V
VHYSTC CMP1, V2UV Comparator Hysteresis CMP1, V2UV Rising l 7.5 10 12.5 mV
tPDA ADJ Comparator Falling Response Time 10% Overdrive l 4 7.3 12 µs
tPDC CMP1, V2UV Comparator Response Times 20% Overdrive l 30 65 µs
Power Path Function
ILIM Output Current Limit V1, V2 = 8.4V l 0.5 1.1 1.6 A
VREV Reverse Comparator Threshold (V1, V2) – VOUT for Power Path Turn-On l 25 50 75 mV
tSWITCH Break-Before-Make Switchover Time V1 = V2 = 5V, IOUT = –100mA l 1 2.5 5 µs
V2 Monitoring
tMONL Longest Possible V2UV Monitor Duration V2TEST ≥ VIH l 88 128 168 ms
tMONS Shortest Possible V2UV Monitor Duration V2TEST ≥ VIH l 1 2 3 ms
tLTEST Time Between V2UV Monitoring Events V2TEST ≥ VIH l 80 132 180 s
tHV2T Minimum Allowed V2TEST High Time V2TEST Driven Externally l 10 ms
tLV2T Minimum Allowed V2TEST Low Time V2TEST Driven Externally l 10 ms
I/O Specifications
VOL Output Voltage Low, CMPOUT1, GNDSW and V2OK I = 100µA l 15 50 mV
I = 1mA l 120 250 mV
VOH V2OK Output High Voltage I = –1µA, V2 = 5V l 1.05 1.65 2.3 V
IOH V2OK, GNDSW, CMPOUT1 Output High Leakage CMPOUT1, GNDSW, V2OK = 18V l ±50 ±150 nA
VIL V2DIS, V2TEST Input Low Voltage V1 = V2 = 5V l 0.2 V
VIH V2DIS, V2TEST Input High Voltage V1 = V2 = 5V l 0.9 V
IV2X(IN,Z) V2DIS, V2TEST Allowable Leakage in Open State l 0.5 µA
IPU(V2OK) V2OK Pull-Up Current V2 = 5V, ADJ = 0V, V2OK = 0V l –2.7 –5 –8 µA
ILEAK ADJ, CMP1, V2UV Leakage Current ADJ, CMP1, V2UV = 0V, 1.5V l ±1 ±5 nA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings temperature will exceed 125°C when overtemperature protection is active.
may cause permanent damage to the device. Exposure to any Absolute Continuous operation above the specified maximum operating junction
Maximum Rating condition for extended periods may affect device temperature may impair device reliability.
reliability and lifetime. Note 5: The LTC4420 is tested under pulsed load conditions such that
Note 2: All currents into pins are positive; all voltages are referenced to TJ ≈ TA. The junction temperature (TJ in °C) is calculated from the ambient
GND unless otherwise noted. temperature (TA in °C) and power dissipation (PD in Watts) according to
Note 3: These pins can be tied to voltages down to –5V through a resistor the formula:
that limits the current to less than –1mA. TJ = TA + (PD • θJA)
Note 4: The LTC4420 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction

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 LTC4420
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated)
V1 Current, V1 Powers OUT V2 Current, V2 Powers OUT
(IOUT = 0) (IOUT = 0) V2 Current, V1 Powers Out
4.5 4.0 450
V1 = 1.8V V2 = 1.8V V1 = V2
V1 = 3.6V V2 = 3.6V
V1 ≥ 6V V2 ≥ 6V 400
4.0

V2 CURRENT (µA)
3.5 350
V1 CURRENT (µA)

V2 CURRENT (nA)
3.5 300

3.0 250
3.0 –40°C
200 25°C
90°C

2.5 2.5 150

–50 –25 0 25 50 75 100 125 0 5 10 15 20
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C) V2 VOLTAGE (V)
TEMPERATURE (°C) 4420 G02 4420 G03
4420 G01

Normalized CMP1 and

Open-Drain (CMPOUT1, GNDSW, V2UV Falling Thresholds vs
V1 Current, V2 Powers Out V2OK) VOL vs Pull-Down Current Temperature
550 250 1.010
V1 = V2

500 200
1.005
NORMALIZED VTHC
V1 CURRENT (nA)

450 150
VOL (mV)

1.000
400 100

–40°C 0.995
350 25°C 50
90°C

300 0 0.990
0 5 10 15 20 0 0.5 1 1.5 2 –50 –25 0 25 50 75 100 125
V2 VOLTAGE (V) PULL-DOWN CURRENT (mA) TEMPERATURE (°C)
4420 G04 4420 G05 4420 G06

Normalized Falling ADJ

Threshold vs Temperature ADJ Hysteresis vs Temperature ADJ Leakage vs Temperature
1.010 70 3.0
VADJ = 0V, 1.5V

2.5
1.005 60
ADJ HYSTERESIS (mV)
NORMALIZED VTHA

ADJ LEAKAGE (nA)

2.0
1.000 50
1.5

0.995 40
1.0

0.990 30 0.5
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
4420 G07 4420 G08 4420 G09

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 LTC4420
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated)
Output Current IOUT Response for IOUT vs VOUT for Different Input
Output Current Limit vs Temperature Different Shorting Impedances Supply Voltages
1.40 3.0 1.2
1.2Ω FOLDBACK VIN = 1.8V
2.2Ω VIN = 3.6V
1.30 2.5 3.3Ω 1.0 VIN = 5V
3.9Ω CURRENT
5Ω LIMIT
CURRENT LIMIT (A)

1.20 2.0 0.8

IOUT (A)
IOUT (A)
OHMIC
1.10 1.5 0.6

1.00 1.0 0.4

0.90 0.5 0.2

0.80 0 0
–50 –25 0 25 50 75 100 125 40µs/DIV 0 1 2 3 4 5
TEMPERATURE (°C) VOUT (V)
4420 G10 4419 G11 4419 G12

Freshness Seal Current vs

Switch RON vs Temperature V2 Voltage and Temperature
5 250
5V 1.8V V1 = 0V
3.6V 3.6V
2V 5V
200
4 ≥6V
V2 CURRENT (nA)

150
RON (Ω)

100

2
50

1 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100
TEMPERATURE (°C) TEMPERATURE (°C)
4419 G13 4420 G14

Switchover from a Higher to a Output Voltage and Current V1 Reverse Voltage Blocking
Lower Voltage Waveforms During Switchover with V2 Powering Out
COUT = 10µF 6V
V1 IOUT = 200mA V2
10V 5V/DIV
V2
10V
OUT
2V/DIV DISCONNECT FROM V1 6V OUT V1
V1
2V/DIV 10V/DIV
V2 COUT = 10µF –10V
C1= C2 = 10µF
ILOAD = 50mA
CONNECT TO V2 IOUT IOUT
0.5A/DIV 0.5A/DIV
ILOAD = 50mA
4419 G15 4420 G16 4420 G17
3ms/DIV 10µs/DIV 20ms/DIV

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LTC4420
PIN FUNCTIONS
ADJ: Adjustable Switchover Threshold Input. ADJ is the V2: Backup Power Supply. OUT is internally switched to
noninverting input to the switchover threshold comparator. V2 if ADJ < 1.047V or V1 < 1.55V, provided other condi-
If V1 ≥ 1.55V and ADJ ≥ 1.097V for at least 64ms, OUT tions listed in Table 1 in Applications Information are met.
is switched internally to the primary V1 input. When the Bypass with 1µF or greater. Tie to GND if unused.
ADJ input voltage is lower than 1.047V, OUT is switched V2DIS: V2 Power Path Disable Input. When driven low,
internally to V2 if conditions in Table 1 of the Applica- this pin disables the V2 to OUT power path if input V2UV
tions Information section are met. Otherwise, OUT stays
drops below 0.387V. Connect a resistor between V2 or
unpowered. Tie ADJ via a resistive divider to V1, in order
OUT and this pin to provide additional pull-up. Leave open
to set the V1 to V2 switchover voltage. Do not leave open.
if unused. This pin is initialized high during power-up.
CMP1: Auxiliary Comparator 1 Monitor Input . CMP1 is the
V2OK: V2OK Logic Output. V2OK is an output that is driven
noninverting input to an auxiliary comparator. The invert-
high with a 5µA pull-up if V2UV > 0.387V at the end of
ing input is internally connected to a 0.387V reference.
the V2UV monitoring period. Otherwise it is driven low.
Connect CMP1 to GND when it is not used.
Connect a resistor between OUT and this pin to provide
CMPOUT1: Auxiliary Comparator Output 1. This open-drain additional pull-up. As this pin is used to enable freshness
comparator output is pulled low when CMP1 is below seal, do not force low or connect a pull-down resistor to
0.387V and during power-up, otherwise it is released. this pin. Leave open if unused.
Once released, connecting a resistor between CMPOUT1
V2TEST: V2 Undervoltage Test Enable Input. This pin sets
and a desired supply voltage up to 18V causes this pin to
the duty cycle of V2 undervoltage monitoring. When V1
be pulled high. Leave open if unused.
is valid, driving V2TEST low disables V2 monitoring while
GNDSW: Pulsed GND Output. This open-drain output is driving it high enables V2 monitoring with a maximum
pulled low when V2UV is being monitored, otherwise it duty cycle of ~0.1%. When V1 is invalid or not present,
is released high. Connect a resistive divider between V2, V2 is always monitored with V2TEST setting the duty
V2UV and GNDSW to set V2 undervoltage threshold. cycle between 0.0015% and 0.1% depending on its own
Leave open if unused. state and previously determined V2 validity. Refer to the
Exposed Pad: The exposed pad is ground and must be state diagram and waveforms in the Applications Informa-
tion section for details. Leave open or connect a resistor
soldered to the PCB ground plane.
between V2 or OUT and this pin to provide additional
GND: Device Ground. pull-up. Connect to GND if unused. This pin is initialized
OUT: Output Voltage Supply. OUT is a prioritized voltage high on power-up.
output that is either connected to V1, V2 or is unpowered V2UV: V2 Undervoltage Monitor Input. V2UV is the non-
as indicated in Table 1 of the Applications Information sec- inverting input to a comparator whose inverting input is
tion. Additionally, OUT must be at least 50mV below the internally connected to a 0.387V reference. Connect a
input supply for a connection to that supply to be activated. resistive divider between V2, V2UV and GNDSW to set V2
Bypass with a capacitor of 1µF or greater. See Applica- undervoltage threshold. See the Applications Information
tions Information for bypass capacitor recommendations. section for details on V2 monitoring. Connect a pull-up
V1: Primary Power Supply. OUT is internally switched to resistor to V2 if unused. Do not leave open.
V1 if V1 ≥ 1.55V and ADJ ≥ 1.097V. When in freshness
seal, applying V1 ≥ 1.55V and ADJ ≥ 1.097V for 32ms
disables freshness seal. Bypass with 1µF or greater. Tie
to GND if unused.

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 LTC4420
FUNCTIONAL DIAGRAM

CMPOUT1
6
0.397V/ CP1
0.387V
+
CMP1
3 –

V1
1
V2
12

OUT
9
50mV + 50mV +
– –
FRESHNESS

EN1 EN2 + – + –
SEAL

CREV2 CREV1
CUV1
+
–
1.55V/
1.52V CUV2
–
+
2.5V
1.097V/ CADJ
1.047V
– 64ms
ADJ
4 + 7.3µs 5µA
CONTROL LOGIC

V2DIS
11 V2OK
1M 8

0.397V/ CV2UV
0.387V
–
V2UV D Q
10 + E GNDSW
7
EN_GNDSW

V2TEST
2
1M

GND
5

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LTC4420
OPERATION
The Functional Diagram shows the major blocks of the The LTC4420 blocks reverse voltages up to –15V when
LTC4420. The LTC4420 is a PowerPath prioritizer that a reverse condition occurs on an inactive channel. The
switches output OUT between primary (V1) and backup LTC4420 also disables a channel if the corresponding
(V2) sources depending on their validity and priority with input supply falls below 1.52V. A small ~3µA current is
V1 having the highest priority. A resistive divider between drawn from either the prioritized input supply, or the high-
V1, ADJ and GND and comparators CUV1 and CADJ are est supply if both input supplies are below 1.55V. Very
used to monitor V1’s voltage to establish validity. V1 is little current (~320nA) is drawn from the unused supply.
valid if V1 ≥ 1.55V and ADJ ≥ 1.097V for 64ms after V1 Pins V2TEST and V2DIS provide flexibility in monitoring
rises above 1.55V. Otherwise V1 is invalid. A resistive and disconnecting the V2 power path using the V2UV
divider between V2, V2UV and GNDSW and comparators monitor input. V2 is monitored by activating the V2-V2UV-
CUV2 and CV2UV are used to monitor V2’s voltage to GNDSW resistive divider. V2TEST allows for adjustability
establish validity. V2 voltage is monitored periodically in of GNDSW duty cycle to trade off V2 quiescent current with
order to minimize current consumption in the divider. V2 V2 monitoring frequency. When low, V2DIS disables the
is valid if V2 ≥ 1.55V and V2UV ≥ 0.4V at the end of the V2 to OUT power path, if V2 is found to be invalid. Refer
V2 monitoring period. Otherwise it is invalid. If neither to the Applications Information section for details. If V2 is
supply is valid, OUT stays unpowered if V2DIS is low. If valid at the end of a V2 monitoring interval, output V2OK
V2DIS is high and V2 > 1.55V, OUT is connected to V2. is latched high. Otherwise it is latched low. V2OK retains
Refer to Table 1 in the Applications Information section its state until the end of the next V2 monitoring interval
for details. Switchover threshold is independent of relative when it gets updated. V2 monitoring is disabled if V2 <
V1 and V2 voltages, permitting V1 to be lower or higher 1.55V or during thermal shutdown. During initial power-
than V2 when V1 powers OUT and vice versa. up V2 monitoring is disabled and V2OK is initialized low.
Power connection to the output is made by enhancing back-
The LTC4420 provides an additional comparator, CP1,
to-back internal P-channel MOSFETs. Current passed by
whose open-drain output pulls low either when the CMP1
the MOSFETs is limited to typically 1.1A if OUT is greater
pin voltage falls below 0.387V or during initial power up.
than 1V. Otherwise it is limited to 250mA. When switching
This comparator can be used to monitor supplies to provide
from V1 to V2, the V1 to OUT power path is first disabled
early power failure warning and other useful information.
and comparator CREV2 is enabled. After the OUT voltage
drops 50mV below V2, as detected by CREV2, OUT is The LTC4420 can be put into a V2 freshness seal mode
then connected to V2. This break-before-make strategy to prevent battery discharge during storage or shipment.
prevents OUT from backfeeding V2. Switchover back to V1 The Applications Information section lists the steps to
occurs in a similar manner once V1 has been revalidated. engage and disengage V2 freshness seal.

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 LTC4420
APPLICATIONS INFORMATION
The LTC4420 is a low quiescent current 2-channel priori- V1 OUT
OUT

tizer that powers both its internal circuitry and its output + 2-CELL R3 R6 R7 R8 COUT
Li-Ion 1M 1M 1M 1M 10µF
C1
OUT from a prioritized valid input supply. Unlike an ideal 7.4V 4.7µF R2
ADJ V2TEST
CMPOUT1 V1UV
150k
diode-OR, the LTC4420 does not necessarily draw current CMP1 V2OK V2UV

from the highest supply as long as one supply is greater R1

78.7k LTC4420 SWITCHOVER
THRESHOLD: V1 < 5.6V (V1 FALLING)
than 1.8V. Table 1 lists the input supply from which the V2 V2DIS
V1UV: V1 < 6V (V1 FALLING)
V2UV: V2 < 6V (V2 FALLING)
LTC4420 draws its internal quiescent current ICC and the + 2-CELL
Li-SOCl2
R5
4.02M
C2
supply to which OUT is connected after input supplies 7.4V 4.7µF R4
V2UV

have been qualified. 280k

GNDSW
GND
A typical battery backup application is shown in Figure 1.
4420 F01

V1 is powered by a 2-cell Li-Ion battery pack whose safe

discharge limit is between 5.6V and 6V. V2 is powered by Figure 1. The LTC4420 Protecting 2-Cell Lithium Battery Packs
a low self discharge 7.6V Li-Thionyl Chloride (Li-SOCl2) on V1 and V2 from Discharge Below Their Safe Minimum Voltage
hold-up battery which is completely discharged when its
voltage drops to 6V. Li-SOCL2 battery life is maximized Setting Switchover and V2 Undervoltage Thresholds
as very little current is drawn from V2 during normal
operation due to the low duty cycle of V2 monitoring and Several factors affect switchover voltage and should be
the LTC4420’s low V2 standby current. To protect the taken into account when calculating resistor values. These
2-cell Li-Ion battery on V1, switchover threshold is set include resistor tolerance, 1.5% ADJ comparator threshold
to be ~5.6V. After switchover to V2, the Li-Ion battery error, divider impedance and worst-case ADJ pin leakage.
primarily supplies only divider R1-R3’s current as the These factors also apply to resistive dividers connected
LTC4420 draws only a small standby current from V1. to monitor inputs CMP1 and V2UV. Referring to Figure
Monitor CMP1 is configured to provide V1 power failure 1 and the Electrical Characteristics table, the typical V1
warning by driving V1UV low when V1 falls below 6V. switchover threshold:
Monitor input V2UV is configured to set V2’s UV threshold VTHA
to 6V and V2DIS is tied low to disconnect the V2 to OUT VSW1 = • (R1+R2+R3) (1)
R1+R2
power path when V2 falls below 6V. V2TEST is tied high
to monitor V2 once every 132s. Relevant equations used
to calculate these component values are discussed in the
following subsections.
Table 1. OUT and LTC4420 ICC Power
INPUT VOLTAGES
V1 > 1.55V ADJ > 1.097V V2 > 1.55V V2DIS > 0.9V V2UV > 0.397* ICC SOURCE OUT CONNECTION
Y† Y† X X X V1 V1
Y N Y Y X V2 V2
Y N Y N Y V2 V2
Y N Y N N V1 Hi-Z
Y N N X X V1 Hi-Z
N X Y N N V2 Hi-Z
N X Y N Y V2 V2
N X Y Y X V2 V2
N X N X X VMAX** Hi-Z
*Note: Refers to V2UV voltage at the end of the V2 monitoring period.
**Note: VMAX = higher of V1 and V2.
† For 64ms.

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LTC4420
APPLICATIONS INFORMATION
Typical V1 undervoltage threshold is: where IOUT is the current supplied by COUT during non-
VTHC overlap or dead time, tNOV. Choosing:
VV1UV = • (R1+R2+R3) (2)
R1 tNOV •IOUT
COUT ≥ (5)
∆VOUT
Worst-case VOL due to current flow into the GNDSW pin
must be taken into account while calculating values for limits output droop to less than ∆VOUT.
the V2 undervoltage resistive divider:
In order to estimate tNOV and IOUT, first consider a scenario
VTHC  V  where power supplies are present on V1 and V2, and their
VV2UV = •  R4+R5+ OL  (3)
V  100µA  voltages are changing slowly compared to the ADJ com-
R4+ OL parator propagation delay tPDA. For such cases, IOUT is
100µA
ILOAD and tNOV is tSWITCH. COUT can be sized according to
Equations 1-3 assume ADJ and CMP1 pin leakages are equation 5 with IOUT = ILOAD(MAX) and tNOV = tSWITCH(MAX)
negligible. To account for pin leakage, equations 1-3 must to limit maximum output droop when switching to a higher
be modified by an ILEAK • REQ term where equivalent supply. When switching to a lower supply, switchover is
resistance REQ must be calculated on a case-by-case ba- initiated only after OUT falls VREV below the supply that
sis. Worst-case component values and reference voltage is being switched in. In such cases, total output droop is
tolerances must be used to calculate the maximum and ∆VOUT + VREV.
minimum threshold voltages. For example, to calculate Next consider a scenario where the input power source
minimum falling switchover threshold voltage VSW1(MIN), powering OUT is unplugged. OUT backfeeds circuitry
use VTHA(MIN), (R2+R1)(MAX), R3(MIN) in equation 1. connected to the input supply pin. Both input and output
125 droop at the same rate. Referring to Figure 1, assume
the battery on V1 is unplugged when OUT is connected
100 to V1. IOUT is the sum of ILOAD and the back fed current
IBACK, which in this example is IR3. As OUT and V1, since
75 the two are connected, droop below the ADJ threshold,
t PDA (µs)

switchover occurs to V2 with a dead time

50
tNOV = tPDA + tSWITCH (6)
25 where tPDA is an overdrive dependent ADJ comparator
delay. As an approximation, use tPDA from the Electrical
0
10 100 1k 10k 100k Characteristics table to estimate tNOV. Use this tNOV and:
dV ADJ /dt (V/s)
4420 F02 IOUT = (IBACK + ILOAD) (7)
Figure 2. ADJ Comparator Propagation Delay as a
Function of Slew Rate; tPDA vs dVADJ/dt in equation 5 to size COUT:

Selecting Output Capacitor COUT COUT ≥

( tPDA + tSWITCH ) •IOUT
(8)
∆VOUT
COUT can be selected to control either output voltage droop
during switchover or output rising slew rate during initial Refer to Figure 2 for a more accurate estimate of tPDA vs
power-up or when switching to a higher supply. dVOUT/dt. If ADJ is filtered with capacitor CADJ, its discharge
In general, output droop, ΔVOUT, can be calculated by: time via divider R1 – R3 increases tPDA. This results in a
higher output droop than estimated by equation (8).
tNOV •IOUT
VOUT = (4)
COUT
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10 For more information www.linear.com/LTC4420

 LTC4420
APPLICATIONS INFORMATION
In order to limit output rising slew rate dVOUT/dt, size: Second, use a bypass capacitor at the input to limit input
voltage overshoot during LTC4420 power path turn off. A
ILIM
COUT ≥ (9) few micro farads is sufficient for most applications. When
dVOUT
hot plugging supplies with large parasitic inductances, it
dt is possible for the R-L-C tank to ring to more than twice
as the LTC4420 limits OUT charging current to ILIM until the nominal supply voltage. Wall adapters and batteries
OUT approaches the input supply to within ILIM • RON, typically have enough loss (i.e. series resistance) to prevent
where RON is the channel switch resistance. Refer to the ringing of this magnitude. However, if this is a problem,
snub input capacitor CSN1 with resistor RSN1, typically
Thermal Protection and Maximum COUT section to deter-
0.5Ω. Place this network close to the supply pin.
mine maximum allowed COUT.
Third, if an input capacitor is not permissible, use a TVS
Inductive Effects (such as SMAJ16CA) in applications when supply pin
Parasitic inductance and resistance can impact circuit transients can exceed 24V. Use a bidirectional TVS in
performance by causing overshoot and undershoot of input applications requiring reverse input protection. Note that
and output voltages when the LTC4420 turns off. Parasitic a TVS does not address droop and motorboating, which
inductance in the power path causes positive-going are solved only by input bypassing.
overshoot on the input and a negative-going undershoot During normal operation, the LTC4420 limits power path
on the output. Another cause of positive input overshoot is current to < 1.6A and internal circuitry prevents OUT from
R-L-C tank ringing during hot plug of an input supply. Input ringing below ground during power path turn off. This is
overshoot is most pronounced when the total resistance also true for output shorts when the short is close to the
of the input tank is low. Care must be taken to ensure over LTC4420’s OUT pin. However, if the output is shorted
voltage transients do not exceed the Absolute Maximum through a long wire, current in the wire inductance (LPAR2
ratings of the LTC4420. Additionally, parasitic resistance in Figure 3) builds up due to the discharge of COUT1 and
and inductance can cause input undershoot (droop) can be much higher than 1.6A. This current causes the
during power path turn on. If severe enough, undershoot OUT pin to ring below its −0.3V absolute maximum rating
can temporarily invalidate a supply and cause repeated once COUT1 has been fully discharged. For this special
power up cycles (motorboating) or unwanted switchover case, split the output capacitor between COUT1 and COUT2
between sources. and make COUT1 small. Snub COUT1 with resister RSN2 to
The first step to avoid these issues is to minimize parasitic damp R-L-C ringing if required. Size COUT2 to obtain the
inductance and resistance in the power path. Guidelines required total output capacitance. Also add a diode between
are given in the layout section for minimizing parasitic OUT and ground close to the LTC4420 to clamp negative
inductance on the printed circuit board (PCB). External ringing if the OUT pin rings below –0.3V.
to the PCB, twist the power and ground wires together to
minimize inductance.

LPAR1 LTC4420 LPAR2

V1 V1 OUT OUT

COUT2
RSN1 OPTIONAL RSN2 OPTIONAL 10µF
0.5Ω 1Ω

CSN1 COUT1 D1
5µF 1µF 1N5818
4420 F03

Figure 3. Recommended Inductive Transient Suppression Circuitry

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LTC4420
APPLICATIONS INFORMATION
V2 Monitoring and Control V2 monitoring duration and time between monitoring
events are set by input V2TEST, V1 validity and V2 validity
The LTC4420 monitors V2 voltage through an external
as determined previously. Complete behavior is described
resistive divider connected between V2, V2UV and GNDSW.
by the state diagram shown in Figure 4. This implementa-
When V2 is being monitored, open-drain output GNDSW
tion was chosen for the following reasons,
is pulled low to activate the resistive divider, otherwise
it is released high. V2UV is monitored by comparator 1. To provide flexibility in monitoring and disconnect-
CV2UV, whose output is latched at the end of the moni- ing the backup battery as required by the application,
toring period. This latched output establishes V2 validity while minimizing current draw through the V2 resistive
and is used in Table 1. divider. V2TEST and V2DIS need to be actively driven
to achieve this.

POWER THERMAL
OR V2 < 1.55V OR
UP SHUTDOWN

SWITCHOVER EXIT THERMAL

TO V2 OR SHUTDOWN
DISABLE
V2 MONITORING
V2 HIG
TE H
ST

OT
V2 N ID
AN

D V A L
D V

T N
UV ES A
V2T H
V2 ID

T
NO HIG
AL

V2

V2 NOT V2TEST
AND AND V1 VALID
VALID HIGH
2ms
128ms V2 MONITORING
V2 MONITORING V2 V2TEST WHEN V1 IS
AND
VALID HIGH VALID

)
ID
AL
TV
V2 NOT VALID AND V1 NOT VALID
V2 NOT
VALID

NO
V2
ND
VALID
VALID

A
V1
V2

AND

I GH
TH
AND

V2TEST
AND

S ID
TE
HIGH

L
(V VA
ND
V2TEST

V1
V2TEST
HIGH

LOW

A D
ID AN
AND

L
VA OW
V1 TL
VALID

S
TE
V1

V2

V1 V2TEST V2
NOT VALID AND LOW OR NOT VALID ( )
2ms NO V2
EST
V2T WAIT FOR RISING V2 MONITORING T
VA
V1 A ND LOW V2TEST OR WHEN V1 IS LI
D AN
ID OVERRIDE CONDITION
VAL V1 VALID AND V2TEST LOW INVALID D
NO V1
T
VA
LI
D

V1 NOT VALID AND (V2TEST LOW AND V2 NOT VALID)

V2 VALID OR V2TEST HIGH 4420 F04

Figure 4. State Diagram Describing V2 Monitoring

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 LTC4420
APPLICATIONS INFORMATION
2. To provide default battery backup monitoring and dis- If automatic V2 disconnect is desired when a V2 UV event
connect in systems where V2TEST and V2DIS are not occurs, tie V2DIS low. Otherwise leave open or tie to either
actively driven. V2TEST and V2DIS are either tied high OUT or V2 through a pull up resistor. If V2 can be reversed,
or low in these applications. tie V2DIS to OUT. If V2DIS can be actively driven, driving
it low some time after a V2 UV event (output V2OK goes
3. To allow a system powered by OUT to shut itself down
low) allows systems powered by OUT to finish active tasks,
if there is no valid input supply.
backup data and initiate shutdown proceedings.
4. To support backup battery charging without having to
disconnect the battery from the system. Actively Driving V2TEST
5. Handling exceptions such as initial power up, recov- In Figure 5, V2TEST is actively driven. When V1 powers up
ery from thermal shutdown and switchover after long above switchover threshold VSW1, it is qualified for 64ms
intervals when V2 was not being monitored. after which the V1 to OUT power path is activated. When
V2 rises above 1.55V, GNDSW is pulsed low for 128ms
Configuring V2TEST and V2DIS and V2UV is monitored, even though V2TEST is low. V2
V2TEST controls the duration of and the time between is found to be valid resulting in V2OK being driven high.
As long as V1 remains valid, V2 is monitored only when
V2 monitoring events. It can either be tied high, low or
V2TEST is driven high with V2 monitoring time being the
actively driven based on the application. The following
lower of either the V2TEST high time or 128ms. Figure 5
section explores common scenarios.
shows two such monitoring events of durations t1 and
In applications where primary supply V1 is going to be t2 where t1 and t2 are less than 128ms. When V1 drops
valid for long periods of time and where V2TEST can be below VSW1, OUT is switched to V2 and V2 validity is
actively driven, V2TEST should generally be driven low and refreshed by monitoring it once for 128ms independent
only pulsed high when V2 status is needed. This minimizes of the state of V2TEST. Following this, since V2 is the
V2-V2UV-GNDSW divider current. This scenario also only valid supply, V2 is monitored for 2ms every 132s
applies when V2 is a battery that slowly discharges over if V2TEST is low or for 128ms every 132s if V2TEST is
time, making a V2 status update every 132s superfluous. high. If V2 becomes invalid and V2DIS is low, the V2 to
When operating off V2, V2TEST may be pulsed at intervals OUT power path gets disabled.
shorter than 131s to check V2’s validity especially after
large load current spikes. V2TEST Tied Low
If V2TEST cannot be actively driven, it should be tied to Figure 6 shows voltage waveforms for the case where
either V2 or OUT through a pull-up resistor. If V2 can be V2TEST is tied low. When V2 powers up above 1.55V,
reversed, tie V2TEST to OUT. Tying V2TEST high ensures GNDSW is pulsed low and V2 is monitored once for 128ms.
that V2 is monitored every 132s as long as V2 > 1.55V. Simultaneously, the V2 to OUT power path is activated in
V2 monitoring duration is 128ms when V2 is valid and order to allow a system powered by OUT to power itself
reduces to 2ms if V2 becomes invalid. Use smaller resis- up and drive V2DIS to a desired state. V2 is determined
tors in the V2-V2UV-GNDSW divider if V2 is a battery that to be valid causing V2OK to be driven high and the V2
can develop a passivation layer when it is not being used. power path to remain activated. If V2 was determined to
Larger V2 current helps break the passivation whenever be invalid and V2DIS was low, V2’s power path would have
the V2 divider is active. been disabled and V2OK pulled low after 128ms. Since
In special cases where V2 needs to be monitored only both V1 and V2TEST are low, V2 is monitored for 2ms
when V1 goes invalid and when battery passivation is not every 132s. When V1 becomes valid, OUT is switched to
an issue, tie V2TEST low. V1 and V2 monitoring is halted until V1 becomes invalid.

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LTC4420
APPLICATIONS INFORMATION

VSW1 VSW1
V1
VUV2
1.55V
V2 t1 t2

V2TEST
128ms t1 t2 128ms 131s 2ms

GNDSW

V2OK

~64ms V2 POWER PATH ACTIVE

V1 POWER PATH ACTIVE
OUT

TIME 4420 F05

Figure 5. V2 Monitoring by Actively Driving VTEST. Note That t1 and t2 are < 128ms

VSW1
V1

VUV2
1.55V
V2 128ms 131s 2ms 131s 2ms

GNDSW

V2OK ~64ms
V1 POWER
V2 POWER PATH ACTIVE PATH ACTIVE
OUT
TIME 4420 F06

Figure 6. V2 Monitoring When V2TEST Is Low

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14 For more information www.linear.com/LTC4420

 LTC4420
APPLICATIONS INFORMATION
INCREASING CMP1 HYSTERESIS Referring to Figure 1, in order to prevent switchover when
COUT is being initially charged add input capacitor C1.
In some applications, built in CMP1 hysteresis may be
Ideally, if V1 is greater than switchover threshold VSW1
insufficient. In such cases, CMP1 hysteresis can be in-
creased as shown in Figure 7. Hysteresis at the monitored by ∆V, size:
input VMON with R8 present and assuming R9 << R8, is  ∆V 
given by: VSW1 •COUT •  1–
 2 •ILIM •RESR 
R3 R3 C1> (13)
VHYST = VHYSTC + VPU (10) ∆V
R1||R3||R8 R8
to ensure no switchover occurs when COUT is initially be-
ing charged. If the resulting C1 value causes large inrush
where VHYSTC is found in the electrical table and is typi- current, is physically too big or requires a large snubber
cally 10mV. Account for supply VPU and resistor R8 when resistor when V1 is plugged (refer to the Typical Applications
calculating rising and falling thresholds of monitored section), select C1 to be as high a value as the application
input VMON. can tolerate. A filter capacitor CADJ can also be added to
VMON ADJ, to ride through the initial output charge up time. CADJ
should be minimized as it slows ADJ response, resulting
R3
VPU in a larger output droop when the input supply powering
CMP1 V1 is either unplugged or drops quickly.
LTC4420 R9
R1
CMPOUT1 Input Shorts and Supply Brownout
R8
4420 F07
The LTC4420 temporarily turns off its active power path
during input shorts or brownout conditions if the input
Figure 7. Increasing COMP1 Hysteresis supply falls below OUT by 0.7V. If the primary input supply
becomes invalid, switchover to the backup supply occurs.
The power path is reactivated when the input recovers to
Supply Impedance and ADJ Comparator Hysteresis within 0.7V of the output.
In some applications, V1 could be supplied by a battery Figure 8 shows the response of the LTC4420 to a brown-
pack with high ESR or through a long cable with appreciable out and recovery on V1 where switchover to V2 does not
series resistance. Load current, IOUT, flowing through this occur as V1 stays above 1.8V. When V1 falls, OUT gets
resistance reduces the monitored V1 voltage by: disconnected from V1 and is slowly discharged by load
∆V1 = IOUT • RESR (11) resistance ROUT. When V1 recovers, the power path is
reactivated and OUT tracks V1. In Figure 9, when V1 falls,
The drop can be as high as: OUT gets disconnected from V1 as V1 drops below the
ΔV1 = ILIM • RESR (12) switchover threshold. When V1 recovers, it needs to be
qualified for 64ms before it is reconnected to OUT. OUT
when COUT is initially being charged. Voltage droop at the gets discharged by ROUT and is connected to V2 once its
V1 pin can result in repeated switchover between V1 and voltage is 50mV less than V2.
V2 if built-in V1 (ADJ) hysteresis is insufficient.

4420fa

For more information www.linear.com/LTC4420 15

LTC4420
APPLICATIONS INFORMATION
2. Once V2OK is asserted high, drive it below 50mV.
V1
5V/DIV 3. Power up V1 and ADJ for at least 94ms. Complete steps
2 and 3 within 80s of V2OK asserting high. Freshness
V2
seal is enabled.
5V/DIV

1 2 3
OUT
5V/DIV 1.8V
COUT = 10µF
ROUT = 100Ω V2
100µs/DIV 4420 F08

0.48V
Figure 8. Voltage Waveforms During a Brownout on V1
V2UV
That Does Not Result in Switchover to V2. Switchover
Threshold = 1.8V DRIVEN LOW
EXTERNALLY
V2OK

1.8V
V1
5V/DIV
V1
1.116V
FSEAL
V2 94ms ENABLED
5V/DIV ADJ 4420 F10

< 80s
OUT
5V/DIV
COUT = 10µF
Figure 10. Freshness Seal Engage Procedure
ROUT = 100Ω
100µs/DIV 4420 F09

Engage this mode if V2 is a backup battery either during

Figure 9. Voltage Waveforms When a Brownout on V1
Results in Switchover to V2. Switchover Threshold = 3V storage or during shipment. Once freshness seal has been
engaged, if V1 is disconnected, V2 stays disconnected
Reverse Voltage Blocking from OUT. Freshness seal is automatically disabled the
next time V1 is revalidated. Limit V2OK pin capacitance
The LTC4420 blocks reverse voltages on supply pins V1
to less than 10nF in order to prevent freshness seal mode
and V2 up to –15V relative to GND and up to –39V relative
from accidentally being engaged.
to OUT. Transient voltage suppressors (TVS) connected to
V1 and V2 must be bidirectional and capacitors connected Design Example
to these pins must be rated to handle reverse voltages. A
reverse voltage on V2 does not disrupt V1 operation and In Figure 11, the LTC4420 prioritizes between a 5V supply
vice-versa. connected to V1 and a 7.4V 2-cell Li-Ion battery con-
nected to V2. The system is designed to switch OUT to
Freshness Seal Mode V2 when V1 drops below 4V, provide early power failure
Freshness seal mode prevents V2 battery discharge by warning when V1 drops below 4.5V and disconnect the
keeping V2 disconnected from OUT even if V1 is absent backup battery voltage when it drops below 6V. Maximum
or invalid. Very little current is drawn from V2—typically anticipated load current is 100mA and maximum allowed
just 120nA. The following sequence (refer to Figure 10) output droop is 100mV. Output rising slew rate is limited to
puts the LTC4420 in freshness seal mode: <0.1V/µs and V1 and V2 input capacitances are limited to
10µF to avoid large inrush current. 1% tolerance resistors
1. Power up V2 and V2UV. are used ADJ, CMP1 and V2UV pin leakages and GNDSW
VOL are ignored as their design impact is small.
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 LTC4420
APPLICATIONS INFORMATION
5V
V1 OUT OUT VTHC • (R1+R2+R3)
INPUT COUT R1= (18)
RSN1
0.5Ω
R3
LTC4420
15µF VPFV1
365k
R6 R7
C1
1M 1M
0.387V
• ( 500kΩ )
2.2µF ADJ V2TEST
R1= (19)
R2
88.7k 4.5V
CMP1 V2DIS
R1
44.2k
Solving equations 16 and 19 results in R1= 43.3kΩ and
CMPOUT1 PFV1
R2 = 87.6kΩ. Using the nearest 1% resistors results in
+ 2-CELL R5
V2 V2OK V2UV
R2 = 88.7kΩ. Recalculating equation 1 using calculated
Li-Ion 1.37M R2 and R3 values and using standard 1% resistor values
7.4V V2UV
C2 R4 close to 43.3kΩ for R1 results in R1= 44.2kΩ.
2.2µF 95.3k
GNDSW
GND A similar procedure is used to calculate R4 and R5 using
equation 3 and total divider current. Resistance of the
4420 F11

GNDSW pull-down, typically 120Ω, is neglected as it is

Figure 11. Design Example small compared to R4 and R5. The design equations are
shown below.
First choose total resistive divider current to be ~10µA for 7.4V
R4+R5 = = 1.48MΩ (20)
V1 and 5µA for V2. Since the V2 divider is pulsed with a 5µA
maximum duty cycle of 0.1%, average V2 divider current
is negligible. For the 5V supply, this results in: as desired current in the divider is 5µA.
5V Rewriting equation 3 neglecting pin leakage and assuming
R1+R2+R3 = = 500kΩ (14) R5>>R4 results in:
10µA
VTHC • (R4+R5)
Since desired switchover threshold, VSW1, and total divider R4 = (21)
VV2UV
impedance are known, use equation 1 to first calculate R3.
Using R3 and equation 2, calculate R1 and R2. Rewriting 0.387V •1.48MΩ
equation 1 results in: R4 = (22)
6V
VTHA • (R1+R2+R3)
(R1+R2) = (15) Solving equations 20 and 22 results in R4 = 96.2kΩ and
VSW1 R5 = 1.38MΩ. Choosing the nearest 1% resistor results
in R4 = 95.3kΩ and R5 = 1.37MΩ.
Using (R1+R2+R3) = 500kΩ from equation 14, results in:
COUT affects both OUT droop during switchover as de-
1.047V • 500kΩ
(R1+R2) = = 130.9kΩ (16) termined by equation 4 and OUT rising slew rate as de-
4V termined by equation 9. Calculate minimum COUT required
R3 ~ (500kΩ – 130.9kΩ) = 369.1kΩ (17) to meet desired output droop and slew rate specifications
using equations 8 and 9 and size COUT to be the larger of
Using the nearest 1% resistor value yields R3 = 365kΩ.
the two values.
Rearranging equation 2, results in:

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LTC4420
APPLICATIONS INFORMATION
COUT required to limit OUT droop to < 100mV is given by layout, choose C1 to be 2.2µF, which is ~1/5th of COUT to
equation 8, suppress inductive transients. Also snub C1 with a 0.5Ω
resistor to prevent ringing.
COUT ≥
( tPDA + tSWITCH ) •ILOAD
100mV (23) Layout Consideration
Make power and ground traces as wide as possible. Place
COUT ≥
(7.3µs + 2.5µs) • 0.1A = 9.8µF bypass capacitors, snubbers and TVS devices as close to
100mV (24) the pin as possible to reduce power path resistance and
parasitic inductance. These result in smaller overvoltage
COUT required to limit OUT slew rate to < 0.1V/µs is given transients and improved overvoltage protection. Place
by equation 9, resistive dividers close to the pins to improve noise im-
ILIM munity. Use a 4-layer board if possible with layer 2 as
COUT ≥ = 11µF dedicated GND and solder the exposed pad to a large PCB
0.1V/µs (25) GND trace for better heat dissipation. A partial layout for
Choose a COUT capacitor whose minimum value is 11µF a 2-layer PCB is shown in Figure 12.
accounting for voltage and temperature coefficients. Do
this for other capacitors as well. Assuming correct PCB

GND GND
C1 C2

V1 LTC4420 V2

OUT

GND

COUT

4419 F12

Figure 12. Recommended 12-Lead MSE Layout for a 2-Layer PCB

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18 For more information www.linear.com/LTC4420

 LTC4420
APPLICATIONS INFORMATION
THERMAL PROTECTION AND MAXIMUM COUT COUT < 500µF if possible. If a larger COUT is necessary,
Depending on the difference between input and output use Figure 13 to choose COUT. Also follow PCB layout
guidelines to improve heat dissipation.
voltages, the LTC4420’s internal power dissipation can be
high when operating in current limit mode. This usually 60k
occurs when a large COUT is being charged either during ILOAD = 0

initial power up or when OUT switches over to a higher

supply. The situation is worsened if there is a DC load on 10k
OUT, as this reduces the current available to charge COUT.

COUT (µF)
In such cases, self heating can cause power path turn-off
due to activation of the thermal protection circuitry. The 1k
power path is reactivated when die temperature drops to
a safe value. This process can repeat indefinitely if COUT is –40°C
discharged fully by load current IOUT in the interval when 25°C
85°C
the power path is off. 100
5 10 15 20
VIN (V)
Maximum allowed COUT to prevent activation of the thermal 4420 F13

protection circuit depends on several factors such as input Figure 13. Maximum Allowed COUT vs Input
supply and output voltages, starting ambient temperature, Voltage for Different TA
heat dissipation in the PCB and DC output current. Choose

TYPICAL APPLICATIONS

Battery Backup with Interface to Low Voltage Logic

5V TO 18V 3.3V
V1 OUT IN OUT
WALL ADAPTER R3 COUT C3
RSN1 LTC1763-3.3V
365k 10µF 10µF
0.5Ω SHDN GND R6 R7 R8
ADJ
C1 R2 1M 1M 1M
88.7k LTC4420
10µF
CMP1 V2TEST
R1 SYSTEM
44.2k V1UV
CMPOUT1
3.6V TO 18V
V2
BACKUP R5 V2OK
RSN2 1M V2OK
0.5Ω V2UV V2DIS
C2 R4
10µF 150k SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
GNDSW V1UV THRESHOLD: V1 < 4.5V (V1 FALLING)
V2OK THRESHOLD: V2 < 3V (V2 FALLING)
GND
4420 TA02

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For more information www.linear.com/LTC4420 19

LTC4420
TYPICAL APPLICATIONS

SuperCap Backup with SuperCap Charging

V1 OUT OUT
L1 3.3µH V2 COUT R6 R7 R8
4.2V R5 10µF 1M 1M 1M
LTC4420
SW1 SW2 1M
V2UV V2TEST
RSENP VOUT R4
C1 RSENS C2 V2DIS
10µF 940mF R3 127k
MID 1M GNDSW
1.7V TO 5.5V LTC3128 940mF ADJ V2OK V2OK
IN R11 R2
INPUT
PROG 1.87M 237k
C3 R13 MAXV FB CMP1 CMPOUT1 V1UV
120pF 12.1k R14 RUN R12 R1
GND GND
127k 301k 121k SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
V1UV THRESHOLD: V1 < 4.4V (V1 FALLING)
4420 TA03 V2OK THRESHOLD: V2 < 3.5V (V2 FALLING)
C2: MURATA DMF325R5H474M3DTA0

Triple Voltage Monitor

V1 OUT OUT
+ 14.8V R3 R10 R7 R8 COUT
Li-Ion C1 2M 2M 1M 1M 10µF
ADJ CMP1
10µF
R1 R9
191k LTC4420 113k

V2 CMPOUT1 OUTUV
+ 9V R5
V2TEST V2DIS
ALKALINE 1M
C2
10µF V2UV
R4 V2OK V2OK
59k
GNDSW SWITCHOVER THRESHOLD: V1 < 12V (V1 FALLING)
GND V2OK THRESHOLD: V2 < 7V (V2 FALLING)
OUTUV THRESHOLD: OUT < 7.5V (OUT FALLING)
4420 TA04

4420fa

20 For more information www.linear.com/LTC4420

 LTC4420
TYPICAL APPLICATIONS

Early Power Failure Warning with Low Battery Indication

L1, 10µH

C4 C5
0.1µF 0.1µF
SW1 SW2
TO OTHER
BST1 BST2 CIRCUITS
5V TO 15V LTC3111 12V
VIN VOUT V1 OUT OUT
INPUT C7, 1nF R12, 44.2k
R3 C1
COMP
R8 R10 1M 22µF R6 R7 R8 COUT
C8 R13 20k 2.21M 1M 1M 1M 10µF
10µF 1M C6 ADJ
C9
39pF
18pF R2
RUN FB LTC4420
75k
R14 SNSGND VCC R11
137k 158k CMP1 V2TEST
C3
PWM V2DIS
1µF R1
41.2k

V2 CMPOUT1 PFV1
+ 4-CELL C2 R5
14.8V 10µF 2M
Li-ION V2UV V2OK V2OK
R4
PFV1, V1 POWER FAILURE THRESHOLD: V1 < 10.6V (V1 FALLING) 66.5k
SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING) GNDSW GND
V2OK THRESHOLD: V2 < 12V (V2 FALLING)
4420 TA05

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For more information www.linear.com/LTC4420 21

LTC4420
TYPICAL APPLICATIONS
Prioritization with Failsafe Backup Supply

DS
BAT54
COIN
CELL
3V
12V OUT
WALL V1 OUT
ADAPTER R3 R7 R8 COUT
RSN1 10µF
1M 1M 1M
0.5Ω
ADJ V2TEST
C1 R2
10µF 75k CMPOUT1 PFV1
CMP1 V2OK V2UV
R1
41.2k LTC4420

V2 V2DIS
+ 2-CELL C2 R5
Li-Ion 10µF 1.37M
7.4V V2UV PFV1 THRESHOLD: V1 < 10.6V (V1 FALLING)
R4 SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING)
95.3k V2UV THRESHOLD: V2 < 6V (V2 FALLING)
GNDSW
GND 4420 TA06

4420fa

22 For more information www.linear.com/LTC4420

 LTC4420
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings.

DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
R = 0.115 0.40 ±0.10
TYP
7 12
0.70 ±0.05

3.50 ±0.05 2.38 ±0.05 2.38 ±0.10

3.00 ±0.10
2.10 ±0.05 1.65 ±0.05 (4 SIDES) 1.65 ±0.10
PIN 1 PIN 1 NOTCH
PACKAGE TOP MARK R = 0.20 OR
OUTLINE (SEE NOTE 6) 0.25 × 45°
CHAMFER
6 1
0.25 ±0.05 0.200 REF 0.75 ±0.05 0.23 ±0.05
0.45 BSC 0.45 BSC
2.25 REF 2.25 REF (DD12) DFN 0106 REV A

0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
2. DRAWING NOT TO SCALE 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
3. ALL DIMENSIONS ARE IN MILLIMETERS TOP AND BOTTOM OF PACKAGE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

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For more information www.linear.com/LTC4420 23

LTC4420
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings.

MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)

BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
2.845 ±0.102 (.112 ±.004)
(.112 ±.004) 0.889 ±0.127
(.035 ±.005) 1 6 0.35
REF

5.10 1.651 ±0.102

1.651 ±0.102 3.20 – 3.45 0.12 REF
(.201) (.065 ±.004)
MIN (.065 ±.004) (.126 – .136) DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
12 7 FOR REFERENCE ONLY
0.65 NO MEASUREMENT PURPOSE
0.42 ±0.038 4.039 ±0.102
(.0165 ±.0015) (.0256) (.159 ±.004)
TYP BSC (NOTE 3) 0.406 ±0.076
RECOMMENDED SOLDER PAD LAYOUT
12 11 10 9 8 7 (.016 ±.003)
REF
DETAIL “A”
0.254
(.010) 3.00 ±0.102
0° – 6° TYP 4.90 ±0.152
(.118 ±.004)
(.193 ±.006) (NOTE 4)
GAUGE PLANE

0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6
DETAIL “A” 1.10 0.86
0.18 (.043) (.034)
(.007) MAX REF

SEATING
PLANE 0.22 – 0.38 0.1016 ±0.0508
(.009 – .015) (.004 ±.002)
TYP 0.650
MSOP (MSE12) 0213 REV G
NOTE: (.0256)
1. DIMENSIONS IN MILLIMETER/(INCH) BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.

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24 For more information www.linear.com/LTC4420

 LTC4420
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/17 Updated tSWITCH test condition 3
Updated pin function for Exposed Pad 6

4420fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC4420
as described herein will not infringe on existing patent rights. 25
LTC4420
TYPICAL APPLICATION
High Efficiency Backup

C4 C5
22nF L1 22nF
3.3µH

5V BST1 SW1 SW2 BST2 5V

WALL V1 OUT VIN OUT
ADAPTER R3 COUT R12 C6 R7 R8
RSN1
1M 10µF 1.1M 10µF 1M 1M
0.5Ω RUN
ADJ V2TEST RUN LTC3129-1
C1 R2 R11 MPPC
LTC4420
10µF 237k 1.05M VS1
CMP1

SYSTEM
VS2
R1 VCC
121k
PWM GND PGND VS3
C3
2.2µF
V1UV
V2 CMPOUT1
+ 2-CELL C2 R5 V2UV
V2OK
7.4V 10µF 1.37M
Li-Ion V2UV V2DIS
R4 R13 SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
95.3k 1M V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) 4420 TA07
GNDSW V2UV THRESHOLD: V2 < 6V (V2 FALLING)
GND

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4420fa

26
LT 0917 REV A • PRINTED IN USA

www.linear.com/LTC4420
For more information www.linear.com/LTC4420
 LINEAR TECHNOLOGY CORPORATION 2016