Lecture Notes

Power MOSFETs

William P. Robbins
Professor, Dept. of Electrical and Computer Engineering
University of Minnesota

Outline
• Construction of power MOSFETs
• Physical operations of MOSFETs
• Power MOSFET switching Characteristics
• Factors limiting operating specfications of MOSFETs
• COOLMOS
• PSPICE and other simulation models for MOSFETs
MOSFETs - 1
W.P. Robbins
Multi-cell Vertical Diffused Power MOSFET (VDMOS)

contact to source
source
diffusion
conductor
field
oxide

gate
oxide

gate
width
N+ N+ N
+
N+
P P

N-

gate N+
conductor

MOSFETs - 2
W.P. Robbins
 Important Structural Features of VDMOS
source gate conductor
body-source
field oxide
short
gate oxide

N+ N+ N+ N+
P (body) P (body)
N- parasitic i
D
channel
(drift region) BJT length
integral
N+ diode

drain

1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation
layer functions.
4. Division of source into many small areas connected electrically in parallel.
Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.
MOSFETs - 3
W.P. Robbins
Alternative Power MOSFET Geometries

• Trench-gate MOSFET
• Newest geometry. Lowest
on-state resistance.

gate oxide
gate source

• V-groove MOSFET.
N+ N+ P
P • First practical power
MOSFET.
N
• Higher on-state
i
N+
D resistance.

drain MOSFETs - 4
W.P. Robbins
MOSFET I-V Characteristics and Circuit Symbols
i
D [v - V = v ]
GS GS(th) DS
ohmic i
D
VGS5

active
actual
VG S 4

linearized
VG S 3

V
GS2
v
V
GS1 V GS
GS(th)
v
V <V DS
GS GS(th) BV
DSS
D D

G
G
N-channel P-channel
MOSFET MOSFET
S S
MOSFETs - 5
W.P. Robbins
 The Field Effect - Basis of MOSFET Operation
VGG3
VGG1 +
+ SiO
SiO 2
2 + + + + + + + + + + +
+ + + + + + + + + + +

+
+ N
N P
ionized
depletion layer inversion layer
acceptors
P boundary with free electrons
ionized
acceptors
N
N depletion layer boundary
VGG2
+
SiO • Val ue deter mi ned by sever al factor s
2
+ + + + + + + + + + + 1. Type of mater i al used for gate conductor
2. Dopi ng densi ty of body r egi on di r ectl y
+ beneath gate
N
3. I mpur i ti es/bound char ges i n ox i de
ionized depletion layer εox
P acceptors boundary 4. Ox i de capaci tance per uni t ar ea Cox =
t ox
N free electrons
t ox = ox i de thi ck ness
Thr eshol d Vol tage V GS(th)
• Adjust thr eshol d vol tage dur i ng devi ce
• V GS wher e str ong i nver si on l ayer has for med. fabr i cati on vi a an i on i mpl antati on of
i mpur i ti es i nto body r egi on just beneath
Typi cal val ues 2- 5 vol ts i n power MOSFETs
gate ox i de. MOSFETs - 6
W.P. Robbins
 Drift Velocity Saturation

electron
drift velocity
• Mobility also decreases because large
8 x 1 06
values of VGS increase free electron
cm/sec density.

• At larger carrier densities, free carriers

collide with each other (carrier-carrier
4 electric
1.5x10 V/cm field scattering) more often than with lattice and
mobility decreases as a result.

• In MOSFET channel, J = q µn n E
• Mobilty decreases, especially via carrier-
= q n v n ; velocity v n = µn E
carrier scattering leead to linear transfer
curve in power devices instead of square
• Velocity saturation means that the law transfer curve of logic level MOSFETs.
mobility µn inversely proportional to
electric field E.

MOSFETs - 7
W.P. Robbins
 Channel-to-Source Voltage Drop

• VGS = VGG = Vox + VCS(x) ;

V + VCS(x) = ID1RCS(x)
GG V
+ DD1 I
D1

Vo x(x) • Larger x value corresponds be being

closer to the drain and to a smaller
+ V (x) inversion
N CS Vox .
x depletion

P
• Smaller Vox corresponds to a smaller
N channel thickness. Hence reduction in
N+ channel thickness as drain is
approached from the source.

MOSFETs - 8
W.P. Robbins
 Channel Pinch-off at Large Drain Current
• Appar ent di l emma of
channel di sappear i ng at
+
V D D 2+ I
D2 dr ai n end for l ar ge I D

V avoi ded.
GG Vo x(x)

inversion 1. Lar ge el ectr i c fi el d at dr ai n

+ V (x)
N CS end or i ented par al l el to
depletion
x dr ai n cur r ent fl ow. Ar i ses
velocity
fr om l ar ge cur r ent fl ow i n
saturation
P region
channel constr i cti on at
dr ai n.
N
N+ 2. Thi s el ectr i c fi el d tak es
over mai ntenance of
mi ni mum i nver si on l ayer
thi ck ness at dr ai n end.
• I D2 > I D1 so V CS2(x ) > V CS1(x ) and thus channel
nar r ower at an gi ven poi nt. • Lar ger gate- sour ce bi as
V GG postpones fl atteni ng
• Total channel r esi stance fr om dr ai n to sour ce
of I D vs V DS unti l l ar ger
i ncr easi ng and cur ve of I D vs V DS for a fi x ed V GS
val ues of dr ai n cur r ent ar e
fl attens out.
r eached.
MOSFETs - 9
W.P. Robbins
 MOSFET Switching Models for Buck Converter
Vd D

Io r
DS(on)
D
F

RG Cgd
G
+
C
V gs
GG

• Buck converter using power MOSFET. • MOSFET equivalent circuit valid for
on-state (triode) region operation.
D

C
gd

G I = f(V )
D GS • MOSFET equivalent circuit valid for off
C
gs - state (cutoff) and active region operation.
S
MOSFETs - 10
W.P. Robbins
MOSFET Capacitances Determining Switching Speed

gate
source
C
C gs gd
C
gd2 idealization
N
+ P N+
C
P gd
Cd s
actual
C gd1
N
v
drain-body v = v 200 V DS
N+ depletion layer GS DS

drain

• Gate-source capacitance Cgs approximately

constant and independent of applied voltages.

• Gate-drain capacitance Cgd varies with applied

voltage. Variation due to growth of depletion layer
thickness until inversion layer is formed.
MOSFETs - 11
W.P. Robbins
 Internal Capacitances Vs Spec Sheet Capacitances

MOSFET internal capacitances Reverse transfer or feedback capacitance

C gd C
bridge
G D
+V -
C gs Cd s b

S C gd

Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Input capacitance
G D Output capacitance

G D
C iss

S
C oss

S
C iss = C gs + C gd

C oss = C gd + C d s
MOSFETs - 12
W.P. Robbins
 Turn-on Equivalent Circuits for MOSFET Buck Converter
Vi n Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
dur i ng td(on). dur ing tr i .
D D Io
F Io F

C C
DC DC
R R C gd1
G C gd1 G

+ +
V i V i
GG G C GG G C
gs gs

Vi n

Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
dur i ng tfv1. Io dur ing tfv2. Io r
DS(on)
R
G
R Cg d 1
G +
V i C
GG G gs
+ C gd2
V i
GG G

MOSFETs - 13
W.P. Robbins
 MOSFET-based Buck Converter Turn-on Waveforms
V
GG+
τ = R (C + C )
G gd1 gs

v (t)
GS
V
G S , Io

τ = R (C + C )
G gd2 gs
V
GS(th)

i (t)
G

t
Charge on C
Charge on C + Cg d gd
gs
• Free-wheeling diode
V in assumed to be ideal.
t (no reverse recovery
fv2
current).
v (t)
DS
i (t)
D

Io

t
t ri V t
d(on) t DS(on)
fv1
MOSFETs - 14
W.P. Robbins
 Turn-on Gate Charge Characteristic

(Vt+ID1/gm)
Qon = ⌠
⌡ [Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs
Vgs,off
Vds,on
⌠
Qp = ⌡ Cgd(Vds) Vds dVds
Vd
Vgs,on
QT = Qon + Qp + ⌠
⌡ [Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs
(Vt+ID1/gm)
MOSFETs - 15
W.P. Robbins
Turn-on Waveforms with Non-ideal Free-wheeling Diode

Vi n
Io i D (t)
F
Io + I rr

I rr t
C gd1
I rr R
G
i (t)
D +
t rr V i
Io
GG G Cgs

t t
ri

V
GS,I • Equivalent circuit for
V o
GS(th) estimating effect of free
t -wheeling diode reverse
recovery.
Vin v (t)
DS

MOSFETs - 16
W.P. Robbins
 MOSFET-based Buck Converter Turn-off Waveforms

τ 2= R (C
G gd2
+ C )
gs
v (t)
GS τ1= R (C + C )
G gd1 gs • Assume ideal fr ee-
V
GG V w heeling diode.
V GS(th)
G S , Io

• Essentially the
t inver se of the tur n- on
i
G
(t) pr ocess.

t
d(off)
v (t) • Model quanitatively
DS
i
D
(t) using the same
equivalent cir cuits as
V
I
o
in for tur n- on. Simply
use cor r ect dr iving
voltages and initial
t
conditions
t t t
rv2 rv1 fi

MOSFETs - 17
W.P. Robbins
 dV/dt Limits to Prevent Parasitic BJT Turn-on
gate D
source

C
+ N+ G gd
N parasitic
BJT
P P
Cg d
N
+
N S
dVDS
drain
• Large positive Cgd
dt
could turn on parasitic BJT.
D
L+ • Turn-on of T+ and reverse recovery of Df- will
D dv DS
F+ produce large positive Cgd in bridge circuit.
dt
T+ I o

• Parasitic BJT in T- likely to have been in reverse

D
L- active mode when Df- was carrying current. Thus
stored charge already in base which will increase
dv DS
DF - likeyhood of BJT turn-on when positive Cgd is
T- dt
generated.
MOSFETs - 18
W.P. Robbins
 Maximum Gate-Source Voltage
• V GS(max) = maximum per missible gate-
sour ce voltage.

• If V GS >V GS(max) r uptur e of gate oxide by

lar ge electr ic fields possible.

• EBD(oxide) ≈ 5- 10 million V/cm

• Gate oxide typically 1000 anstr oms thick
• V GS(max) < [5x106] [10- 5] = 50 V
• Typical V GS(max) 20 - 30 V

• Static char ge on gate conductor can r uptur e

gate oxide
• Handle MOSFETs w ith car e (gr ound
your self befor e handling device)
• Place anti- par allel connected Zener diodes
betw een gate and sour ce as a pr otective
measur e
MOSFETs - 19
W.P. Robbins
 MOSFET Breakdown Voltage
depletion layer boundary depletion layer boundary
without field plate with field plate action
action of gate electrode of gate electrode

+ +
N N N
P P

+
N

• BVDSS = drain-source breakdown 2. Appropriate length of drain drift region

voltage with VGS = 0
3. Field plate action of gate conductor
• Caused by avalanche breakdown of overlap of drain region
drain-body junction
4. Prevent turn-on of parasitic BJT with
• Achieve large values by body-source short (otherwise BVDSS
= BVCEO instead of BVCBO)
1. Avoidance of drain-source reach-
through by heavy doping of body
and light doping of drain drift region
MOSFETs - 20
W.P. Robbins
 MOSFET On-state Losses
source gate

accumulation
channel layer
resistance resistance
+
N N+
P
P
I drift region
source region D resistance
resistance
N

drain region
resistance
+
N

drain

• On-state power dissipation Pon = • rDS(on) dominated by drain drift resistance

Io2 rDS(on) for BVDSS > few 100 V

Vd BVDSS2
• Large VGS minimizes accumulation • rDS(on) = ≈ 3x10-7
ID A
layer resistance and channel
resistance • rDS(on) increases as temperature increases.
Due to decrease in carrier mobility with
increasing temperature. MOSFETs - 21
W.P. Robbins
 Paralleling of MOSFETs

Rd
• MOSFETs can be easily
paralleled because of Q
1
positive temperature G
coefficient of rDS(on).

• Positive temperature coefficient leads to thermal

stabilization effect.

• If rDS(on)1 > rDS(on)2 then more current and thus

higher power dissipation in Q2.

• Temperature of Q2 thus increases more than

temperature of Q1 and rDS(on) values become
equalized.

MOSFETs - 22
W.P. Robbins
 MOSFET Safe Operating Area (SOA)

log ( i )
D

I
• No distinction betw een
DM
FBSOA and RBSOA. SOA
10
-5
sec
is squar e.

10 -4 sec
• FB = for w ar d bias.
Tj , m a x V GS ≥ 0.
-3
10 sec
• RB = r ever se bias.
V GS ≤ 0.

DC • No second br eakdow n.

BV
DSS

log ( v )
DS
MOSFETs - 23
W.P. Robbins
Structural Comparison: VDMOS Versus COOLMOS™
source
gate
cond
uctor

N+ N+ N+ N+
+ +
P P
• Conventional
vertically oriented
N-
power MOSFET

N+

drain

• COOLMOS™ structure
(composite buffer
structure, super-junction
MOSFET, super multi
-resurf
MOSFET)
• Vertical P and N regions of
width b doped at same
density (Na = Nd)

MOSFETs - 24
W.P. Robbins
COOLMOS™ Operation in Blocking State

• COOLMOS™ structure partially

depleted.
• Arrows indicate direction of
depletion layer growth as device
turns off.
• Note n-type drift region and
adjacent p-type stripes deplete
uniformly along entire vertical
length.

• COOLMOS™ structure at edge

of full depletion with applied
voltage Vc. Depletion layer
reaches to middle of vertical P
and N regions at b/2.
• Using step junction formalism,
Vc = (q b2 Nd)/(4 ε) = b Ec,max/2
• Keep Ec,max ≤ EBD/2. Thus
Nd ≤ ( ε EBD)/(q b)

MOSFETs - 25
W.P. Robbins
 COOLMOS™ Operation in Blocking State (cont.)

• For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.

• Ev spatially uniform since space charge compensated for by Ec. Ev ≈ V/W for V >> Vc.

• Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.

• At breakdown Ev = EBD ≈ 300 kV/cm ; V = BVBD = EBDW

MOSFETs - 26
W.P. Robbins
 COOLMOS™ Operation in ON-State

• On-state specific resistance ARon [Ω-cm2]

much less than comparable VDMOS
because of higher drift region doping.

• COOLMOS™ conduction losses much

less than comparable VDMOS.

• Ron A = W/(q µnNd) ; Recall that Nd = (ε EBD)/(q b)

• Breakdown voltage requirements set W = BVBD/ EBD.

• Substituting for W and Nd yields Ron A = (b BVBD)/(ε µn EBD2)

MOSFETs - 27
W.P. Robbins
 Ron A Comparison: VDMOS versus COOLMOS™

• COOLMOS at BVBD = 1000 V. Assume b ≈ 10 µm. Use EBD = 300 kV/cm.

• Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 Ω-cm . Corresponds to Nd = 4x1015 cm-3

• Typical VDMOS, Ron A = 3x10-7 (BVBD)2

• Ron A = 3x10-7 (1000)2 = 0.3 Ω-cm ; Corresponding Nd= 1014 cm3

• Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40

• At BVBD = 600 V, ratio = 1/26.
• Experimentally at BVBD = 600 V, ratio is 1/5.

• For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, “Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model”,
IEEE Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)

MOSFETs - 28
W.P. Robbins
 COOLMOS™ Switching Behavior
• Larger blocking voltages Vds > depletion
• MOSFET witching waveforms for clamped inductive load. voltage Vc, COOLMOS has smaller Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.

• Small blocking voltages Vds < depletion

v (t) voltage Vc, COOLMOS has larger Cgs, Cgd,
GS V GS,Io
and Cds than comparable (same Ron and
V
GS(th) BVDSS) VDMOS.

t
• Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V • Turn-on delay time - shorter
DS(on)
d
• Current rise time - shorter

t
• Voltage fall time1 - shorter
td ( o n ) t r i t fv1 t t d(off) t rv1 tfi • Voltage fall time2 - longer
fv2
• Turn-off delay time - longer
i (t) t rv2 • Voltage rise time1 - longer
D Io
• Voltage rise time2 - shorter
t • Current fall time - shorter

MOSFETs - 29
W.P. Robbins
 PSPICE Built-in MOSFET Model

Circuit components

Drain

RD • RG, RDS, RS, RB, and RD = parasitic

Cgb
ohmic resistances
Cbd

• Cgs Cgd, and Cgb = constant voltage-

Cgd independent capacitors

RG RB
RDS Idrain • Cbs and Cbd = nonlinear voltage-
Gate Bulk dependent capacitors (depletion layer
capacitances)
Cgs Cbs

• Idrain = f(Vgs, Vds) accounts for dc

RS characteristics of MOSFET
Source

• Model developed for lateral (signal level)

MOSFETs

MOSFETs - 30
W.P. Robbins
 Lateral (Signal level) MOSFET

• Body-source short keeps Cbs constant.

• Body-source short puts Cbd between drain and

source.

• Variations in drain-source voltage relatively

small, so changes in Cbd also relatively small.

• Capacitances relatively independent of terminal

voltages

• Cgs, Cbg, Cgd due to electrostatic • Consequently PSPICE MOSFET model has
capacitance of gate oxide. Independent voltage-independent capacitances.
of applied voltage

• Cbs and Cbd due to depletion layers.

Capacitance varies with junction voltage.
MOSFETs - 31
W.P. Robbins
 Vertical Power MOSFET

• Drain-drift region and large drain-source • MOSFET circuit simulation

voltage variations cause large variations in models must take this variation
drain-body depletion layer thickness into account.
• Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.

• Moderate changes in Cgb and Cbs.

MOSFETs - 32
W.P. Robbins
 Inadequacies of PSPICE MOSFET Model
4
MTP3055E
V = 0 • Cgs and Cgd in PSPICE model are
C gd GS
constant independent of terminal voltages
[nF]
2 SPICE model
• In vertical power MOSFETs, Cgd varies
substantially with terminal voltages.
Motorola subcircuit model

0
0V 10V 20V 30V
V
DS

60V
MTP3055E V • Comparison of transient response of drain-
DS source voltage using PSPICE model and
40V an improved subcircuit model. Both
Motorola models used in same step-down converter
SPICE
20V subcircuit circuit.
model
model
0V
0s 100ns 200ns 300ns
Time
MOSFETs - 33
W.P. Robbins
 Example of an Improved MOSFET Model
• Developed by Motorola for their TMOS line of
power MOSFETs

Dr a i n • M1 uses built-in PSPICE models to describe

dc MOSFET characteristics. Space charge
LDRAIN capacitances of intrinsic model set to zero.
DGD
CGDMAX • Space charge capacitance of DGD models
RDRAIN1 voltage-dependent gate-drain capacitance.
RGDMAX RDRAIN2 • CGDMAX insures that gate-drain capacitance
does not get unrealistically large at very low
LGATE RGATE DBODY drain voltages.
M1 • DBODY models built-in anti-parallel diode
Gate CGS inherent in the MOSFET structure.
RDBODY
RSOURCE • CGS models gate-source capacitance of
MOSFET. Voltage dependence of this
LSOURCE capacitance ignored in this model.
• Resistances and inductances model parasitic
Source components due to packaging.
• Many other models described in literature. Too
numerous to list here.
MOSFETs - 34
W.P. Robbins
 Another Improved MOSFET Simulation Model
Drain
• M2 and M3 are SPICE level 2
L
D
MOSFETs used along with Voffset to
model voltage dependent behavior of
R Cgd.
d

M2 M3
• JFET Q1 and Rd account for voltage drop
D sub
V offset Q
1
in N- drain drift region
+
-

Gate M1
• Dsub is built-in SPICE diode model used
LG R
G to account for parasitic anti-parallel diode
in MOSFET structure.
RS

LS
• Reference - "An Accurate Model for
Power DMOSFETs Including Inter-
Source electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
• LG, RG, LS RS, LD, RD - parasitic Johnson, IEEE Trans. on Power
Electronics, Vol. 6, No. 2, pp. 192-198,
inductances and resistances (April, 1991)
• M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.

MOSFETs - 35
W.P. Robbins