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    MEL ZG621 VLSI DESIGN (Lect 4)

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    2023ht80200
    1. The document summarizes a lecture on VLSI design that covered layout design rules and CMOS inverter design. 2. Key topics included minimum feature size, lambda design rules, transistor layout, and the mask layers used. 3. The lecture also demonstrated the full-custom layout design process for a CMOS inverter and discussed inverter circuit characteristics.

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    MEL ZG621 VLSI DESIGN (Lect 4)

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    2023ht80200
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    1. The document summarizes a lecture on VLSI design that covered layout design rules and CMOS inverter design. 2. Key topics included minimum feature size, lambda design rules, transistor layout, and the mask layers used. 3. The lecture also demonstrated the full-custom layout design process for a CMOS inverter and discussed inverter circuit characteristics.

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    VLSI DESIGN

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    1. The document summarizes a lecture on VLSI design that covered layout design rules and CMOS inverter design. 2. Key topics included minimum feature size, lambda design rules, transistor layout, and the mask layers used. 3. The lecture also demonstrated the full-custom layout design process for a CMOS inverter and discussed inverter circuit characteristics.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    20 views24 pages

    MEL ZG621 VLSI DESIGN (Lect 4)

    Uploaded by

    2023ht80200
    1. The document summarizes a lecture on VLSI design that covered layout design rules and CMOS inverter design. 2. Key topics included minimum feature size, lambda design rules, transistor layout, and the mask layers used. 3. The lecture also demonstrated the full-custom layout design process for a CMOS inverter and discussed inverter circuit characteristics.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 24

    VLSI DESIGN

    MEL ZG621
    Lecture-4
    19-08-2023
    Dr. Vilas H Gaidhane
    BITS Pilani
    Dubai Campus
    Lecture 4
    Module 1 Module 2

    1. Layout Design Rules 1. Resistive load inverter

    2. Full custom mask layout 2. Inverter with n-type MOSFET


    design load

    19-Aug-2023 MEL ZG621 VLSI Design 2


    Module 1
    Layout Design Rule
    ➢The physical mask layout of any circuit to be manufactured must
    conform to a set of geometric constraints or rules, called layout design
    rules.
    ➢Objective of design rules is to achieve a high overall yield and reliability
    using the smallest possible silicon area.
    ➢Design rules are defined in to ways
    1. Micron rules, in which the layout constraints such as minimum
    feature sizes are stated in terms of absolute dimensions in
    micrometers.
    2. Lambda rules, which specify the layout constraints in terms of a
    single parameter (l).
    19-Aug-2023 MEL ZG621 VLSI Design 3
    Layout design rules
    ➢ Chips are specified with set of masks
    ➢ Minimum dimensions of masks determine transistor size (and hence
    speed, cost, and power)
    ➢ Feature size f = distance between source and drain
    ➢ Feature size improves 30% every 3 years or so
    ➢ Normalize for feature size when describing design rules
    ➢ Express rules in terms of l = f/2
    ➢Example. l = 0.3 mm in 0.6 mm process

    19-Aug-2023 MEL ZG621 VLSI Design 4


    Layout design rules
    Layer Color Representation

    Well (p,n) Yellow


    Active Area (n+,p+) Green
    Select (p+,n+) Green
    Polysilicon Red
    Metal1 Blue
    Metal2 Magenta
    Contact To Poly Black
    Contact To Diffusion Black
    Via Black

    19-Aug-2023 MEL ZG621 VLSI Design 5


    Layout design rules
    Same Potential Different Potential
    9 λ 2λ
    0
    Well or Polysilicon
    6λ
    10 λ 2λ
    3λ 3λ
    Active Metal1
    Contact
    or Via 2λ
    3λ Hole 3λ
    2 λ 2 λ
    Select Metal2
    4λ

    2λ 3λ

    19-Aug-2023 MEL ZG621 VLSI Design 6


    Layout design rules- Sample Set

    19-Aug-2023 MEL ZG621 VLSI Design 6


    Full-Custom Mask Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 8


    Full-Custom Mask Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 8


    Full-Custom Mask Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 8


    Full-Custom Mask Layout Design
    ➢The basic mask layout principles for CMOS inverters and logic gates
    ➢This physical structure directly determines the Transconductance, the parasitic
    capacitances and resistances, and the silicon area.
    ➢To save the time and effort, automated layout generation is generally preferred
    ➢The physical (mask layout) design of CMOS logic gates is an iterative process

    Stick Diagram

    pMOS

    nMOS

    19-Aug-2023 MEL ZG621 VLSI Design 8


    Full-Custom Mask Layout Design

    Functionality and
    Performance
    Specifications

    Design Rule Check


    Circuit Topology

    Estimate Parasitics Circuit and Parasitics


    Capacitance
    Extraction

    Resize and
    Initial sizing of Modify
    Transistors
    Circuit Simulation
    Stick diagram
    Improved
    Layout Performance
    Mask Layout Complete
    Design

    19-Aug-2023 MEL ZG621 VLSI Design 9


    CMOS Inverter Layout Design
    ➢The mask layout design of a CMOS inverter will be examined step-by-step
    1. Create the transistors according to the design rule

    19-Aug-2023 MEL ZG621 VLSI Design 10


    CMOS Inverter Layout Design
    ➢The mask layout design of a CMOS inverter will be examined step-by-step
    1. Create the transistors according to the design rule

    19-Aug-2023 MEL ZG621 VLSI Design 11


    CMOS Inverter Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 12


    CMOS Inverter Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 13


    CMOS Inverter Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 13


    CMOS Inverter Layout Design

    19-Aug-2023 MEL ZG621 VLSI Design 18


    Module 2
    1. Resistive load inverter

    2. Inverter with n-type MOSFET load

    19-Aug-2023 MEL ZG621 VLSI Design 19


    Inverter
    • Inverter is a fundamental logic gate that performs a Boolean
    operation on a single input variable.

    • The inverter can be design by MOS circuit

    Input A Output B
    0 1
    1 0

    Voltage transfer characteristic (VTC) of the ideal inverter.


    19-Aug-2023 MEL ZG621 VLSI Design 20
    MOS Inverter
    • Inverter is a fundamental logic gate that performs a Boolean
    operations

    Vin = VGS
    Vout = VDS

    Next circuit seen by the output node


    can be represented as a lumped capacitance,
    Driver
    Cout

    General circuit structure of an nMOS inverter.


    19-Aug-2023 MEL ZG621 VLSI Design 21
    MOS Inverter
    • For very low input voltage
    levels, the output voltage V is
    equal to the high value of VOH
    (output high voltage)

    • As Vin increase gradually,


    driver MOS conduct, and
    output start decreasing slowly.

    • On VTC curve, two critical


    points are located at which
    slope is -1. i.e.,
    dVout
    voltage transfer characteristic (VTC) of a realistic = −1
    dVin
    nMOS inverter.
    19-Aug-2023 MEL ZG621 VLSI Design 22
    MOS Inverter
    ➢ Input and output Voltage Levels
    VOH : Maximum output voltage when the output level is logic " 1"
    VOL : Minimum output voltage when the output level is logic "0"
    VIL : Maximum input voltage which can be interpreted as logic "0"
    VIH : Minimum input voltage which can be interpreted as logic " 1"

    VIN Vout ➢Noise Margin is usually defined in

    VOH terms of Low Noise Margin (NML) and


    NMH High Noise Margin (NMH).
    𝑉𝐼𝐻 Transition
    Region
    𝑉𝐼𝐿 NM L = VIL −V
    NML OL
    VOL
    NM H = V −V
    OH IH

    19-Aug-2023 MEL ZG621 VLSI Design 23


    MOS Inverter
    2 Enhancement type
    MOS Load Inverter
    1 Resistive Load
    Inverter

    3 Depletion type MOS Load 4 CMOS Inverter


    Inverter
    19-Aug-2023 MEL ZG621 VLSI Design 24

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