ZXSpectrum48K ServiceManual
ZXSpectrum48K ServiceManual
ZXSpectrum48K ServiceManual
FOR
ZX SPECTRUM®
• LIST OF CONTENTS
INTRODUCTION
SECTION 2 DISASSEMBLY/ASSEMBLY
i LIST OF ILLUSTRATIONS i
Fig No.
(i)
- INTRODUCTION
SYSTEM DESCRIPTION
1 Introduction 1.1
2 Architecture 1.1
3 Z80A CPU 1.2
4 Memory Organisation 1.4
Read/Write Operations 1.4
5 Input/Output 1.6
TV Picture Generation 1.6
Keyboard Scanning 1.8
Tape Interface 1.10
6 Power S u p p l i e s 1.11
Circuit Diagrams
ZX Spectrum, Issue 2 Fig. 1.4
ZX Spectrum, Issue 3 Fig. 1.5
1. INTRODUCTION
2. ARCHITECTURE
1.1
3. Z80A CPU
3.3 Address Bus. A15-AO constitutes a 16-bit address bus with active
h i g h , tri-state outputs. The address bus provides the address for
memory (up to 64k bytes) data exchanges and for data exchanges with
the ULA. It is also used d u r i n g the interrupt routine (see below)
when scanning the keyboard matrix.
3.6 The read and write s i g n a l s ( R D and W R ) are active low, and one or
other is active i n d i c a t i n g that the CPU wants to read or write data to
a memory l o c a t i o n or I/O device. All the control s i g n a l s discussed so
far are active low, tri-state outputs.
The control signal described here is the interrupt
3.7 last maskable
(INT). This input is active low and is generated by the ULA once
every 20 ms. Each time it is received the CPU ' c a l l s ' the ' m a s k a b l e
i n t e r r u p t ' routine d u r i n g which the real-time is incremented and the
keyboard is scanned.
1.2
3.9 Dynamic Memory Refresh. The CPU incorporates b u i l t - i n dynamic RAM
refresh circuitry. As part of the instruction OP code fetch cycle,
the CPU performs a memory request after first p l a c i n g the refresh
address on the lower eight bits of the address bus. At the end of the
cycle the address is incremented so that over 255 fetch cycles, each
row of the dynamic RAM is refreshed. This mechanism only applies to
the optional 32k expansion RAM in the 48k Spectrum. An alternative
refresh method is adapted for the standard 16K RAM.
4. MEMORY ORGANISATION
4.1 In the standard 16k Spectrum there are 32k bytes of addressable memory
e q u a l l y divided between ROM and RAM.
4.2 The lower 16k bytes of memory (addresses 0000 - 3FFF) are implemented
in a single ROM (IC5) which holds the monitor program. This program
is a complex Z80 machine code program divided broadly into three parts
one each covering the input/output routines, the BASIC interpreter and
expression h a n d l i n g . Details of the program content, although outside
the scope of this m a n u a l , are referred to as necessary.
4.3 The upper 16 bytes of memory (addresses 4000 - 7FFF) are implemented
using eight 16k bit dynamic RAMs (IC6-IC13). Approximately h a l f of
this space is a v a i l a b l e to the user for w r i t i n g BASIC or machine code
programs. The remainder is used to hold the system v a r i a b l e s
i n c l u d i n g 6k bytes reserved for the memory mapped d i s p l a y area.
1.4
m e c h a n i s m a l l o w i n g the CPU to read the extension ROM in the interface
for m i c r o d r i v e and RS232 a p p l i c a t i o n s .
4.5.4 Standard 16k RAM (IC6-IC13). The eight 16k RAM ICs m a k i n g up the
standard 16k x 8 bit RAM memory are organised as a matrix of 128 rows
x 128 columns. Thus, separate 7-bit row and column addresses are
reguired to access any one of the locations. These addresses are
s u p p l i e d by the CPU on address bus A13-AO via an address multiplexer
IC3/IC4. The low order address bits A6-AO give the row address and
are selected at the b e g i n n i n g of the memory access cycle when
i n i t i a l l y the RAS output from the ULA is high. Later, as the row
address is latched, RAS goes low selecting the high order address bits
A13-A7 giving the c o l u m n address.
4.5.5 The RAS/CAS outputs from the ULA are generated in seguence in response
to MREQ and A14 from_the CPU. The DRAMWE output, a l s o from the ULA is
a decode of the RD/WR waveforms t e l l i n g the RAM to expect either a
read or a write cycle.
4.5.6 It is also apparent from the circuit diagram that the ULA can access
RAM by generating a set of addresses independent of those generated by
the CPU. The address port for the RAM is therefore d u a l l e d by the
i n s e r t i o n of small value resistors (R17-R23) on the address
m u l t i p l e x e r side of the RAM. This ensures that where there is likely
to be conflict between the ULA and CPU, the ULA address has priority.
Priority is assigned on the basis that the ULA must access the memory
mapped d i s p l a y area in the RAM at set i n t e r v a l s in order to b u i l d up
the video for the TV d i s p l a y . If the ULA is about to access the RAM
and it detects either A14 or A15 (i.e. the CPU is also about to access
the RAM) the ULA i n h i b i t s the CPU clock temporarily h a l t i n g the CPU
memory transaction until its own transaction is completed.
4.5.7 Resistors Rl to R8, in series with the data bus lines, perform a
s i m i l a r function to the address portplr£sistors described above. They
ensure that the ULA does not 'see' CPU write data w h i l e the ULA is
accessing the RAM.
4.5.8 Refresh for the standard 16k dynamic RAM is accomplished during normal
read cycles, i.e. most rows are refreshed each time the ULA accesses
the memory mapped display area d u r i n g picture compilation; the
remaining rows are refreshed as a result of other read cycles also
known to occur at regular intervals w i t h i n the refresh period.
1.5
4.5.9 32k Expansion RAM (IC15-IC32). The eight 32k ICs m a k i n g up the 32k x
8 bit expansion RAM are in fact 64k ICs with either row or column
drop-out rendering one half of the memory n o n - f u n c t i o n a l . In order to
accommodate the Texas Instruments RAM (Type TMS 4532) or the optional
OKI RAM (Type MSM3732) a set of l i n k s are provided, v i s i b l e on the
c i r c u i t diagram above the address m u l t i p l e x e r IC25/IC26. These l i n k s
not only cater for the different m a n u f a c t u r e r (Issue 3 Spectrums o n l y )
but a l s o a l l o w , in both instances, one of two 1C versions to be
selected depending on which h a l f of the RAM (top, bottom, left or
right) is f u n c t i o n a l . The l i n k s are respectively TI and OKI
(manufacturer - Issue 3 Spectrums o n l y ) , -3/-4 (TI version) and -H/-L
(OKI version - Issue 3 Spectrums o n l y ) .
NOTE: It is essential when replacing ICs in this area that all RAMs
carry the same manufacturers part number and that the l i n k s
are selected a c c o r d i n g l y .
4.5.10 The expansion RAM is organised as a matrix of 128 rows x 256 columns
(TI RAMs) or 256 rows x 128 (OKI RAMs). Thus, separate 7/8 bit row
and column addresses are required to access any one of these
l o c a t i o n s . These addresses are supplied by the CPU on address bus
A14-AO via an address m u l t i p l e x e r IC25/IC26. For example, when
accessing the TI RAM the low order address bits A6 to AO give the row
address; AR is h e l d low on the -3 version selecting the top half of
the memory and high on the -4 version selecting the bottom h a l f . The
column address is given by the high order address bits A14-A7.
4.5.11 Row/column address selection and RAS/CAS t i m i n g for the RAM is decoded
in IC23/IC24 from inputs s u p p l i e d by the CPU, i.e. address l i n e A15
selecting addresses 8000 upwards, and MREQ heralding a memory read or
write cycle. A theoretical t i m i n g diagram i l l u s t r a t i n g the RAS/CAS
waveforms is given in Figure 1.2.
5. INPUT/OUTPUT
5.1 The input/output section of the Spectrum is centered round the ULA
(IC1). The functions performed w i t h i n the device i n c l u d e TV video
c o m p i l a t i o n , keyboard scanning and tape input/output. It also derives
and controls the CPU clock (<j>CPU) using an external 14 MHz crystal XI,
and drives the loudspeaker when a ' B E E P ' instruction is being
executed. Each of these sections and the supporting circuits are
described below.
1.6
FIG 1.2 EXPANSION RAM RAS/CAS TIMING (READ CYCLE SHOWN)
1.7
5.2.2 U s i n g the 14 MHz clock the ULA derives l i n e and f i e l d t i m i n g
compatible with the external TV receiver. Video is derived by
accessing the memory mapped display area in the RAM in a set seguence
at set times throughout the picture frame. The addresses are
necessarily independent of the CPU and appear on the ULA address lines
A6 through AO as two separate bytes timed by the RAS/CAS row/column
address select l i n e s .
5.2.3 The net result is three separate video waveforms outputs from the ULA
on pins 15, 16 and 17. These carry the l u m i n a n c e signal Y,
i n c o r p o r a t i n g the l i n e and field sync, and two u n m o d u l a t e d c o l o u r -
difference s i g n a l s U and Y m a k i n g the Spectrum c o m p a t i b l e with both
colour and monochrome receivers.
5.2.4 From the ULA the colour difference s i g n a l s are a p p l i e d to the colour
m o d u l a t o r IC14 via two level s h i f t i n g networks. These match the ULA
output levels with those reguired at the B-Y and R-Y inputs to the
modulator. In the Issue 2 Spectrum the l e v e l s h i f t i n g network is
passive, incorporating two potentiometers VR1, VR2. These are
reguired to set-up the chroma b i a s level on IC14 pin 3 such that the
voltage difference measured between pin 3 and the colour difference
s i g n a l s on pins 2 and 3 respectively is n o m i n a l l y 0V d.c. In the
Issue 3 Spectrum two active networks i n c o r p o r a t i n g IRS and TR9
e l i m i n a t e the potentiometers, greatly i m p r o v i n g colour stability.
5.2.5 The level shifted c o l o u r difference s i g n a l s , input to IC14, are then
encoded, by guadrature m o d u l a t i n g two 4.43 MHz chroma sub-carriers.
The sub-carriers are generated with the assistance of an external
crystal X2 and a CR l e a d / l a g network introducing a 90° phase shift
between pins 1 and 18. (A further difference between the Issue 2 and
3 Spectrums lies in the bias o s c i l l a t o r . The early issues incorporate
a trimmer TC2 a l l o w i n g the chroma sub-carrier freguency to be
adjusted; on the later issues the freguency is f i x e d ) . The resultant
m o d u l a t e d colour difference s i g n a l s are f i n a l l y mixed producing a
composite chroma sub-carrier at IC14 pin 13.
5.2.6 At this point the chroma s i g n a l is a.c. coupled to the base of TR2 and
added to the inverted luminence signal on TR1 collector. The
resultant composite video is then buffered and a p p l i e d to an
encapsulated U H F m o d u l a t o r operating on European standard channel 36.
5.3.3 The seguence starts with I/O port address FE d r i v i n g address line A8
low. The keyboard matrix also sees t h i s potential on column 6 a p p l i e d
via D6 and the ribbon cable KB2. Thus, when any of the switches on
the inter-section with column 6 is pressed, the corresponding row
output s u p p l y i n g the ULA via the second ribbon cable (KB1), is p u l l e d
low. The row s i g n a l ( s ) is subseguently inverted by the ULA and placed
on one of the five low order data bus l i n e s . For e x a m p l e , if the CAPS
SHIFT key is pressed row one output drives data bus DO high and so on.
The seguence ends with I/O address 7F when c o l u m n 8 is addressed. In
t h i s instance, operation of the SPACE key drives DO h i g h . C l e a r l y ,
the keyboard scanning routines make the d i s t i n c t i o n between the CAPS
SHIFT and SPACE key by knowing which address l i n e is being driven.
5.4.1 When LOADing or SAVEing programs using a cassette recorder, the ULA
transfers i n f o r m a t i o n between the M I C and EAR sockets and the data
bus, performing A/D and D/A conversions as reguired. Since the LOAD
and SAVE functions are m u t u a l l y e x c l u s i v e , a s i n g l e pin on the ULA
(i.e. pin 28) is used both for input and output. Separate I/O
read/write cycles to port address 254 configure the pin accordingly.
During the LOAD operation the CPU executes successive I/O read cycles,
reading the EAR input off data bus 6. When performing a SAVE
operation, the CPU executes successive I/O write cycles, this time
w r i t i n g data to the MIC output via data bus 3.
5.4.2 To ensure that I/O cycles are correctly implemented, the IOREQ l i n e
s u p p l y i n g the ULA is gated with address l i n e AO via TR6. Thus, if any
memory transactions occur where AO is high (i.e. not port address 254)
then the IOREQ input is forced high i n h i b i t i n g any attempt to perform
an I/O cycle.
1.10
6. POWER SUPPLIES
(a) regulated +5V for the 1C logic c i r c u i t s , the ULA and the U H F
modulator,
(b) -5V and +12V for the standard 16k dynamic RAM,
DISASSEMBLY/ASSEMBLY
1 Disassembly 2.1
2 Assembly 2.1
1. DISASSEMBLY
1.3 To change either the keyboard membrane or the rubber keyboard mat it
is first necessary to remove the escutcheon plate (template). This is
attached to the case by double-sided adhesive tape around the edges.
The template is removed by inserting a screwdriver at one end and
l e v e r i n g it away from the case. It is not n o r m a l l y possible to remove
the template without damage.
2. ASSEMBLY
2.2 When r e p l a c i n g a keyboard component, note that the membrane keys into
projections on the case. Place the keypad over the membrane and
ensure that it is positioned and seated properly. Faulty i n s t a l l a t i o n
can result in depressed keys being trapped under the template during
subsequent key operations. To install the template, place double-
sided adhesive tape around all four edges, locate it in position on
the case and apply firm pressure around the edges (12 mm tape on sides
and bottom, 6 mm at top).
2.1
2.3 When a l i g n i n g the top h a l f of the case with the bottom h a l f ensure
that the two keyboard ribbon cables are not trapped between projecting
components w i t h i n the case. In their correct positions there is
s u f f i c i e n t room for the cables to take up a comfortably curved
position i n s i d e the case. If a cable is trapped and bent d o u b l e , an
open c i r c u i t w i l l sooner or later r e s u l t .
SECTION 3
1. GENERAL ALIGNMENT
1.2 Voltage Check. Check that the i n t e r n a l l y generated power voltages are
as f o l l o w s :
1.3 Colour Adjustment. Potentiometers VR1 and VR2 are used to effectively
n u l l the voltages between pins 4 and 2 (for VR1) and pins 2 and 3 (for
VR2) on IC14 (LM1889). To a l l o w for thermal drift, the potentiometers
are set for non-zero voltages; furthermore these voltage off-sets are
set to satisfactory but non-optimum l e v e l s in production, and optimum
values may be used to advantage in servicing. The relevant figures
are given in the f o l l o w i n g t a b l e - voltages are given relative to pin
3 of LM1889.
3.1
Pot. IC14 Factory Settinq Optimum ( m V ) Overall Ranqe
Pin No. (mV) Voltage Tolerance (mV)
(b) Connect pin 17 of IC14 (LM1889) via a 4.7 pF capacitor and a lead
to the frequency meter. It is recommended that this is done
u s i n q a jiq made up from an 1C test c l i p . Pin 18 of this c l i p
must be removed to m i n i m i s e stray capacitance. Connect a 10k ohm
resistor between the input t e r m i n a l s of the frequency meter.
Measure the frequency and adjust trimmer TC2 if the measured
frequency is outside tolerance.
(a) Set up the Spectrum to display qreen PAPER with red INK.
(b) Type-in three or four lines of characters and monitor the screen.
3.2
2. SYSTEM TEST
2.1 The system test for the Spectrum may be undertaken using the ZXTP
taped program (see 1.1 Test Equipment in Section 4) loaded
conventionally; this requires that the keyboard is connected. The
test should be carried out with the Spectrum connected to its own
power supply.
2.2 The test program exercises all of the Spectrum circuitry with the
exception of the SAVE function. To test this function a small,
possibly one line program should be typed in, SAVED and then VERIFIED
as described in the instruction manual.
3.3
SECTION 4
1 Introduction 4.2
Test Equipment 4.2
Modification History 4.3
Modifications - Issue 1 Board 4.4
Modifications - Issue 2 Board 4.5
32k Extension Memory - (16k-48k) 4.5
Hitachi vs NEC ROM 4.6
3 Repair 4.19
EQUIPMENT SPECIFICATION/MANUFACTURER
Oscilloscope with
O s c i l l o s c o p e probe ( x l O ) Rise Time: 0.02 us/cm
4.2
1.2 Modification History
(b) The Ferranti ULA, type 5C102, plus spider addition replaced by
ULA type 5C112.
5C102. This ULA has a timing fault which was cured by connecting
a 74LSOO 1C mounted on a miniature board and spider. This ULA
was fitted to approximately 40,000 units.
5C112. This improved ULA has no spider m o d i f i c a t i o n , but has
either a diode or resistor or transistor connected to it. The
details are:
6C001 This ULA alters the timing of the colour burst s i g n a l , and
improves the performance of the Spectrum with certain television
sets (e.g. H i t a c h i , Grundig) . It also causes the screen picture
to be shifted by one character width to the left.
4.3
Board Issue No 2 2 3
ULA Type 5C112 6C001 6C001
Component
R47 220 a Ik Ik
R49 8 k2 10 k 10 k
R56 220 n 470 fi Ik
R63 220 n 470 n Ik
(a) 100 pF capacitor between RAS and ground - necessary only when
u s i n g ULA 5C102.
(b) 470 pF capacitor between IC2, pin 28 and ground - required only
when IC2 and RAM ICs are all of NEC manufacture.
(c) 1 k resistor between RAS and 23V and 1 k resistor between CAS and
12V, only when RAM ICs are of National manufacture. R57 (330n)
must be removed, and the 470 pF capacitor is not required.
(d) 47 k resistor between pin 13 of LMI889 and ground - required only
if the difference between white and y e l l o w colours is inadequate.
(e) If disc capacitors are used for C41 and C49 (47 nF) they must be
replaced by axial components.
4.4
1.4 Modifications - Issue 2 Board
C77 ( I Q O n F ) added
C49 changed from 47nF to 560pF
R60 changed from 270fl to 68n
TR4 can be either ZTX650 or TIPP31
4.5
Board Issue 3: This allows OKI ICs to be used in p l a c e of TI 4532.
A g a i n , all ICs must be of the same designation. Appropriate links (2)
must be fitted in the grid located on the board between the edge-
connector and the ' m i c ' jack socket. A g a i n the extra memory is
obtained by p l u g g i n g in 4 logic ICs and eight memory ICs.
Clearly, if the ROM is changed for one of a different make, then these
links must be changed as w e l l .
2. FAULT DIAGNOSIS
2.1 Techniques
4.6
2.2 Power Supply Unit
2.3 Initialisation
It is possible that one of the Z80A or RAM control lines has become
faulty therefore, comparing with a known serviceable board if
p o s s i b l e , check the waveforms at the f o l l o w i n g points at origin and
destination:
Memory Check
4.8
(a) for a 48k unit - 65535
(b) for a 16k u n i t - 32767
4.9
2.5 Keyboard Structure
The keyboard is connected horizontally in eight blocks of five keys
and vertically m It
configuration. five blocksthat
follows of if
eight keys. of
any block Figure 4.1 shows
five keys the
fail the
fault is with KB2 circuitry or the 8-way membrane, and that if any
block of eight keys fail the fault is with KB1 circuitry or the 5-way
membrane. Possible keyboard faults are listed in paragraph 2.6
4.10
2.6 Fault-Finding Guide
3. Change IC1.
4. If +5V and VIDEO INPUT
correct change modulator.
2. If l o a d i n g stripes in
border are unusually
wide, check D13.
3. Check/change IC1.
4.17
TABLE 4.1. IC14 (IML889) PIN SIGNALS
2 (R - Y INPUT)
4 (B - Y INPUT)
5 0V (GROUND)
13 (CHROMA SUBCARRIER)
14 (R.F SUPPLY)
4.18
3. REPAIR
(b) Make sure there is a good contact made between the voltage
regulator body and the associated heatsink in order to ensure
adequate heat conduction. The heatsink h o l e in certain Issue 3
boards a l l o w s excessive play w h i c h could cause f o u l i n g of the
edge connector. Take care in re-assembly that the h e a t s i n k is
fitted away from the edge connector.
(g) After any component has been renewed the circuit board s h o u l d be
examined c a r e f u l l y , to ensure that there are no solder
' s p l a t t e r s ' which may cause short circuits between tracks or
connector pins.
For both the Issue 2 and the Issue 3 boards the memory upgrade is
accomplished by p l u g g i n g four logic ICs and eight memory ICs into
e x i s t i n g board sockets. Depending on the types of memory 1C used,
appropriate circuit l i n k s must be fitted on the board. Figure 4.3
shows the layout of the area of the board containing the empty
sockets. The Issue 3 board is shown which also gives positions (top
left of diagram) of the l i n k s .
4.19
4.2 Issue 2 Board
1C TYPE
IC24 74LSOO
IC25, IC26 74LS157 (NOT N a t i o n a l Semiconductors)
NOTES: (1) All external RAM ICs must be of the same type
(i.e. all -3 or -4 v a r i a n t s ) .
(2) LINK 3 on the board (IC26, pin 10) should be fitted
if IC15-IC22 are type 4532-3.
(3) L I N K 4 s h o u l d be fitted if IC15-IC22 are type 4532-4.
.3 Issue 3 Board
1C TYPE
IC23 74LS32
IC24 74LSOO
NOTES: (1) All extension RAM ICs must be of the same type.
(2) Two l i n k s must be fitted on the board (grid
located between edge connector and m/c jack
socket) depending on memory manufacturer and
type (high or low e n a b l e ) . See Figure 4.4 for
l i n k positions vs manufacturer and 1C type.
4.20
FIGURE 4.4 ISSUE 3 LINKS vs 1C MANUFACTURER AND TYPE
4.22
SECTION 5
PARTS LIST
1 Introduction 5.1
1. INTRODUCTION
1.1 Parts lists for the ZX SPECTRUM are provided in table form; one for
the case assembly (Table 5.1) and another for the board assembly
(Table 5.2). The latter covers the Issue 2 and 3 Spectrums and is
related to the board layout diagrams given in Figure 5.1 and 5.2.
T a b l e 5.2 a l s o lists the a l t e r n a t i v e components which the service
engineer w i l l o c c a s i o n a l l y f i n d on production versions of the Issue 2
board or may introduce retrospectively in order to improve
performance. These components are listed in the column headed ' I S S U E
2 MODS' with references to notes against them. These notes are
explained below-
2. NOTES TO TABLE 5.2
(1) The alternative values given for R47, R49, R56 and T63 are used
if the ULA fitted is Type 6C001.
(2) The alternative values for R48, R50, R72 and C65 are introduced
to improve the colour q u a l i t y .
(3) C74 is essential on all Issue 2 boards and s h o u l d be fitted
retrospectively. At the same time R60 must be replaced with the
larger v a l u e .
(4) The introduction of alternative components for R24 and R27 is
essential. At the same time C67 replaces D14 and R73 is added.
(5) Issue 2 boards fitted with the Type 5C112 ULA have either a
transistor (TR6) or diode/resistor m o d i f i c a t i o n (see Issue 2
circuit diagram for d e t a i l s ) .
(6) On Issue 3 boards only crystal X2 must have a close tolerance
s p e c i f i c a t i o n (i.e. 10 ppm absolute, 10 ppm 20°C to 60°C, 5 ppm
per year.)
(7) On Issue 3B boards, the d.c. converter design has improved
r e l i a b i l i t y . R60 is changed from 270n to 68ft and C49 is changed
from 47nF to 560pF. Capacitor C77 ( l O O n F ) has been added.
5.1
2.1 General Capacitor Change. Early Issue 2 units were manufactured u s i n g
a considerable number of 47 nF and 100 nF disc capacitors. Where
these occur the service engineer should take the opportunity to
replace C41 and C49 with axial types.
DESCRIPTION MANUFACTURER
Keyboard Template
Rubber Feet
D o u b l e - s i d e d adhesive tape -
12 mm wide; Tesafix 959 B.D.F. Tesa
5.2
TABLE 5.2 BOARD ASSEMBLY
CAPACITORS
( U n l e s s otherwise stated a l l c a p a c i t o r s are a x i a l types)
COIL
5.3
CONNECTORS
CRYSTALS
DIODES
INTEGRATED CIRCUITS
5.5
TRANSISTORS
MISCELLANEOUS
REG 5V r e g u l a t o r 7805
M o d u l a t o r Screen 1740
Insulator
Third/Fourth versions - grey keys, but heatsink now visible through the edge
connector slot
Plugs & Cables - use only genuine Sinclair issue or HK plugs, etc.
Modification of earplug: Connect a 330 ohm resistor between signal and earth
leads of earplug to a l l o w earplug to be left in place while saving a programme.
Tape and Sound Circuits: 5Vp-p at ear socket for 2Vp-p at IC1 verifies IC1.
Alignment: Only needed for early models. Place meter on pin 4 of IC4 and
adjust VR1 to obtain 130mV; adjust VR2 to obtain -75raV at pin 2 with a 20mV
allowable error either way. Use TC2 to set colour subcarrier frequency to
4.433619MHz to 50Hz either way. TCI only helpful to improve screen colour
pattern.
10 FOR A=0 TO 7
20 FOR B=0 TO 3
30 PAPER A: PRINT" ";
40 NEXT B
50 NEXT A
60 GOTO 10
If this shows incorrect or missing colours then align as stated for early
models. See repair data for later models.
3
REPAIR DATA
These computers are reportedly very unreliable with some 50% of new
ones alleged to have to be returned for replacement. Many faults are due to
loose or badly fitted components so that a good checkover is essential for this
reason, to determine if a factory failure first. ;
Check heatsink first for any reported fault, is it loose? Are there
overtightened screws? Look for dry joints, cracks in print or cracked boards,
badly fitted components, especially ICs; dirty or tarnished contacts, pins,
holders, edge connectors; damaged keyboard t a i l s and fins are certainly not
uncommon for whatever reason.
Before investigating any fault check any add-ons and interfaces to the
computer for broken solder, etc. caused by user wiggling them about. It is
also essential to note if add-on is loose or faulty which w i l l give a guide to
any damage so caused. This w i l l also determine if fault in add-on not
computer. Knowing what add-ons are used can be a good guide to probable fault:
for example, suspect TR4 blown and/or destroyed RAMS if a Kempton is used.
Disconnect Spectrum from recorder and with any tape playing use a long
thin-bladed screwdriver to adjust the azimuth screw through the hole normally
provided for this purpose. The object is to obtain the sharpest possible
sounding note, noting that if note is in the least muffled sounding then there
is no chance of the Spectrum loading from it.
Ifno hole is provided this should be done with the recorder cover
removed. Although it is reccomnended that volume should be set at midpoint it
is far better to vary volume setting to that at which maximum treble is
obtained. F i n a l l y give head a good clean and recheck setting.
If the adjustment does not cure the problem then save a short programme
from the computer (or use one previously saved) and if this doesn't load then
it is safe to assume that there is a fault, probably in the computer. In this
case, check connections to computer and the circuit from the edge connector to
the first I.C.
4
Early circuit showing
presets Td, TC2, VRl
and VR2 to match the
early type boards.
Ensure that all modifications have been carried out and that the edge
connector is O.K. and not loose or, damaged. Check for proper fitting of all
peripherals and verify that owner is not persistently inserting/removing any of
the add-ons, etc. while the computer is switched on. Note that many users are
apparently incapable of grasping this simple point. Check the plug/sockets and
cable, if not suitable then replace with correct ones. Check the mains and
possible interference from other items on same circuit.
7) KEYBOARD FAULTS
Check heatsink thoroughly. If heatsink is O.K. then the ULA I.C. IC1
will be the cause. If IC1 has been replaced before it may be worth adding
extra heatsink for it. See also following symptom.
9) INTERMITTENT FAULTS
A few models appeared with the SN version and these may even have been
used as replacements during repairs. Although unlikely to find now, if SN
types have been used replace completely by LH type.
;
11) POWER SUPPLY O.K. - COMPUTER NOT WORKING CORRECTLY
If computer is functioning at all check for single RAM failure then
multiple RAM failure as already described. If RAMS are O.K. or fault is more
serious and RAMS cannot be checked then check if the 5v supply is reaching all
I.C.s in order IC1, 2, 24, 23, 3, 4, 26, 25 and 5. Replace the open circuit
component cutting off the 5v supply if this is the case. ,'
Faulty or missing sound usually identifies the ULA I.C. IC1 as being
faulty and this is the most likely suspect in any case. Flick the clock
crystal with your finger, this will guickly determine if it is faulty or not.
Although I.C.s are best checked out systematically using a logic probe
or even a 'scope, it is worth noting that after IC1 the most likely culprits
are IC2 and IC5, neither of which are particularly reliable and it may even be
worth replacing the three automatically as a fast check.
//