Gopinath

Item 66/22 - Annexure - 18
Course Code Course Title L T P C

BECE204L Microprocessors and Microcontrollers 3 0 0 3
Pre-requisite BECE102L Syllabus version
1.0
Course Objectives:
1. To acquaint students with architectures of Intel microprocessors, microcontroller and
ARM processors.
2. To familiarize the students with assembly language programming in 8051
microcontroller and ARM processor.
3. To interface peripherals and I/O devices with the 8051 microcontroller.
Course Outcome:
At the end of the course, the student should be able to
1. Comprehend the various microprocessors including Intel Pentium Processors
2. Infer the architecture and Programming of Intel 8086 Microprocessor.
3. Comprehend the architectures and programming of 8051 microcontroller.
4. Deploy the implementation of various peripherals such as general purpose input/
output, timers, serial communication, LCD, keypad and ADC with 8051
microcontroller
5. Infer the architecture of ARM Processor
6. Develop the simple application using ARM processor.
Module:1 Overview of Microprocessors 3 hours

Introduction to Microprocessors, 8-bit/16-bit Microprocessor, Overview of Intel Pentium, I (i3,
i5, i7) Series Processor.
Module:2 Microprocessor Architecture and Interfacing: Intel x86 8 hours

16-bit Microprocessor: 8086 - Architecture and Addressing modes, Memory Segmentation,
Instruction Set, Assembly Language Processing, Programming with DOS and BIOS function
calls, minimum and maximum mode configuration, Programmable Peripheral Interface
(8255), Programmable Timer Controller (8254), Memory Interface to 8086.
Module:3 Microcontroller Architecture: Intel 8051 7 hours

Microcontroller 8051 - Organization and Architecture, RAM-ROM Organization, Machine
Cycle, Instruction set: Addressing modes, Data Processing - Stack, Arithmetic, Logical;
Branching – Unconditional and Conditional, Assembly programming.
Module:4 Microcontroller 8051 Peripherals 5 hours

I/O Ports, Timers-Counters, Serial Communication and Interrupts.
Module:5 I/O interfacing with Microcontroller 8051 7 hours

LCD, LED, Keypad, Analog-to-Digital Convertors, Digital-to-Analog Convertors, Sensor with
Signal Conditioning Interface.
Module:6 ARM Processor Architecture 5 hours

ARM Design Philosophy; Overview of ARM architecture; States [ARM, Thumb, Jazelle];
Registers, Modes; Conditional Execution; Pipelining; Vector Tables; Exception handling.
Module:7 ARM Instruction Set 8 hours

ARM Instruction- data processing instructions, branch instructions, load store instructions,
SWI Instruction, Loading instructions, conditional Execution, Assembly Programming.
Module:8 Contemporary issues 2 hours
Proceedings of the 66th Academic Council (16.06.2022) 396

Item 66/22 - Annexure - 18
Total Lecture hours: 45 hours

Text Book(s)
1. A.K. Ray, K.M. Bhurchandi, Advanced Microprocessor and Peripherals, 2012, 2nd
Edition, Tata McGraw-Hill, India.
2. Mohammad Ali Mazidi, Janice G. Mazidi, Rolin D. McKinlay, The 8051
Microcontroller and Embedded Systems, 2014, 2nd Edition, Pearson, India.
Reference Books
1. Muhammad Ali Mazidi, ARM Assembly Language Programming & Architecture: 1,
2016, 2nd Edition, Microdigitaled.com
2. A. Nagoor Kani, 8086 Microprocessors and its Applications, 2017, Second Edition, Tata
McGraw-Hill Education Pvt. Ltd., New Delhi, India.
3. Joseph Yiu, The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors,
2015, 2nd Edition, Elsevier Science & Technology, UK
Mode of Evaluation: Continuous Assessment Test, Digital Assignment, Quiz and Final
Assessment Test
Recommended by Board of Studies 14-05-2022
Approved by Academic Council No. 66 Date 16-06-2022
Proceedings of the 66th Academic Council (16.06.2022) 397

Interrupts in 8051
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a
device needs its service
A microcontroller can serve several devices by two ways

• Interrupts
 Whenever any device (peripheral) needs its service, the device notifies the microcontroller by
sending it an interrupt signal.
 Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and
serves the device.
• Polling
 The microcontroller continuously monitors the status of a connected device (peripheral).
 When the conditions met, it performs the service.
 After that, it moves on to monitor the next device until every one is serviced.
 Due to this, significant amount of microprocessor’s time will be wasted since the
microprocessor is visiting all the peripherals with out knowing the requirement of peripheral.
Types of Interrupts in 8051
Six interrupts are allocated in 8051, as follows;

• Reset : power-up reset
• Two interrupts for the timers: one for timer-0 overflow (TF0) and one more for timer-1
overflow (TF1).
• Two interrupts for external hardware.
Pins P3.2 and P3.3 have dual functionality for the external hardware interrupts INT0 (EX0)
and INT1 (EX1).
• Serial communication has a single interrupt that belongs to both receive (receive
interrupt (RI)) and transfer (transmit interrupt (TI)).
Enable/disable Interrupts in 8051
• Upon reset, all interrupts are disabled (masked), meaning that none will be responded to
by the microcontroller if they are invoked.
• There is a register called IE (interrupt enable) that is responsible for enabling (unmasking)
and disabling (masking) the interrupts.
• IE register is accommodated in SFR memory area.
D7 D0
EA - - ES ET1 EX1 ET0 EX0
• If EA = 1, interrupts are enabled and will be responded to, if their corresponding bits in IE
register are high;
• If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is
high.
Enable/disable Interrupts in 8051
• Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INT0 and INT1, are used as
external hardware interrupts
• There are two activation levels for the external hardware interrupts (INT0 and INT1).
Level trigged - In the level-triggered mode, INT0 and INT1 pins are normally high. So,
If a low-level signal is applied to them, it triggers the interrupt.
Edge trigged – Set IE0/IE1 bit (TCON.1/TCON.3) to enable edge triggering for
INT0/INT1
8051-Interrupt Priority Upon Reset
8051- Modifying the default Interrupt Priority
Interrupt Priority (IP) Register (Bit-addressable)
D7 D0
-- -- PT2 PS PT1 PX1 PT0 PX0
• Priority bit=1 assigns high priority

• Priority bit=0 assigns low priority
• In the 8051, a low-priority interrupt can be interrupted by a higher-priority Interrupt.

• But it prohibits the interruption of higher-priority Interrupt by using another low-priority
interrupt.
Interrupt service routine - Interrupt Vector Table
• interrupt service routines (ISR) or interrupt handler is a pre-written program which defines
the service for an interrupt request.
• Each interrupt request have its own ISR. All these ISRs will be stored in the memory and
the addresses of the starting memory locations of these ISRs will be updated in to interrupt
vector table.
• Interrupt vector table is an index of memory addresses where, the starting address of the
interrupt service routines (ISRs) are saved.
• When an interrupt request comes, microcontroller search the interrupt vector table to find
the address of the starting memory location of the required ISR.
• So that, corresponding ISR will be executed to serve the interrupt request.
Interrupt Vector Table of 8051 µC
Programming using Interrupts-Example1
Discuss what happens if interrupts INT0, TF0, and INT1 are activated at the same time.
Assume priority levels were set by the power-up reset and the external hardware interrupts
are edge triggered.
Solution:
priority levels were set by the power-up reset means default priority levels.
If these three interrupts are activated at the same time, their statuses are saved internally.
Then the 8051 checks all five interrupts according to the sequence listed in the default
priority order. If any is activated, it services it in sequence.
Therefore, when the above three interrupts are activated, INT0 (external interrupt- IE0) is
serviced first, then timer 0 (TF0), and finally INT1 (external interrupt- E1).
(a) Program the IP register to assign the highest priority to INT1(external interrupt 1), then
(b) discuss what happens if INT0, INT1, and TF0 are activated at the same time. Assume the
interrupts are edge-triggered.
Solution:
(a) MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority. The instruction SETB IP.2 also
will do the same thing as the above line since IP is bit-addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than the others; therefore,
when INT0, INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1
first, then it services INT0, then TF0.
The instruction in Step (a) makes both the INT0 and TF0 bits in the IP register 0. As a result,
the sequence in default priority order is followed which gives a higher priority to INT0 over
TF0.
Assume that after reset, the interrupt priority is set by the instruction MOV IP,#00001100B.
Discuss the sequence in which the interrupts are serviced.
Solution:
The instruction “MOV IP #00001100B” (B is for binary) assigned INT1 and timer 1 (TF1) to a
higher priority level compared with the rest of the interrupts. However, INT1 and timer 1 (TF1)
both are set, they are prioritized as per the default priority order (INT1 gets highest priority and
TF1 gets second priority). The priorities of the remaining interrupts are rearranged by
following the default priority order.
Finally, the updated priorities are as follows.
External Interrupt 1 (INT1) : Highest Priority
Timer Interrupt 1 (TF1) : Second Priority
External Interrupt 0 (INT0) : rearranged as per default.
Timer Interrupt 0 (TF0) : rearranged as per default.
Lowest Priority Serial Communication (RI+TI) : rearranged as per default.
D7 D0
Interrupt priority (IP) register: -- -- PT2 PS PT1 PX1 PT0 PX0
Write a program using interrupts to do the following:
(a) Receive data serially and sent it to P0,
(b) Have P1 port read and transmitted serially, and a copy given to P2,
(c) Make timer 0 generate a square wave of 5kHz frequency on P0.1.
Assume that XTAL-11,0592. Set the baud rate at 4800.
Solution:
ORG 0
LJMP MAIN
ORG 000BH ;ISR for timer 0
CPL P0.1 ;toggle P0.1
RETI ;return from ISR
ORG 23H
LJMP SERIAL ;jump to serial interrupt ISR
ORG 30H
MAIN: MOV P1,#0FFH ;make P1 an input port
MOV TMOD,#22H ;timer 1,mode 2(auto reload)
Programming using Interrupts-Examples4 page2
Solution:
MOV TH1,#0F6H ;4800 baud rate
MOV SCON,#50H ;8-bit, 1 stop, ren enabled
MOV TH0,#-92 ;for 5kHZ wave
MOV IE,10010010B ;enable serial int.
SETB TR1 ;start timer 1
BACK: MOV A,P1 ;read data from port 1
MOV SBUF,A ;give a copy to SBUF
MOV P2,A ;send it to P2
SJMP BACK ;stay in loop indefinitely
Programming using Interrupts-Example4 page3
Solution:
;-----------------SERIAL PORT ISR
ORG 100H
SERIAL:JB TI,TRANS ;jump if TI is high
MOV A,SBUF ;otherwise due to receive
MOV P0,A ;send serial data to P0
CLR RI ;clear RI since CPU doesn’t
TRANS: CLR TI ;clear TI since CPU doesn’t
END
Interrupt Vector Table for the 8051
Solution:
We will use Timer 0 in mode 2 (auto-reload). TH0 = 100/1.085 ms = 92.
;—-Upon wake-up go to main, avoid using memory space ;allocated to Interrupt

Write a program that Vector Table
ORG 0000H
continuously gets 8-bit ;
LJMP MAIN ;bypass interrupt vector table
data from P0 and ;—-ISR for Timer 0 to generate square wave

ORG 000BH ;Timer 0 interrupt vector table
sends it to P1 while CPL P2.1 ;toggle P2.1 pin
simultaneously ;
creating a square ;—-The main program for initialization

ORG 0030H ;after vector table space
wave of 200 ms period MAIN: MOV TMOD,#02H ;Timer 0, mode 2(auto-reload)
MOV P0,#0FFH ;make P0 an input port
on pin P2.1. MOV TH0,#-92 ;TH0=A4H for -92
MOV IE,#82H ;IE=10000010(bin) enable Timer 0
SETB TR0 ;Start Timer 0
Use Timer 0 to create BACK: MOV
MOV
A,P0
P1,A
;get data from P0
;issue it to P1
the square wave. SJMP BACK ;keep doing it
;loop unless interrupted by TF0
Assume that END
XTAL = 11.0592 MHz.

Since 1085 µs is 1000 x 1.085 we need to use mode 1 of
Solution: Timer 1.
;--Upon wake-up go to main, avoid using memory space
;--allocated to Interrupt Vector Table
ORG 0000H
;
;--ISR for Timer 1 to generate square wave
Write a program that ORG 001BH ;Timer 1 interrupt vector table
LJMP ISR_T1 ;jump to ISR
continuously gets 8-bit data ;
from P0 and sends it to P1 ;--The main program for initialization
ORG 0030H ;after vector table
while simultaneously creating MAIN: MOV TMOD,#10H ;Timer 1, mode 1
MOV P0,#0FFH ;make P0 an input port
a square wave that has a high MOV TL1,#018H ;TL1=18 the Low byte of -1000
portion of 1085 µs and a low MOV
MOV
TH1,#0FCH
IE,#88H
;TH1=FC the High byte of -1000
;IE=10001000 enable Timer 1 int.
portion of 15 µs. SETB TR1 ;start Timer 1
BACK: MOV A,P0 ;get data from P0
MOV P1,A ;issue it to P1
SJMP BACK ;keep doing it
Assume XTAL = 11.0592 MHz. ;
Use Timer 1. ;--Timer 1 ISR. Must be reloaded since not auto-reload
ISR_T1: CLR TR1 ;stop Timer 1
CLR P2.1 ;P2.1=0, start of low portion
MOV R2,#4 ; 2 MC
HERE: DJNZ R2,HERE ;4x2 machine cycle(MC) 8 MC
MOV TL1,#18H ;load T1 Low byte value 2 MC
MOV TH1,#0FCH ;load T1 High byte value 2 MC
SETB TR1 ;starts Timer 1 1 MC
SETB P2.1 ;P2.1=1, back to high 1 MC
RETI ;return to main
END
Write a program to generate a square wave of 50 Hz frequency on pin P1.2. It uses an interrupt for Timer 0.
Assume that XTAL = 11.0592 MHz.
ORG 0
LJMP MAIN
ORG 000BH ;ISR for Timer 0
CPL P1.2 ;complement P1.2
MOV TL0,#00 ;reload timer values
MOV TH0,#0DCH
RETI ;return from interrupt
ORG 30H ;starting location for prog.

;------main program for initialization
MAIN: MOV TMOD,#00000001B ;Timer 0, Mode 1
MOV TL0,#00
MOV TH0,#0DCH
MOV IE,#82H ;enable Timer 0 interrupt
SETB TR0 ;start timer
HERE: SJMP HERE ;stay here until interrupted
END
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on
an LED. The LED is connected to P1.3 and is normally off. When it is turned on it should stay on for a fraction of a
second. As long as the switch is pressed low, the LED should stay on.
ORG 0000H
;--ISR for hardware interrupt INT1 to turn on the LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on LED
MOV R3,#255 ;load counter
BACK: DJNZ R3,BACK ;keep LED on for a while Pressing the switch will
CLR P1.3 ;turn off the LED turn the LED on. If it
RETI ;return from ISR is kept activated, the
;--MAIN program for initialization LED stays on.
ORG 30H
MAIN: MOV IE,#10000100B ;enable external INT1
END
Minimum Duration of the Low Level-Triggered Interrupt (XTAL = 11.0592 MHz)
Note: On RESET, IT0 (TCON.0) and IT1 (TCON.2) are both low, making
external interrupts level-triggered.
TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1 overflows.
Cleared by hardware as the processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 on/off.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware when timer/counter 0 overflows.
Cleared by hardware as the processor vectors to the service routine.
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the external interrupt edge
TCON (Timer/Counter) (H-to-L transition) is detected.
Register (Bit-addressable) Cleared by CPU when the interrupt is processed.
Note: This flag does not latch low-level triggered interrupts.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to

specify falling edge/low-level triggered external interrupt.
IE0 TCON.1 External interrupt 0 edge flag. Set by CPU when external interrupt
(H-to-L transition) edge is detected. Cleared by CPU when interrupt is processed.
Note: This flag does not latch low-level triggered interrupts.
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling
edge/low-level triggered external interrupt.
Assuming that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the falling edge of the pulse will
send a high to P1.3, which is connected to an LED (or buzzer). In other words, the LED is turned on and off at the same rate
as the pulses are applied to the INT1 pin. This is an edge-triggered version of Example 11-5.
ORG 0000H
LJMP MAIN
;--ISR for hardware interrupt INT1 to turn on the LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on the LED
MOV R3,#255
BACK: DJNZ R3,BACK ;keep the LED on for a while
CLR P1.3 ;turn off the LED
;--MAIN program for initialization
ORG 30H
MAIN: SETB TCON.2 ;make INT1 edge-trigger interrupt
MOV IE,#10000100B ;enable External INT1
END
Minimum Pulse Duration to Detect Edge-triggered Interrupts. XTAL = 11.0592 MHz
What is the difference between the RET and RETI instructions? Explain why we cannot use RET
instead of RETI as the last instruction of an ISR.
Both perform the same actions of popping off the top two bytes of the stack into
the program counter, and making the 8051 return to where it left off. However,
RETI also performs an additional task of clearing the interrupt-in-service flag,
indicating that the servicing of the interrupt is over and the 8051 now can accept
a new interrupt on that pin. If you use RET instead of RETI as the last instruction
of the interrupt service routine, you simply block any new interrupt on that pin
after the first interrupt, since the pin status would indicate that the interrupt is
still being serviced. In the cases of TF0, TF1, TCON.1, and TCON.3, they are
cleared by the execution of RETI.
Single Interrupt for Both TI and RI
Write a program in which the 8051 reads data from P1 and writes it to P2 continuously while giving a
copy of it to the serial COM port to be transferred serially.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.
Solution:
ORG 0
LJMP MAIN
ORG 23H
LJMP SERIAL ;jump to serial interrupt ISR
ORG 30H
MOV TMOD,#20H ;timer 1, mode 2(auto-reload)
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8-bit, 1 stop, REN enabled
MOV IE,#10010000B ;enable serial interrupt
;
;------------------Serial Port ISR
ORG 100H
SERIAL: JB TI,TRANS ;jump if TI is high
CLR RI ;clear RI since CPU does not
TRANS: CLR TI ;clear TI since CPU does not
END
In the above program notice the role of TI and RI. The moment a byte is written into SBUF it is framed
and transferred serially. As a result, when the last bit (stop bit) is transferred the TI is raised,
which causes the serial interrupt to be invoked since the corresponding bit in the IE register is high.
In the serial ISR, we check for both TI and RI since both could have invoked the interrupt. In other
words, there is only one interrupt for both transmit and receive.
Write a program in which the 8051 gets data from P1 and sends it
to P2 continuously while incoming data from the serial port is sent to P0.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.
Solution:
ORG 0
LJMP MAIN
ORG 23H
LJMP SERIAL ;jump to serial ISR
ORG 30H
MOV TMOD,#20H ;timer 1, mode 2(auto-reload)
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8-bit,1 stop, REN enabled
MOV IE,#10010000B ;enable serial interrupt
SETB TR1 ;start Timer 1
;------------------SERIAL PORT ISR
ORG 100H
MOV P0,A ;send incoming data to P0
CLR RI ;clear RI since CPU doesn’t
TRANS: CLR TI ;clear TI since CPU doesn’t
END
Interrupt Flag Bits for the 8051/52
Write a program using interrupts to do the following: (a) Receive data serially and send it to P0, (b)
Have port P1 read and transmitted serially, and a copy given to P2, (c) Make Timer 0 generate a square
wave of 5 kHz frequency on P0.1. Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.
ORG 0
LJMP MAIN
ORG 000BH ;ISR for Timer 0
CPL P0.1 ;toggle P0.1
ORG 23H
LJMP SERIAL ;jump to serial int. ISR
ORG 30H
MOV TMOD,#22H ;timer 0&1,mode 2, auto-reload
MOV TH1,#0F6H ;4800 baud rate
MOV TH0,#-92 ;for 5 KHz wave
MOV IE,#10010010B ;enable serial, timer 0 int.
MOV P2,A ;write it to P2
;------------------SERIAL PORT ISR
ORG 100H
MOV A,SBUF ;otherwise due to received
MOV P0,A ;send serial data to P0
CLR RI ;clear RI since CPU does not
TRANS: CLR TI ;clear TI since CPU does not
END
LED INTERFACING
Interfacing comprises of hardware (Interface device) and Software
(source code to communicate, also called as the Driver).
Simply, to use an LED as the output device, LED should be connected to
Microcontroller port and the MC has to be programmed inside make
LED ON or OFF or blink.
Light Emitting Diodes or LEDs are the mostly commonly used
components in many applications, mostly used for signal transmission
/power indication purposes.
It is very cheaply and easily available in a variety of shape, color, and
size.
The LEDs are also used for design message display boards and traffic
control signal lights etc.
It has two terminals positive and negative as shown in the figure.
Observe carefully the interface LED interface 2 is in forward biased
because the input voltage of 5v connected to the positive terminal of the
LED, So here the Microcontroller pin should be at LOW level and vice
versa with the LED interface 1 connections.
LED INTERFACING WITH 8051
PROGRAM FOR BLINKING OF LEDS
ORG 00H ; Assembly Starts from 0000H.
START: MOV P1, #0FFH ; Move 11111111 to PORT1.
ACALL WAIT ; Call WAIT
MOV A, P1 ; Move P1 value to ACC
CPL A ; Complement ACC
MOV P1, A ; Move ACC value to P1
ACALL WAIT ; Call WAIT
SJMP START ; Jump to START
WAIT: MOV R2, #10 ; Load Register R2 with 10 (0x0A)
WAIT1: MOV R3, #200 ; Load Register R3 with 10 (0xC8)
WAIT2: MOV R4, #200 ; Load Register R4 with 10 (0xC8)
WAIT3: DJNZ R4, WAIT3 ; Decrement R4 till it is 0. Stay there if not 0.
DJNZ R3, WAIT2 ; Decrement R3 till it is 0. Jump to WAIT2 if not 0.
DJNZ R2, WAIT1 ; Decrement R2 till it is 0. Jump to WAIT1 if not 0.
RET ; Return to Main Program
END ; End Assembly
SEVEN SEGMENT DISPLAY
7 segment LED display is very popular and it can display digits
from 0 to 9 and quite a few characters like A, b, C, ., H, E, e, F, n,
o, t, u, y, etc.
A seven segment display consists of seven LEDs arranged in the
form of a squarish 8 slightly inclined to the right and a single
LED as the dot character.
Different characters can be displayed by selectively glowing the
required LED segments.
Seven segment displays are of two types, common cathode and
common anode.
In common cathode type, the cathode of all LEDs are tied
together to a single terminal which is usually labeled as .
In common anode type, the anode of all LEDs are tied together
as a single terminal and cathodes are left alone as individual pins.
SEVEN SEGMENT DISPLAY INTERFACING
Since these are basically LEDs arranged as a group they can

either have the anode in common or cathode thus they are
named as Common-Anode/Common-Cathode displays.
Common Cathode: In this type of segments all the cathode

terminals are made common and tied to GND. Thus the
segments a to g needs a logic High signal(5v) in order to
glow.
Common Anode: In this type of segments all the anodes

terminals are made common and tied to VCC(5v). Thus the
segments a to g needs a logic LOW signal(GND) in order to
glow.
Assembly language program to interface seven segment display (0-9) when it
connected to port1
ORG 0000H
MAIN: MOV DPTR, #400H
REPEAT: CLR A
MOVC A, @A+DPTR ; Copy data from external location to accumulator
MOV P1, A ; Move the pattern of the digit into port P1
ACALL DELAY ; Call a delay to so that the transition is visible
INC DPTR ; Point to the next pattern
CJNE A, 0, REPEAT ; Repeat till 0 (Stop bit) is received
SJMP MAIN ; Run this forever till externally stopped
DELAY:
MOV R0, #08H
LP2: MOV R1, #0FFH
LP1: MOV R2, #0FFH
LP3: DJNZ R2, LP3
DJNZ R1, LP1
DJNZ R0, LP2
RET
ORG 400H
DB 3FH, 06H, 5BH, 4FH, 66H, 6DH, 7DH, 07H, 7FH, 6FH, ; Lookup table for digits 0 to 9
END
Write a program to display
by using seven
segment display while it is
connected to port 0 of 8051.
ORG 0000H
MAIN: MOV DPTR, #200H
MOV R0,#05H
REPEAT: CLR A
MOVC A, @A+DPTR ; Copy data from external location to accumulator
MOV P0, A ; Move the pattern of the digit into port 0
ACALL DELAY ; Call a delay to so that the transition is visible
INC DPTR ; Point to the next pattern
DJNZ R0, REPEAT ; Repeat till R0 = 0
SJMP MAIN ; Run this forever till externally stopped
DELAY:
MOV R0, #08H
LP2: MOV R1, #0FFH
LP1: MOV R2, #0FFH
LP3: DJNZ R2, LP3
DJNZ R1, LP1
DJNZ R0, LP2
RET
ORG 200H
DB 76H, 79H, 38H, 38H, 3FH ; Lookup table for alphabets
LCD INTERFACING
LCD is finding widespread use replacing LEDs
The declining prices of LCD
The ability to display numbers, characters, and graphics
Incorporation of a refreshing controller into the LCD,
thereby relieving the CPU of the task of refreshing the
LCD
Ease of programming for characters and graphics.
6x2 LCD is one of the most used display unit.
16x2 LCD means that there are two rows in which 16
characters can be displayed per line, and each character
takes 5X7 matrix space on LCD.
Pin Descriptions for LCD
used by the
LCD to latch
information
-Send displayed
presented to
information or
its data bus
instruction
command codes
to the LCD
-Read the
contents of the
internal
registers
LCD Command
Codes
+5V
8051 VCC
P1.0 D0
VEE 10k
POT
LCD
P1.7 D7 VSS
RS R/W E
P2.0
P2.1
P2.2
16 x 2 LCD 80 81 82 83 84 85 86 through 8F
C0 C1 C2 C3 C4 C5 C6 through CF
LCD INTERFACING
Sending Data/ Commands to LCDs w/ Time Delay
To send any of the commands to the LCD, make pin RS=0. For data, make RS=1. Then send a
high-to-low pulse to the E pin to enable the internal latch of the LCD. This is shown in the code
below.
;calls a time delay before sending next data/command
;P1.0-P1.7 are connected to LCD data pins D0-D7
;P2.0 is connected to RS pin of LCD
;P2.1 is connected to R/W pin of LCD
;P2.2 is connected to E pin of LCD
ORG 0H
MOV A,#38H ;INIT. LCD 2 LINES, 5X7 MATRIX
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#0EH ;display on, cursor blinking
MOV A,#01H ;clear LCD
MOV A,#06H ;shift cursor right
MOV A,#84H ;cursor at line 1, pos. 4
;display letter N
ACALL DATAWRT ;call display subroutine
;display letter O
ACALL DATAWRT ;call display subroutine
AGAIN: SJMP AGAIN ;stay here
COMNWRT: ;send command to LCD
MOV P1,A ;copy reg A to port 1
CLR P2.0 ;RS=0 for command
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse ;it must be 450ns wide
CLR P2.2 ;E=0 for H-to-L pulse
RET
DATAWRT: ;write data to LCD
MOV P1,A ;copy reg A to port 1
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse ;it must be 450ns wide
CLR P2.2 ;E=0 for H-to-L pulse
RET
DELAY: MOV R3,#50 ;50 or higher for fast CPUs
HERE2: MOV R4,#255 ;R4 = 255
HERE: DJNZ R4,HERE ;stay until R4 becomes 0
DJNZ R3,HERE2
RET
END
;Check busy flag before sending data, command to LCD
;p1=data pin
;P2.0 connected to RS pin
;P2.1 connected to R/W pin
;P2.2 connected to E pin
ORG 0H
MOV A,#38H ;init. LCD 2 lines ,5x7 matrix
ACALL COMMAND ;issue command
MOV A,#0EH ;LCD on, cursor on
MOV A,#01H ;clear LCD command
MOV A,#06H ;shift cursor right
MOV A,#84H ;cursor: line 1, pos. 6
ACALL COMMAND ;command subroutine
MOV ;display letter N
ACALL DATA_DISPLAY
MOV ;display letter O
ACALL DATA_DISPLAY
HERE:SJMP HERE ;STAY HERE
.....
.....
COMMAND:
ACALL READY ;is LCD ready?
MOV P1,A ;issue command code
CLR P2.0 ;RS=0 for command
CLR P2.1 ;R/W=0 to write to LCD
SETB P2.2 ;E=1 for H-to-L pulse
CLR P2.2 ;E=0,latch in
RET
DATA_DISPLAY:
ACALL READY ;is LCD ready?
MOV P1,A ;issue data
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W =0 to write to LCD
SETB P2.2 ;E=1 for H-to-L pulse
CLR P2.2 ;E=0,latch in
RET To read the command register, we make
READY: R/W=1, RS=0, and a H-to-L pulse for the E pin.
SETB P1.7 ;make P1.7 input port
CLR P2.0 ;RS=0 access command reg
SETB P2.1 ;R/W=1 read command reg
;read command reg and check busy flag
BACK:SETB P2.2 ;E=1 for H-to-L pulse
CLR P2.2 ;E=0 H-to-L pulse
JB P1.7,BACK ;stay until busy flag=0
RET If bit 7 (busy flag) is high, the LCD is
END
busy and no information should be issued
to it.
Keyboard Interfacing
❑ Keyboards are organized in a matrix of rows and
columns
➢ The CPU accesses both rows and columns through ports
KEYBOARD
▪ Therefore, with two 8-bit ports, an 8 x 8 matrix of keys can be
INTERFACING connected to a microprocessor
➢ When a key is pressed, a row and a column make a contact
▪ Otherwise, there is no connection between rows and columns
KEYBOARD ❑ It is the function of the microcontroller to scan the keyboard
INTERFACING continuously to detect and identify the key pressed
Grounding ❑ To detect a pressed key, the microcontroller grounds all rows by
Rows and providing 0 to the output latch, then it reads the columns
Reading
➢ If the data read from columns is D3 – D0 = 1111, no key has
Columns
been pressed and the process continues till key press is
detected
➢ If one of the column bits has a zero, this means that a key press
has occurred
▪ For example, if D3 – D0 = 1101, this means that a key in
the D1 column has been pressed
▪ After detecting a key press, microcontroller will go through
the process of identifying the key
❑ Starting with the top row, the microcontroller grounds it by
KEYBOARD
providing a low to row D0 only
INTERFACING
➢ It reads the columns, if the data read is all 1s, no key in that row is
activated and the process is moved to the next row
Grounding
Rows and
❑ It grounds the next row, reads the columns, and
Reading checks for any zero
Columns
(cont’) ➢ This process continues until the row is identified
❑ After identification of the row in which the key has
been pressed
➢ Find out which column the pressed key belongs to
Contents
• ADC
• DAC
DAC Interfacing
D/A Converter Circuits
• Binary-weighted registers
b1b2 ...bN
VREF V V
iO  b1  REF b2  ...  NREF
1
bN
R 2R 2 R vO  iO R f
Example:
In order to generate a stair-step ramp, set up the circuit in Figure 13-18 and
connect the output to an oscilloscope. Then write a program to send data to the
DAC to generate a stair-step ramp.
Solution:
CLR A
AGAIN: MOV P1,A ;send data to DAC
INC A ;count from 0 to FFH
ACALL DELAY ;let DAC recover
SJMP AGAIN
Table: Angle vs. Voltage Magnitude for Sine Wave
Example 13-5
Verify the values given for the following angles: (a) 30° (b) 60°.
Solution:
(a) Vout = 5 V + (5 V x sin q) = 5 V + 5 x sin 30° = 5 V + 5 x 0.5 = 7.5 V

DAC input values = 7.5 V x 25.6 = 192 (decimal)
(b) Vout = 5 V + (5 V x sin q) = 5 V + 5 x sin 60° = 5 V + 5 x 0.866 = 9.33 V

DAC input values = 9.33 V x 25.6 = 238 (decimal)
Figure: Angle vs. Voltage Magnitude for Sine Wave
Thank You
ARM INSTRUCTION SET : Data processing instructions,
branch instructions, load store instructions, SWI Instruction,
Loading instructions, conditional Execution, Assembly
Programming.
Introduction
ARM has got set of the instructions for ARM state and THUMB state.
ARM Instruction set is broadly divided into 7 categories. They are :
 Data processing instructions
 Conditional instructions
 Load and Store instructions
 Multiply instructions
 Software interrupt instructions
 Branch instructions
 Barrel shifting operation
All ARM state instructions are 32 bit wide.
All instructions will need 3 operands.
Most of the instructions could be executed in one cycle.
Data Processing Instructions
The data processing instructions are comprised of arithmetic, logical, comparison as well as data
movement instructions.
Opcode Mnemonic Operation performed Brief Interpretation
0000 AND Rd=RN and OP2 Logical bitwise AND operation.
0001 EOR Rd = RN XOR OP2 Logical bitwise EXOR operation.
0010 SUB Rd = RN-OP2 Subtract
0011 RSB Rd=OP2-RN Reverse subtraction
0100 ADD Rd=RN+OP2 Addition

Cont.
Opcode Mnemonic Operation Performed Brief Interpretation
0101 ADC Rd = RN+OP2+C Addition with carry
0110 SBC Rd = RN-OP2+C-1 Subtract with carry (borrow)
0111 RSC Rd = OP2 – RN +C – 1 Reverse subtraction with carry(borrow)
1000 TST SCC RN AND OP2 Test operation
1001 TEQ SEC RN EXOR OP2 Test for equivalence
1010 CMP SEC RN – OP2 Compare the two operands
1011 CMN SEC RN + OP2 Negate compare of the operands
1100 ORR Rd = RN OR OP2 Bitwise logical OR
1101 MOV Rd = OP2 Move operation
1110 BIC Rd = RN NAND OP2 Clear the bit in perspective
1111 MVN Rd = NOT OP2 Bitwise logical NOT operation performed and result placed in Rd
Arithmetic Instructions
Instruction Description
ADD • It is meant for adding two operands and result will be sent to third operand specified as Rd.
• Instruction format is ADD operand1 + operand2.
• This is a 32 bit addition operation instruction.
• ADD r0,r1,r2;//instruction for adding two 32 bit numbers where r1 and r2 will have the operands to be
added and the result will be moved to the destination register r0. r0 seen as Rd here.
• ADD R0,R0, #1 increments R0 by 1, where #represents immediate addressing mode.
ADC • Add with carry operation can be performed with ADC. ADC operand1+operand2+carry;//instruction for
adding two operands with the carry.
SUB • To subtract two operands, one can use this instruction. sub r0,r0,r1;//subtract r1 from r0 and storing the
result in r0.
• The subtraction is a 32 bit signed operation.
SBC Subtract with borrow. SBC operand1 – operand2+carry-1;//Instruction used to subtract with borrow.
RSB This instruction performs subtraction without carry, but reverses the order in which its operands are
subtracted. The instruction : RSB <dest>,<lhs>,<rhs> will do <dest> = <rhs> - <lhs>
RSC This is “with carry version of RSB”.
Logical Operations
AND This instruction performs bitwise logical AND operation as per AND table. Bit 0 of the operand1 is
ANDed with bit 0 of operand2 and stored in bit 0 of the destination register. AND R0,R0,R5
EOR This is exclusive OR operation. Ex-OR table is followed to make the bitwise 32 bit operation. Ex:
EOR R0,R0,#1;
ORR This will perform bitwise OR operation. Ex: ORR R0,R0,R1
BIC This is bit clearing operation. This instruction is meant for getting the NOT of RHS (second
operand) and with that result AND with first operand.
Comparison operations
CMP Compare instruction and the operation of the comparison is carried out by subtracting the two
operands. It does not store the result anywhere, in stead status bits will be set accordingly
based on result of the operation. Ex: CMP R0,R1; Get greater of R1, R0 in R0.
CMN Same as previous. But there will be a negation operation of the second operand (rhs) before
the comparison is being performed. Ex: CMN R1,#1; compare R1 with -1.
TST It is used to perform operand1 AND operand2. It was very similar to logical ANDing.
TEQ It is used to perform Ex-OR operation on the two operands. TEQ <lhs>,<rhs>. One important
use of TEQ is to test if two operands are equal, that too without affecting the state of the C flag
as CMP could do. After such an operation, Z = 1 if operands are equal, or 0 if not.
Ex: TEQ R0,#0; See if R0 = 0
Data Movement Operations
This is the last set of instructions which fall under data processing instructions.
MOV and MOVS Move instruction moves data from the source to destination. The syntax will be: MOV
<dest>, <source> ; MOV r0, r1; Put R1 into R0
MOVS instruction operate with flags. MOVS r0,r1; Put R1 into R0, setting the flags
MVN MVN instruction moves the logically NOTed value of its operand <RHS> to the register
specified by <dest>
MVN <dest>,<Operand>
MVNS R0,R0; Invert all bits of R0, setting flags.
Conditional Execution
All ARM instructions have the ability of conditional execution.
OPCODE MNEMONIC OPERATION PERFORMED BRIEF INTERPRETATION

0000 EQ Z is set Equal to condition is checked.
0001 NE Z is cleared Not equal condition is checked
0010 CS/HS C is set Carry bit is set/Unsigned greater than equal to
condition is checked
0011 CC/LO C is cleared Carry bit is cleared/Lesser than condition is tested.
0100 MI N is set Signed negative condition is checked

0101 PL N is cleared Signed positive or zero condition is evaluated
0110 VS V is set Occurrence of overflow is checked

0111 VC V is cleared Non-occurrence of overflow is checked
Cont.
OPCODE Mnemonic Operation Performed Brief Interpretation
1000 HI C is set & Z is cleared Unsigned greater than condition
1001 LS C is cleared or Z is set Unsigned less than or equal condition
1010 GE N equals V Signed greater than or equal condition
1011 LT N is not V Signed less than condition
1100 GT Z is cleared & N equals V Signed greater than
1101 LE Z is set & N not V Signed less than
1110 AL Unconditional checking (Occurs always)
1111 NV No change Never occurs

Cont.
When programmer wishes to execute an instruction conditionally, post fixing the instruction
with appropriate condition code would do.
Ex: ADD r0,r1,r2; r0 = r1+r2 will be performed and result will be stored in r0.
To include simple condition as the instruction should execute if at all zero flag is set, then the
instruction can be written as:
 ADDEQ r0,r1,r2; if zero flag is set then add.
By default data processing operations do not affect the condition flags (apart from
comparisons).
To get the conditional flags hit and affected, the S bit of the instruction needs to be set by post
fixing the instruction.
Ex: ADDS r0,r1,r2; MOVS r0,r1
LOAD & STORE Instructions
Load and store instructions are meant for data transfer from memory to registers and vice versa.
There are 3 major classes of load and store instructions:
 Single register data transfer and for this purpose ARM provides LDR/STR
 Block data transfer and LDM/STM are used for accomplishing block data transfer
 Single data swap can be performed by SWP instruction.
STR and STRB • Decide what operation has to be done. Whether to read the data from the memory or storing the
data into the memory.
• STR is meant for storing the data into memory. When someone wishes to store the data onto the
memory , the location where the data has to be stored needs to be specified. One can quote the
address in 2 ways:
• Pre-indexed addressing
• Post indexed addressing
Cont.
Pre-indexed Addressing
Syntax for pre-indexed addressing was:
• STR(cond.) <source>, [<base> {,<offset_value>}]
• Here, <source> is the source which holds the data to be transferred.
• <base> is the register which contains the base address of the memory location required for storage.
• <offset> is a field which is not mandatory. If it is used, then address where data has to be put =
<base>+<offset>
• Ex: STR R0, [R1,#25] - This operation will store the data available in R0 to the address obtained by adding
the base address specified by R1 + 25. Offset need not be positive always.
• STR R0, [R1,#-25] which stores R0 at R1 – 25.
• STR will help in getting the storage operations for words where STRB can be used for performing operation
based on bytes.
Cont.
Post-indexed addressing:
Here offset would not be added to the base address until the instruction has been executed.
STR {cond.} <srce>, [<base>], <offset>
LDR This instruction is helpful in loading. The syntax can be:

LDR <dest.>, <expression> where <expression> yields an address.
• Here PC will be used as the base register.
• If the address will not fall in right range, there will be an error message. The range is -4095
to +4095.
Multiplication Instructions
There are two basic instructions supported in ARM for multiplication. They are MUL and MLA.
MUL The syntax of MUL is:

MUL <dest, <lhs>,<rhs> which can be framed as MUL R0, R1, R2; Here R0 is the destination register where
the result of operation would be stored and R1 and R2 are the operands to the multiplicand.
No immediate addressing mode is supported in ARM multiplication instruction MUL.
MLA It is expanded as multiply accumulate. The syntax can be
MLA <dest>,<lhs>,<rhs>,<add> which can be framed as MLA R0,R1,R2,R10;
Where R0 will have the end result. R1 and R2 are the operands to be multiplied and before storing the
result, the ADD register’s value will be added with the product obtained and then it will be stored in
destination register.
Software Interrupt Instructions
It is a simple and most important instruction in ARM processor. There is only one instruction in
this category called “SWI”.
When SWI is run, the CPU will immediately enter the supervisor mode and will save the return
address in R14_SVC.
From the time supervisor mode is entered, OS will be taking over and set of operations
requested by the USER mode will be performed
Branching Instructions
There are two kinds of branching instruction supported in ARM core.
They are normal branching and branching with link.
B It is a simple branching operation where the instruction just a single letter ‘B’. The syntax is:
B <expression> <expression> specified the address within the program to which the control has to be
transferred. Normally labels will be used for this purpose and same would be defined somewhere else in the
code.
B loop: branching to loop and the same can be defined somewhere in the code. .Loop ADD R1, R2, R3
BL • B is having one more variant of its kind. It is nothing but BL which is expanded as Branch with Link. The
instruction has to perform a link operation before the branching has to be performed.
• Current value of the R15 register should be stored in R14 and the branching action can be taken. The
address that ARM core saves in R14 is the address of the instruction that immediately follows the BL.
• After returning from subroutine the content of R14 back to R15 would do the task. MOVS R15, R14. Since ‘S’
is included, the flags will be restored automatically.
• The Syntax of BL: BL <expression>
Barrel Shifting Operation
ARM has no support for the shift instructions. Barrel shifter is used supporting the shifting
operations.
LSL LSL is expanded as Logical Shift left Immediate. It takes the number of bits to be shifted as the
argument. The syntax is:
LSL #n where, n is the number of bits by which the value is shifted. After n shifts, n bits have
been shifted in on the left side and the carry bit is set to bit 32-n.
X b31 b0
This is before shifting.
b31 b30 b0 0
This was post execution for LSL #1. If the instruction is MOV r3, r4, LSL #2. Assume r3 = 5 and
r4 = 8. This instruction is executed : r3 = r4 * 2^2. Since the value 2 is specified in the LSL it has
been taken as 2 ^2. Similarly if it is LSL #n it will be taken as 2^n.
Cont.
LSR Its logical shift right.

b31 b0 X
0 b31 b1 b0
This is post LSR.

Cont.
ROR Rotate right is the expansion of ROR.
B31 B0 Pre ROR
X
Post ROR #1
B0 b31 b1 b0
There is no instruction called ROL.
RRX Rotate right Extended. This is a unique instruction and there is no need for specifying the
count.
B31 B0 X
X b31 b1 b0
Stack in ARM
They are LDM and STM. They can be related to PUSH and POP of 8086 processor. LDM and STM are used for
the purpose of storing and retrieving actions.
We know, stack is a memory area which can grow on addition of data to it and will shrink when data popped
out of it.
It works in the principle of LIFO.
When an item is getting added to the stack, SP will point to the new item that has been added.
Once one item is moved out of the stack, SP will point to the previous item itself.
Before PUSHing and POPing two things must be remembered.
 When user try to add the item to the stack, it should not be full.
 There should be enough space for holding the new entrant.
 When POPing, there should be enough data to be popped out i.e. one can’t POP out of empty stack.
Cont.
STM: STM is the instructions which help in pushing items onto the stack.
The syntax of the instruction: STM <type><base>{!}, <registers>
<type> can be one of the four letters which serves as a mark of stack being full or empty with F or E. Similarly
ascending or descending mode of the stack is specified by A or D.
<BASE> register is nothing but the stack pointer.
! Option is also present in the syntax and it will cause the write back.
<registers> will specify the registers which have to be pushed onto stack.
Ex: STMED r13! {r1,r2,r5}
R1,R2 and R5 will be saved and R13 will serve as the SP. E is specified as stack empty.
Ex: STMFD R13,{R1-R15}. Here STM will store all the registers from R1 to R15, without affecting the register
R13.
Some ARM Programs
1. Addition of two numbers using ARM instruction set

AREA RESET, CODE, READONLY
;AREA is a directive which helps in specifying the region where the code has to be stored.
ENTRY
MOV R0,#0x1 ;Loading Register R0 with 0x1;
MOV R1, #0xA ;Loading Register R1 with 0xA;
ADD R3,R0,R1 ;Adding them together to get the result stored in R3
B. ;Looping. BL can also be used in place of B.
END
Cont.
1. Write a program to SWAP two numbers with ARM state instruction set.
ENTRY
MOV R0,#0x3 ;First value is moved to R0
MOV R1, #0x0A ; Second value is moved to R1
MOV R2, #0 ;Keeping the third register, swapping is initiated.
MOV R2, R0 ;Copying the content of R0 to third register R2.
MOV R0, R1 ; So now, R1 can be moved to R0.
MOV R1, R2 ; Restore R0’s default value in R1. Swapping is done.
B. ;Looping. BL can also be used.
END
Cont.
1. Write a program to get one’s complement of a value.
AREA RESET,CODE,READONLY
ENTRY
MOV R0,#0x0 ;Value to be complemented
MVN R0,R0 ;MVN will invert the value and will store the result in R0
B. ;Looping. BL can also be used.
END
Cont.
1. Write a program to get two’s complement of a value.
ENTRY
MOV R0,#0x1 ; Value to be complemented
MVN R0,R0 ;Invert the value and store it in R0
ADD R1,R0,#1 ;Adding for finding 2’s complement.
B.
END
Cont.
1. Write a program to find greatest of 2 nos.
ENTRY
MOV R0,#0x1 ;Moving the first value
MOV R1,#0x2 ; Moving the second value to be compared with first one.
CMP R0,R1 ;Comparing, the result was not stored somewhere, in stead CPSR can
be analyzed. Here the N flag will be set as R0 value is smaller than R1.
B.
END
THUMB STATE IN ARM CORE
ARM core has two execution states ARM and THUMB.
It switches between states using BX instruction. THUMB is a compressed and 16 bit
representation of a subset of the ARM instruction set.
Many complex functions require multiple instruction in RISC, in this scenario thumb is used to
reduce the memory cost of extra instructions.
It also increases the performance from narrow memory and optimizes code density.
Like ARM, Thumb also uses load store architecture for data processing, data transfer and control
flow instructions.
The standard chip that includes the Thumb instruction set is the ARM7TDMI where ‘T’ specifies
the Thumb.
Thumb vs ARM
Thumb ARM
Most Thumb instructions are unconditionally All ARM instructions are conditionally executed.
executed
Employs 2 address format Employs 3 addresses format
It has explicit shift codes Implements shifts as operand modifiers
Thumb instruction formats are less regular due to Regular
dense coding
Thumb Accessible Registers
All the registers in Thumb are not directly accessible.
Low register r0 – r7: Completely accessible
High registers r8 – r12: Accessible only with MOV,ADD,CMP; only CMP sets the condition code
flags.
SP (Stack pointer), LR (Link Register) and PC (Program Counter): Limitedly accessible
CPSR: Directly accessible
SPSR: Not accessible
THUMB Instructions
Mnemonic Instruction/Description Syntax ARM-code Equivalent
ADC It is used to add the numbers with a carry ADC Rd, Rs ADCS Rd,Rd,Rs
ADD It is used to add two numbers without carry ADD Rd,Rs,Rn ADDS Rd,Rs,Rn
AND It is a logical instruction which is used to compare two AND Rd,Rs ANDS Rd,Rd,Rs
numbers
ASR Arithmetic shift right ASR Rd,Rs MOVS Rd,Rd,ASR Rs
B Unconditional branch B label B Label
BCC Conditional branch BCC label BCC label
BIC Bit clear BIC Rd, Rs BICS Rd,Rd,Rs
BL Branch and Link BL label BL label
BX Branch and Exchange BX Hs BX Hs
CMN Compare Negative CMN Rd,Rs CMN Rd,Rs
CMP Compare CMP Rd,#offset 8 CMP Rd,#offset 8
Mnemonic Instruction/Description Syntax ARM-code equivalent
EOR EOR EOR Rd,Rs EORS Rd,Rd,Rs
LDMIA Load Multiple LDMIA Rb!, {RList} LDMIA Rb!, {RList}
LDR Load Word LDR Rd, [PC, #lmm] LDR Rd, [PC, #lmm]
LDRB Load Byte LDRB Rd, [Rb,R0] LDRB Rd, [Rb,R0]
LDRH Load Half Word LDRH Rd, [Rb, #lm] LDRH Rd, [Rb, #lm]
LSL Logical Shift Left LSL Rd, Rs, #offset 5 MOVS Rd, Rs,LSL #offset
5
LDSRB Load Sign-extended byte LDSRB Rd, [Rb, R0] LDSRB Rd, [Rb, R0]
LDSRH Load sign-extended half LDRSH Rd, [Rb,R0] LDRSH Rd, [Rb,R0]
word
LSR Local Shift Right LSR Rd, Rs MOVS Rd,Rd,LSR Rs
MOV Move register MOV Rd, #offset 8 MOV Rd, #offset 8
Mnemonic Instruction/Description Syntax Arm-code equivalent
MUL Multiply MUL Rd, Rs MULS Rd, Rs,Rd
MVN Move NOT Register MVN Rd, Rs MVNS Rd, Rs
NEG Negate NEG Rd, Rs RSBS Rd, Rs,#0
ORR Logical OR ORR Rd,Rs ORRS Rd, Rd,Rs
POP It is used to POP registers POP {Rlist} LDMIA R13!, {Rlist}
PUSH It is used to PUSH registers PUSH {Rlist} STMDB R13!, {Rlist}
ROR Rotate Right ROR Rd, Rs MOVS Rd, Rd,ROR Rs
SBC It is used to subtract two numbers with carry SBC Rd, Rs SBCS Rd, Rd, Rs
STMIA Store multiple STMIA Rb!, {Rlist} STMIA Rb!, {Rlist}
STR Store word STR Rd, [Rb, R0] STR Rd, [Rb, R0]
STRB Store Byte STRB Rd, [Rb, R0] STRB Rd, [Rb, R0]
Mnemonic Instruction Syntax Arm-code development.
STRH Store Half-word STRH Rd, [Rb, R0] STRH Rd, [Rb, R0]
SWI Software Interrupt SWI values SWI values
SUB It is used to subtract two SUB Rd, Rs, Rn SUB Rd, Rs, Rn
numbers without carry
TST Test bits TST Rd, Rs TST Rd, Rs
ARM vs THUMB
ARM Code Thumb Code
ARM Divide Thumb divide
;IN: r0 (value), r1 (divisor) ;IN: r0(value), r1 (divisor)
;OUT: r2 (MODULUS), r3 (DIVIDE) ;OUT: r2 (MODulus), r3 (DIVide)
MOV r3, #0 MOV r3, #0
LOOP Loop
SUBS r0, r0, r1 ADD r3, #1
ADDGE r3,r3,#1 SUB r0,r1
BGE Loop BGE loop
ADD r2,r0, r1 SUB r3, #1
ADD r2, r0, r1
Total no of bytes: 20 bytes
Total no of bytes = 12 bytes
How to set THUMB state?
By default THUMB state is in disabled mode.
To get it enable CPSR should be accessed and T bit should be set.
Setting T bit can be done by adding 0x20. It will set the T bit and eventually the THUMB mode will be
set.
ENTRY
MRS R0, CPSR ;Copying the content of current CPSR to R0
ADD R0, R0, #0X20 ; Adding 0x20 in such a way that T bit will be set
MSR cpsr_c, r0 ;Added result should be moved to CPSR with MSR instruction
B.
Now programmer can check CPSR that T bit is got set.
1. Add the contents of Registers R1,R2 and save the result in to R3.Use
Step execution in keil, write down the contents of various flags of ARM7
AREA PROG_2_1, CODE, READONLY

ENTRY
MOV R1, #0x25 ;R1 = 0x25
MOV R2, #0x34 ;R2 = 0x34
ADD R3, R2,R1 ;R3 = R2 + R1
HERE B HERE ;stay here forever
END
2. Perform Multiplication operations in ARM7

AREA EXP2, CODE, READONLY
ENTRY
START MOV R0,#0XFFFFFFFF
MOV R1,#0X80000000
MULS R2,R0,R1
END
3. Load R1 register with F631024C and R0 register with 17539ABD.Swap
the contents using a logic gate function.
ENTRY
START LDR R1,=0xF631024C
LDR R0,=0x17539ABD
EOR R0,R0,R1
EOR R1,R0,R1
EOR R0,R0,R1
END
4. Let the register content of r5 and r7 are 5 and 8 respectively. Without
using MUL instruction make r5 content as 14h(20d)
ENTRY
START mov r5,#5
mov r7,#8
mov r7,r5,lsl#2
END
5. What is the inference of the following code? execute and observe
ENTRY
START mov r1,#0x77
mov r0,#0
rsb r0,r1,#2
END

ENTRY
START MOV R0,#5
MOV R3,R0
MOV R1,#1
LOOP
MUL R2,R0,R1
MOV R0,R2
ADD R1,#1
CMP R1,R3
BLT LOOP
MOV R5,R0
HLT
B HLT
END

ENTRY
START MOV R0,#-4
LDR R2,=0X80000000
AND R3,R2,R0
CMP R3,R2
MVNEQ R1,R0
ADDEQ R1,#1
MOVNE R1,R0
HLT
B HLT
END
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$

What, More Number Systems?
Why do we need more number systems?
• Humans understand decimal
• Computers understand binary only.
• Since computers have 32, 64, and even 128 bit busses, displaying
numbers in binary is cumbersome.
• Data on a 32 bit data bus would look like the following:

0110 1001 0111 0001 0011 0100 1100 1010
• Hexadecimal (base 16) number systems is used to represent

binary data in a more compact form.
Converting To and From Decimal
Decimal10
0123456789
Weighted
Multiplication
Successive
Division
Successive Weighted
Division Multiplication
Hexadecimal16
0123456789ABCDEF
Binary2
01
2
Counting . . . 2, 8, 10, 16
Decimal Binary Octal Hexadecimal
0 00000 0 0
1 00001 1 1
2 00010 2 2
3 00011 3 3
4 00100 4 4
5 00101 5 5
6 00110 6 6
7 00111 7 7
8 01000 10 8
9 01001 11 9
10 01010 12 A
11 01011 13 B
12 01100 14 C
13 01101 15 D
14 01110 16 E
15 01111 17 F
16 10000 20 10
17 10001 21 11
18 10010 22 12 3
19 10011 23 13
Decimal ↔ Hexadecimal Conversion
The Process: Successive Division
• Divide the decimal number by 16; the remainder is the LSB of the
hexadecimal number.
• If the quotation is zero, the conversion is complete. Otherwise
repeat step (a) using the quotation as the decimal number. The
new remainder is the next most significant bit of the hexadecimal
number.
Example:
Convert the decimal number 9410 into its hexadecimal equivalent.
5
16 94 r  E  LSB
0
16 5 r  5  MSB
 9410 = 5E16
4
Example: Dec → Hex
Example:
5
Example: Dec → Hex
Example:
Solution:
26
16 429 r  D (13)  LSB
1
16 26 r  A (10)  42910 = 1AD16 = 1ADH
0
16 1 r 1  MSB
6
Hexadecimal ↔ Decimal Process
The Process: Weighted Multiplication
• Multiply each bit of the hexadecimal number by its corresponding
bit-weighting factor (i.e., Bit-0→160=1; Bit-1→161=16; Bit-
2→162=256; etc.).
• Sum up all of the products in step (a) to get the decimal number.
Example:
Convert the octal number 5E16 into its decimal equivalent.
5 E
161 160  5E 16 = 9410
Bit-Weighting
16 1 Factors
80 + 14 = 9410
7
Example: Hex → Dec
Example:
Convert the hexadecimal number B2EH into its decimal equivalent.
8
Example: Hex → Dec
Example:
Convert the hexadecimal number B2EH into its decimal equivalent.
Solution:
B 2 E
162 161 160
256 16 1
 B2EH = 286210
2816 + 32 + 14 = 286210
9
Hex Decimal Addition
10
Hex Decimal Subtraction
11
Module:1
Overview of microprocessor
Module outline
• What is a microprocessor
• Block diagram of a computer system
• Nibble, byte, word and longword
• Internal structure and basic operation of a microprocessor
• Bus system: data bus, address bus and control bus.
• History of microprocessors : 4, 8, 16, 32 and 64 byte
2
What is a microprocessor?
ANY OF A TYPE OF MINIATURE ELECTRONIC DEVICE THAT CONTAINS THE
ARITHMETIC, LOGIC, AND CONTROL CIRCUITRY NECESSARY TO PERFORM
THE FUNCTIONS OF A MICRO COMPUTER'S CENTRAL PROCESSING UNIT
MICROPROCESSOR
MICRO +PROCESSOR
CPU OF A MICROCOMPUTER
3
DEFINITION OF MICROPROCESSOR
⚫ Microcomputer:-
It is a programmable machine.
The main characteristics of a computer are:
• Responds to a specific set of instructions in a well-defined manner
• Its main components are CPU, Input & Output devices & Memory
⚫ Microprocessor:-
It is a programmable VLSI chip which includes ALU, register circuits & control
circuits. Its main units are-
• ALU
• Registers
• Control Unit
⚫ Microcontroller:-
Silicon chip which includes microprocessor, memory & I/O in a single package
4
Microprocessor • Microprocessor (μp) – silicon chip which includes
ALU, register circuits & control circuits
and
• Microcontroller (μc) – silicon chip which includes
Microcontroller microprocessor, memory & I/O in a single package.
Microcomputer
Microprocessor Microcontroller
DIAGRAM OF A COMPUTER SYSTEM
A computer is a programmable machine that receives input, stores and

manipulates data, and provides output in a useful format.
Diagram of a Computer System 6

BLOCK DIAGRAM OF A BASIC COMPUTER SYSTEM
Basic computer system consist of a Central Processing Unit

(CPU), memory (RAM and ROM), input/output (I/O) unit.
Address bus
ROM RAM I/O I/O

CPU interface devices
Data bus Control bus
Block diagram of a basic computer system
7
Basic components of a microcomputer
1. CPU - Central Processing Unit
• The portion of a computer system that carries out the
instructions of a computer program
• The primary element carrying out the computer's functions.
• It is the unit that reads and executes program.
• Program: Set of instructions required to perform some
desired operations.
• The data in the instruction tells the processor what to do.
Pentium D dual core processors

8
2. Memory
• Physical devices used to store data or programs.
• Computer main memory comes in two principal varieties:
Random-Access Memory (RAM) and Read-Only Memory
(ROM).
• RAM can be read and written when the CPU commands it, but
ROM is pre-loaded with data and software that never changes, so
the CPU can only read from it.
• ROM is typically used to store the computer's initial start-up
instructions.
• In general, the contents of RAM are erased when the power to
the computer is turned off, but ROM retains its data indefinitely.
• In a PC, the ROM contains a specialized program called the
BIOS that coordinates loading the computer's operating system
from the hard disk drive into RAM whenever the computer is
turned on or reset.
9
3. I/O Unit
• Input/Output (I/O), refers to the communication between an

information processing system, and the outside world possibly a
human, or another information processing system.
• Inputs are the signals or data received by the system, and outputs
are the signals or data sent from it
• Devices that provide input or output to the computer are called
peripherals
• On a typical personal computer, peripherals include input devices
like the keyboard and mouse, and output devices such as the
display and printer.
• Hard disk drives, floppy disk drives and optical disc drives serve
as both input and output devices.
• Computer networking is another form of I/O.
10
DATA SIZE
Nibble 4 bit
Byte 8 bit
Word 16 bit
Long word 32 bit
11
Binary Information
Representation
• Bit: the smallest unit of storage. A

bit stores just a 0 or 1.
• One byte = collection of 8 bits e.g. 0
1 0 1 1 0 1 0. One byte can store one
character, e.g. 'A' or 'x' or ‘$’.
• Word = 2 bytes = 16 bits e.g. ‘An’
• Long Word = 2 words = 32 bits e.g.
‘Word’
• Very Long Word = 4 words = 64 bits
e.g. ‘Alphabet’
12
Internal structure and basic operation of
microprocessor
ALU Register Address bus

Section
Data bus
Control and timing

section Control bus
Block diagram of a Microprocessor Unit
13
Arithmetic and logic unit (ALU)
• The component that performs the arithmetic and logical operations
• The most important components in a microprocessor, and is
typically the part of the processor that is designed first.
• Able to perform the basic logical operations (AND, OR), including
the addition operation.
14
Control unit
• The circuitry that controls the flow of information through the
processor, and coordinates the activities of the other units within
it.
• In a way, it is the "brain within the brain", as it controls what
happens inside the processor, which in turn controls the rest of the
PC.
• On a regular processor, the control unit performs the tasks of
fetching, decoding, managing execution and then storing results.
15
Register sets
• The register section/array consists completely of circuitry used to
temporarily store data or program codes until they are sent to
the ALU or to the control section or to memory.
• The number of registers are different for any particular CPU and the
more register a CPU have will result in easier programming tasks.
• Registers are normally measured by the number of bits they can

hold, for example, an "8-bit register" or a "32-bit register".
16
System Bus
• Microprocessor Unit(MPU) communicates with Memory and I/O
using the System Bus
• Address bus
• Unidirectional
• Memory and I/O Addresses
• Data bus
• Bidirectional
• Transfers Binary Data and Instructions
• Control bus
• Read and Write timing signals
Data bus
• The data bus is 'bi-directional’
• Data or instruction codes from memory or input/output
are transferred into the microprocessor
• The result of an operation or computation is sent out
from the microprocessor to the memory or input/output.
• Depending on the particular microprocessor, the data bus can handle
8 bit or 16 bit data.
18
Address bus
• The address bus is 'unidirectional', over which the microprocessor
sends an address code to the memory or input/output.
• The size (width) of the address bus is specified by the number of bits
it can handle.
• The more bits there are in the address bus, the more memory
locations a microprocessor can access.
• A 16 bit address bus is capable of addressing 65,536 (64K)
addresses.
19
Control bus
• The control bus is used by the microprocessor to send out or receive
timing and control signals in order to coordinate and regulate its
operation and to communicate with other devices, i.e. memory or
input/output.
20
Timing Circuit: Micro processor clock
• Also called clock rate, the speed at which a microprocessor

executes instructions.
• Every computer contains an internal clock that regulates the rate
at which instructions are executed and synchronizes all the
various computer components.
21
HISTORY OF MICROPROCESSORS
22
Contents
 Introduction
 4-Bit Microprocessors
Introduction
 Fairchild Semiconductors (founded in 1957) invented the first

IC in 1959.
 In 1968, Robert Noyce, Gordan Moore, Andrew Grove

resigned from Fairchild Semiconductors.
 They founded their own company Intel (Integrated

Electronics).
 Intel grown from 3 man start-up in 1968 to industrial giant by
1981.
 It had 20,000 employees and $188 million revenue.

Intel 4004
 Introduced in 1971.
 It was the first

microprocessor by Intel.
 It was a 4-bit µP.
 Its clock speed was 740KHz.
 It had 2,300 transistors.
 It could execute around

60,000 instructions per
second.
25
Intel 4040
 It was also 4-bit µP.
26
8-bit Microprocessors
Intel 8008
 It was first 8-bit µP.
 Its clock speed was 500 KHz.
 Could execute 50,000 instructions

per second.
27
Intel 8080
 Its clock speed was 2 MHz.
 Was 10 times faster than 8008.
 Could execute 5,00,000
instructions per second.
28
Intel 8085
 Its data bus is 8-bit and address bus
is 16-bit.
 Could execute 7,69,230 instructions
per second.
 It could access 64 KB of memory.
 It had 246 instructions.
 Over 100 million copies were sold.
29
Intel 8086  It was first 16-bit µP.
 Its clock speed is 4.77 MHz, 8 MHz

and 10 MHz, depending on the
version.
 Its data bus is 16-bit and address
bus is 20-bit.
 Could execute 2.5 million
 It could access 1 MB of memory.
 It had 117 basic instructions.
 It had Multiply and Divide

Intel 8088
 It was created as a cheaper

version of Intel’s 8086.
 It was a 16-bit processor with

an 8-bit external bus.
 Could execute 2.5 million

 This chip became the most

popular in the computer
industry when IBM used it for
its first PC.
31
Intel 80186 & 80188
 They were 16-bit µPs.
 Clock speed was 6 MHz.
 80188 was a cheaper version
of 80186 with an 8-bit
external data bus.
 They had additional
components like:
 Interrupt Controller
 Clock Generator
 Local Bus Controller
 Counters
32
Intel 80286
 It was 16-bit µP.
 Its data bus is 16-bit and
address bus is 24-bit.
 It could address 16 MB of
memory.
 It had 1,34,000 transistors.
 It could execute 4 million
33
Introduced in 1986.

Intel 80386 It was first 32-bit µP.

 Its data bus is 32-bit and address bus is

32-bit.
 It could address 4 GB of memory.
 It had 2,75,000 transistors.
 Its clock speed varied from 16 MHz to 33
MHz depending upon the various
versions.
 Different versions:
 80386 DX
 80386 SX
 80386 SL
Intel 80386 became th2e1 best selling
microprocessor in history.
Intel 80486
 It had 1.2 milliontransistors.
 Its clock speed varied from
16 MHz to 100 MHz
 It had five different
versions:
 80486 DX
 80486 SX
 80486 DX2
 80486 SL
 80486 DX4
 8 KB of cache memory was
introduced.
22
Intel Pentium
 It was originally named
80586.
 Its data bus is 32-bit and
address bus is 32-bit.
 It could address 4 GB of memory.
 Could execute 110 million
 Cache memory:
 8 KB for instructions.
 8 KB for data.
Intel Pentium Pro
 It had L2 cache of 256 KB.
 It had 21 million transistors.
 It was primarily used in server
systems.
 Cache memory:
 8 KB for instructions.
 8 KB for data.
 It had L2 cache of 256 KB.

37
Intel Pentium II
 Its clock speed was 233 MHz to
500 MHz.
 Could execute 333 million
 MMX technology was supported.
 L2 cache & processor were on
one circuit.
38
Intel Pentium II Xeon
 It was designed for servers.

 Its clock speed was 400 MHz
to 450 MHz.
 L1 cache of 32 KB & L2 cache

of 512 KB, 1MB or 2 MB.
 It could work with 4 Xeons in

same system.
39
Intel Pentium III
 Its clock speed varied
from 500 MHz to 1.4 GHz.
 It had 9.5 million
transistors.
40
Intel Pentium IV
 Its clock speed was from 1.3

GHz to 3.8 GHz.
 L1 cache was of 32 KB & L2

cache of 256 KB.
 It had 42 million transistors.
 All internal connections were

made from aluminium to
copper.
41
Intel Dual Core
 It is 32-bit or 64-bit µP.
 It has two cores.
 Both the cores have there
own internal bus and L1
cache, but share the
external bus and L2 cache.
 It supported SMT
technology.
 SMT: Simultaneously
Multi- Threading
 E.g.: Adobe Photoshop
supported SMT.
Introduced in 2006.
Intel Core 2

 It is a 64-bit µP.
 Its clock speed is from 1.2 GHz
to 3 GHz.
 It has 291 million transistors.
 It has 64 KB of L1 cache per
core and 4 MB of L2 cache.
 It is launched in three different
versions:
 Intel Core 2 Duo
 Intel Core 2 Quad
 Intel Core 2 Extreme
43
Intel Core i7
 It has 4 physical cores.
 Its clock speed is from 2.66 GHz
to 3.33 GHz.
core, 256 KB of L2 cache and 8
MB of L3 cache.
44
Intel Core i5
 Its clock speed is from 2.40
GHz to 3.60 GHz.
core, 256 KB of L2 cache and
8 MB of L3 cache.
45
Intel Core i3
 Its clock speed is from 2.93GHz to
3.33 GHz.
 It has 64 KB of L1 cache per core,
512 KB of L2 cache and 4 MB of
L3 cache.
46
Microcontroller
The microcontroller like 8051 was designed in the year 1981 by Intel.
Its foundation was on Harvard Architecture and was developed principally for bringing into play Embedded
Systems.
An Embedded system product is used to do only one task, or we can say these are the application specific
processors with memory, I/O, Timers, buses etc. on one single chip.
At first, it was created using NMOS technology but as NMOS technology needs more power to function therefore
Intel re-intended Microcontroller 8051 employing CMOS technology and a new edition came into existence with a
letter ‘C’ in the title name, for illustration: 80C51.
The most common embedded systems that we use from day to day life are Air Conditioner, Touch Screen, Anti-
Break System, Biometric Attendance System, Face Sensors etc.
1
Microprocessor Microcontroller
Key Differences Heart/Brain of the Computer System. Heart/Brain of the embedded system.
Between Externally connected with input-output

components.
input-output components are embedded.
Microprocessor and The circuit may be large depending upon
Microcontroller
The circuit is very small.
usage.
Not cost-effective. Cost-effective.
The total consumption of power is high. Total consumption of power is less.
Power saving mode is not generally

Power saving mode is generally offered.
available.
Used in MP3 players, washing machines,

Used in PC.
AC etc.
Memories like RAM and ROM are absent. Carries RAM, ROM, etc.
Runs at a very high speed. Runs at a relatively lower speed.
It is complex and costly. Simple and cheap.
Example: DEC Alpha 21164, IBM RS6000, Example: Intel 8051, PIC 16x, Zilog’s Z8,
etc. Freescale’s 6811 etc.
2
Some Embedded products using 3
Microcontroller
 Security systems  Laser printer  Garage door openers
 Fax machines  Color printer  Intercom
 Remote controls  Air bag  Air Conditioners
 Video games  ABS  Refrigerator
 Camera  Keyless entry  Telephones
 Toys  Climate control  Washing Machine
 Exercise equipment  TVs  Lighting Control
 Microwave  Biometric System  Musical Instruments

Microcontroller Companies
Company Web Site
Intel www.intel.com/design/mcs51
Atmel www.atmel.com
Philips/Signetics www.semiconductors.philips.com
Infineon www.Infineon.com
Dalla Semi/Maxim www.maxim-ic.com
Silicon Labs www.silabs.com
4
How to choose a microcontroller ?
Three criteria in Choosing a Microcontroller:

• Meeting the computing needs of the task efficiently and cost effectively
• Speed, the amount of ROM and RAM, the number of I/O ports and
timers, size, packaging, power consumption
• Easy to upgrade
• Cost per unit
• Availability of software development tools
• Assemblers, debuggers, C compilers, emulator, simulator, technical
support
• Wide availability and reliable sources of the microcontrollers.
5
The 8051 Microcontroller
A harvard Single chip
architecture (separate microcontroller (µc)
instruction/data
memories)
Developed by intel in Today largely superseded by a vast

1980 for use in range of faster and/or functionally
embedded systems. enhanced 8051-compatible devices
manufactured by more than 20
independent manufacturers
• ROM - 4K Byte
• RAM – 128 Byte
• I/O Pins – 32
• Interrupt Sources – 6
Block Diagram of 8051 • Timers – 2
• Serial port - 1
6
8051 microcontroller is designed by Intel in 1981.
It is an 8-bit microcontroller.
It is built with 40 pins DIP (dual inline package)

Main Features of
The 8051 It has 4KB of ROM storage
Microcontroller In consist of 128 bytes of RAM storage
It has two 16-bit timers
It consists of are four parallel 8-bit ports, which are

programmable as well as addressable as per the requirement.
An on-chip crystal oscillator is integrated in the microcontroller

having crystal frequency of 12 MHz.
7
Comparison of the 8051 Family Members
Feature 8051 8052 8031
ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6
8
Pin Diagram of
8051
8051 microcontroller is available in 40

pin Dual Inline package (DIP)
Four I/O ports (Port-1, Port-2, Port-3,

Port-4 ) w
The remaining pins are assigned to

VCC, GND, XTAL1, XTAL2, RST,
ALE, EA and PSEN here in each port
has 8 pin.
9
Explanation of the Pins
- Pin 1 to Pin 8 (Port – 1) – Pin 1 to Pin 8 is assigned to Port 1 for simple I/O
operations. It is a bidirectional port.
- Pin 9 (RST) – It is a reset input Pin, which is used to reset the 8051
- Pin 10 to Pin 17 (Port-3) – Pin 10 to Pin 17 are assigned to Port 3. This port is
also a bidirectional I/O port like port 1. This port performs some special functions
like interrupts, control signals, timer input, serial communication etc.
- Pin 18 and Pin 19 (XTAL2 And XTAL1) –Pins 18 and 19 i.e. XTAL 2 and
XTAL 1 are the pins for interfacing external oscillator. Mostly, a Quartz Crystal
Oscillator is connected here to get the system clock.
- Pin 20 (GND) – Pin 20 is the Ground Pin. It is connected to the 0V (negative

terminal) of the Power Supply.
10
Explanation of the Pins
- Pin 21 to Pin28 (Port 2) – Pin 21 to pin 28 are port 2 pins. This port is also a bidirectional I/O port. But, this
is only possible when we are not using any external memory. If we use external memory, then these pins will
work as high order address bus (A8 to A15).
- Pin 29 (PSEN) – The Pin 29 is the Program Store Enable Pin (PSEN). It is used to enable external program
memory and read a signal from the external program memory.
- Pin 30 (ALE) – Pin 30 is the Address Latch Enable Pin. This pin is used to enable or disable the external
memory interfacing.
- Pin 31 (EA) – Pin 31 is the External Access Enable (EA) Pin. This pin allows external Program Memory. It is
an input pin and connected from VCC or GND. If we want to access the program from external program
memory, it must be connected with GND. If we want to use on-chip memory, it must be high (connected with
VCC).
- Pin 32 to Pin 39 (Port 0) – Pin 32 to Pin 39 are Port 0 pins. when we don’t use any external memory, these
pins are used as a bidirectional pin like port 2 and port 3. But, when ALE or Pin 30 is at 1, then this port is
used as data bus. And when the ALE pin is at 0, then this port is used as a lower order address bus (A0 to A7).
- Pin 40 (VCC) – This pin is used to provide (+5V ) power supply to the 8051 microcontroller circuit.
11
12
- Accumulator (A register) – The Accumulator, as its name suggests, is 13
used as a general register to accumulate the results of many instructions. It
can hold an 8-bit (1-byte) value and is the most versatile register the 8051.
This register is mostly used for arithmetic operations. The accumulator
register (A or ACC) act as an operand register, in case of some
instructions.
- B register – This is an 8-bit register that is bit addressable and is used for
two instructions only like MUL AB and DIV AB.
MOV & ADD Instruction:

MOV destination, source ;copy source to dest
ADD A, Source
• MOV A,#55H
• MOV R0,A MOV A,#55H
• MOV R1,#34H
MOV R0,#46H
• MOV A,R1
• MOV R2,#20 ADD A,R0
• MOV A,R2
Module 3, Microprocessor & Microcontroller, SENSE VIT Dr. Shelja, Assistant Professor
- PSW register – Program Status Word (PSW) is the flag 14
resister in 8051. The flag bits are used to indicate the

arithmetic condition of the ACC. This register consists of
flags like Carry, Auxiliary Carry Flag, Flag 0 Register
Select 1, Register Select 0, Parity Flag, Overflow flag.
● CY, the carry flag: This flag is set whenever there is a carry out from
the D7 bit. This flag bit is affected after an 8-bit addition or subtraction.
It can also be set to 1 or 0 directly by an instruction such as “SETB C”
and “CLR C” where “SETB C” stands for “set bit carry” and “CLR C”
for “clear arry”.
● AC, the auxiliary carry flag: If there is a carry from D3 to D4

during an ADD or SUB operation, this bit is set; otherwise, it is cleared.
● P, the parity flag: The parity flag reflects the number of 1s in the A
(accumulator) register only. If the A register contains an odd number of
1s, then P = 1, Otherwise, P = 0 if A has an even number of 1s.
● OV, the overflow flag: This flag is set whenever the result of a signed
number operation is too large, causing the high-order bit to overflow
into the sign bit. In general, The overflow flag is only used to detect
errors in signed arithmetic operations.
Module 3, Microprocessor & Microcontroller, SENSE VIT

Dr. Shelja, Assistant Professor
Instructions That Affect Flag Bits
Note: X can be 0 or 1.
15
Example 1
Show the status of the CY, AC, and P flags after the addition of 38H and 2FH in the following
instructions.
MOV A,#38H
ADD A,#2FH ;after the addition A=67H, CY=0
Solution:
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit.

AC = 1 since there is a carry from the D3 to the D4 bit.
P = 1 since the accumulator has an odd number of 1s (it has five 1s).
16
Example 2
Show the status of the CY, AC, and P flags after the addition of 9CH and 64H in the following
instructions.
MOV A,#9CH
ADD A,#64H ;after addition A=00 and CY=1
Solution:
9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit.

AC = 1 since there is a carry from the D3 to the D4 bit.
P = 0 since the accumulator has an even number of 1s (it has zero 1s).
17
Some 8051 16-bit Registers
18
- DPTR (Data Pointer)- This 16-bit register

contains a higher byte (DPH) and the lower
byte (DPL) of a 16-bit external data RAM
address
- Program Counter – is a 16 bit register that

helps to access address from 0000H to
FFFFH. Program Counter is used to address
the next instruction to be executed from the
ROM.

19
Memory Organization
The 8051 microcontroller's memory is

divided into Program Memory and Data
Memory.
Program Memory (ROM) is used for

permanent saving program being
executed.
Data Memory (RAM) is used for

temporarily storing and keeping
intermediate results and variables.
20
ROM Memory
Map in the
8051 Family
 Program Memory (ROM) is used
for permanent saving program
(CODE) being executed.
 8051 memory organization
allows external program memory
to be added. memory type How
does the microcontroller handle
external memory depends on
the pin EA logical state.

Data Memory -
21
RAM

22

Machine cycle
Addressing Modes
 What is addressing modes?
◦ The addressing modes help us specify the way
in which an operand’s effective address is
represented in any given instruction.
◦ The CPU can access data in various
ways, which are called addressing modes
◦ The addressing modes describe an efficient and
flexible way to define complex effective
addresses.
Types of AM in 8051
 Immediate
 Register
 Direct
 Register Indirect
 Indexed
Opcode and Operand
 The opcode is the instruction that is
executed by the CPU and
 The operand is the data or memory
location used to execute that instruction.
Immediate Addressing Mode
 Here, the source operand is a constant.
 The immediate data must be preceded by the hash
sign, “#”
 This addressing mode can load information into any
registers, including 16-bit DPTR register.
 We can also use immediate addressing mode to send
data to ports.
 Ex. MOV R4, #45H
 MOV DPTR, #4521H
 MOV P1, #55H
Register Addressing Mode
 Use registers to hold the data to be

manipulated.
 The source and destination registers must
match in size.
 The movement of data between Rn
registers is not allowed.
Direct Addressing Mode
 Direct addressing mode is capable of
addressing whole 128 byte RAM.
 But most often used the to access RAM
locations 30-7FH.
 MOV 56h,A ; To save the content of A in
RAM location 56H.
Register Indirect Addressing Mode
 In this addressing mode, a register is used
as a pointer to the data.
 If the data is a part of the internal data
RAM, either register R0 or R1 can be used
for this purpose and in the instruction
format they must be preceded with “@”
sign.
 Apart from this, the data can also be
accessed from externally located RAM
using register indirect with the help of the
DPTR register.
Cont.
 One of the advantage of the Register-indirect
mode is that it makes accessing data dynamic
rather than static.
 Register indirect addressing is used to access:
◦ Internal data RAM using @R0, @R1 and @SP (in
the case of PUSH and POP only)
◦ External data memory using @DPTR.
◦ Ex. MOV A, @R0 – It means, move contents of RAM
location whose address is held by R0 to A.
◦ MOVX @DPTR, A – Move the contents of A, to
external RAM location whose address is held by
DPTR.
Indexed Addressing Mode
 This addressing mode is widely used in
accessing data elements of look-up table
entries located in the program ROM
space.
 The instruction used for this purpose is
◦ MOVC A, @A+DPTR
◦ MOVC A, @A+PC.
 “C” stands for “code”.
Cont.
 In the first case, the contents of register A
is added to the contents of the 16 bit
register DPTR to generate the address of
the data element stored in on-chip ROM.
 That data element is transferred to A.
 This is also refereed as “base register
plus index register addressing
mode”.
 The DPTR act as base register and the A
register act as index register.
Cont.
 In the second case, the PC is incremented
to the address of the following instruction
before it is added to the A register to
generate the address of the data element
stored in on-chip ROM.
 Then, that data element is transferred to
A.
Introduction
 An instruction is an order or command given

to a processor by a computer program.
 All commands are known as instruction set
and set of instructions is known as program.
 8051 have in total 111 instructions, i.e. 111

different words available for program writing.
Types Of Instructions
1. Data transfer instructions.

2. Arithmetic instructions.
3. Logical instructions.
4. Logical instructions with bits.
5. Branch instructions.
Data Transfer Instructions
 These instructions move the content of one

register to another one.
 Data can be transferred to stack with the help

of PUSH and POP instructions.
 MNEMONIC DESCRIPTION BYTES
 MOV A,Rn (A) (Rn) 1
 MOV A,addr (A) (addr) 2
 MOV A,@Ri (A) (Ri) 1

 MOV A,#X (A) Data 2
 MOV Rn,A (Rn) (A) 1
 MOV Rn, addr (Rn) (addr) 2

 MOV Rn, #X (Rn) Data 2
 MOV addr, A (addr) (A) 2
 MOV addr, Rn (addr) (Rn) 2

 MOV addr, addr (addr) (addr) 3
 MOV addr, @ Ri (addr) (Ri) 2
 MOV addr, # X (addr) Data 3

 MOV @ Ri, A (Ri) (A) 1
 MOV @ Ri, addr (Ri) (addr) 2
 MOV @ Ri, #X (Ri) Data 2

 MOV DPTR, #X (DPTR) Data 3
 MOVC A @ (A) (A+DPTR) 1

A+DPTR
 MOVC A@ (A) (A+PC) 1

A+PC
 MOVX A,@ Ri A (Ri) 1
 MOVX A, @ (A) (DPTR) 1

DPTR
 MOVX @Ri, A (Ri) (A) 1

 MOVX @ (DPTR) (A) 1

DPTR, A
 PUSH Rx Push directly 2

addressed Rx register on stack
 POP Rx (Rx) (Stack) 2

 XCH A, Rn (A) (Rn) 1
 XCH A, Rx (A) (Rx) 2
 XCH A, @Ri (A) (Ri) 1

 XCHD Exchange 4 lower 1

bits in accumulator with indirectly
addressed register
 These instructions perform several basic

operations. After execution, the result is
stored in the first operand.
 8 bit addition, subtraction, multiplication,

increment-decrement instructions can be
performed.
 MNEMONICS DESCRIPTION BYTE
 ADD A, Rn A = A + Rn 1
 ADD A, Rx A = A + Rx 2
 ADD A, @ Ri A = A+ @Ri 1
 ADD A, # X A = A + Byte 2
 ADDC A, Rn A = A + Rn + C 1
 ADDC A , Rx A = A + Rx + C 2
 ADDC A, @ Ri A = A + Ri + C 1
 ADDC A, # X A = A + Byte + C 2
 SUBB A, Rn A = A – Rn – 1 1
 SUBB A, Rx A = A – Rx – 1 2
 SUBB A, @ Ri A = A – Ri – 1 1
 SUBB A, # X A = A – Byte – 1 2
 INC A A=A+1 1
 INC Rn Rn = Rn + 1 1
 INC Rx Rx = Rx + 1 2
 INC @ Ri Ri = Ri + 1 1
 DEC A A=A–1 1
 DEC Rn Rn = Rn – 1 1
 DEC Rx Rx = Rx – 1 2
 DEC @ Ri Ri = Ri – 1 1
 INC DPTR DPTR = DPTR + 1 1

 MUL AB B:A = A * B 1
 DIV AB A = [A/B] 1
 DA A Decimal adjustment of 1
accumulator according to BCD code
Logical Instructions
 These instructions perform logical operations

between two register contents on bit by bit
basis.
 After execution, the result is stored in the first

operand.
 MNEMONIC DESCRIPTION BYTE
 ANL A, Rn (A) (A) ^ (Rn) 1
 ANL A, Rx (A) (A) ^ (Rx) 2
 ANL A,@ Ri (A) (A) ^ (Ri) 1

 ANL A, # X (A) (8 bit data) ^ (A) 2
 ANL Rx, A (Rx) (A) ^ (Rx) 2
 ANL Rx,# X (Rx) (8 bit data) ^ (Rx) 3

 ORL A, Rn (A) (A) + (Rn) 1
 ORL A, Rx (A) (A) + (Rx) 2
 ORL A, @ Ri (A) (A) + (Ri) 2

 ORL Rx, A (Rx) (A) + (Rx) 2
 ORL Rx,# X (Rx) (8 bit data) + (Rx) 2
 XORL A, Rn Logical exclusive 1

OR operation between the contents of
accumulator and R register.
 XORL A, Rx Logical exclusive OR 2

operation between the contents of the
accumulator and directly addressed register
Rx.
 XORL A,@ Ri Logical exclusive OR 1
accumulator and directly addressed register.
 XORL A, # X Logical exclusive OR 2

operation between the contents of
accumulator and the given 8 bit data.
 XORL Rx, A Logical exclusive OR 2
accumulator and directly addressed register
Rx.
 XORL Rx, # X Logical exclusive OR 3

directly addressed register Rx and the given
8 bit data.
 CLR A (A) 0 1
 CPL A (A) (/A) 1

 SWAP A (A3-0) (A7-4) 1
 RL A (An + 1) (An) 1
(A0) (A7)
 RLC (An + 1) (An) 1
(A0) (C)
(C) (A7)
 RR A (An) (An + 1) 1
(A7) (A0)
 RRC A (An) (An + 1) 1

(A7) (C)
(C) (A0)
Logical Instructions On Bits
 Similar to logical instructions, these

instructions also perform logical operations.
 The difference is that these operations are

performed on single bits.
 CLR C (C=0) 1
 CLR bit clear directly addressed bit 2
 SETB C (C=1) 1
 SETB bit Set directly 2

addressed bit
 CPL C (1 = 0, 0 = 1) 1
 CPL bit Complement directly 2

addressed bit
 ANL C, bit Logical AND operation 2

between Carry bit and directly addressed
bit.
 ANL C,/bit Logical AND operation 2

between Carry bit and inverted directly
addressed bit.
 ORL C, bit Logical OR operation 2

between Carry bit and directly addressed
bit.
 ORL C,/bit Logical OR operation 2

between Carry bit and inverted directly
addressed bit.
 MOV C, bit Move directly addressed 2

bit to carry bit.
 MOV bit, C Move Carry bit to directly 2

addressed bit.
Program Flow Control Instructions
 In this group, instructions are related to the

flow of the program, these are used to
control the operation like, JUMP and CALL
instructions.
 Some instructions are used to introduce

delay in the program, to the halt program.
 ACALL adr11 (PC) (PC) + 2 2

(SP) (SP) + 1
((SP)) (PC7 – 0)
(SP) (SP) + 1
((SP)) (PC15-8)
 LCALL adr16 (PC) (PC) + 3 3

(SP) (SP) + 1
((SP)) (PC7-0)
(SP) (SP) + 1
((SP)) (PC15-8)
(PC) addr15-0
 RET (PC15-8) ((SP)) 1

(SP) (SP) – 1
(PC7-0) ((SP))
(SP) (SP) - 1
 RET1 (PC15-8) ((SP)) 1

(SP) (SP) – 1
(PC7-0) ((SP))
(SP) (SP) – 1
 AJMP addr11 (PC) (PC) + 2 1

(PC10-0) page address
 LJMP addr16 (PC) addr15-0 3
 SJMP rel short jump from 2

(from -128 to +127 locations in
relation to first next instruction)
 JC rel (PC) (PC) + 2 2

IF ( C ) = 1
THEN (PC) (PC) + rel
 JNC rel (PC) (PC) + 2 2

IF ( C) = 0
 JB bit, rel Jump if addressed 3

bit is set. Short jump.
 JBC bit, rel Jump if addressed 3

bit is set and clear it.
Short jump.
 JMP @A + DPTR (PC) (A) + (DPTR) 1
 JZ rel (PC) (PC) + 2 2

IF (A) = 0
 JNZ rel (PC) (PC) + 2 2

IF (A) = 0
 CJNE A, Rx, rel Compare the contents 3

of acc. And directly addressed register Rx.
Jump if they are different. Short jump.
 CJNE A, #X, rel (PC) (PC) + 3 3

IF ( A) < > data
THEN (PC) (PC) + relative
offset
IF (A) < data
THEN ( C ) 1
ELSE ( C ) 0
 CJNE @ RI, # x, rel (PC) (PC) + 3 3

IF (Rn) <> data
offset
IF (Rn) < data
THEN ( C ) 1
ELSE ( C ) 0
 CJNE @ Ri, # X, rel (PC) (PC) + 3 3

IF ((Ri)) <> data
offset
IF ((Ri)) < data
THEN ( C ) 1
ELSE ( C ) 0
 DJNZ Rn , rel (PC) (PC) + 2 2

(Rn) (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
 DJNZ Rx, rel (PC) (PC) + 2 3

(Rx) (Rn) – 1
IF (Rx) > 0 or (Rx) < 0
 NOP No operation 1
Example 3-1: Looping in the 8051
Write a program to
(a) clear ACC, then
(b) add 3 to the accumulator ten times.
Solution:
;This program adds value 3 to the ACC ten times
MOV A,#0 ;A=0, clear ACC

MOV R2,#10 ;load counter R2=10
AGAIN: ADD A,#03 ;add 03 to ACC
DJNZ R2,AGAIN ;repeat until R2=0(10 times)
MOV R5,A ;save A in R5
Example 3-2
What is the maximum number of times that the loop in Example 3-1 can be repeated?
Solution:
Since R2 holds the count and R2 is an 8-bit register, it can hold a

maximum of FFH (255 decimal); therefore, the loop can be repeated a
maximum of 256 times.
Example 3-3: Loop Inside a Loop
Write a program to (a) load the accumulator with the value 55H, and (b) complement the ACC 700
times.
Solution:
Since 700 is larger than 255 (the maximum capacity of any register), we use two registers to hold
the count. The following code shows how to use R2 and R3 for the count.
MOV A,#55H ;A=55H
MOV R3,#10 ;R3=10, the outer loop count
NEXT: MOV R2,#70 ;R2=70, the inner loop count
AGAIN: CPL A ;complement A register
DJNZ R2,AGAIN ;repeat it 70 times (inner loop)
DJNZ R3,NEXT
In this program, R2 is used to keep the inner loop count. In the instruction “DJNZ R2,AGAIN”,
whenever R2 becomes 0 it falls through and “DJNZ R3,NEXT” is executed. This instruction forces
the CPU to load R2 with the count 70 and the inner loop starts again. This process will continue
until R3 becomes zero and the outer loop is finished.
Table 3-1: 8051 Conditional Jump Instructions
Example 3-4
Write a program to determine if R5 contains the value 0. If so, put 55H in it.
Solution:
MOV A,R5 ;copy R5 to A

JNZ NEXT ;jump if A is not zero
MOV R5,#55H
NEXT:...
Example 3-5
Find the sum of the values 79H, F5H, and E2H. Put the sum in registers R0 (low byte) and R5 (high
byte).
Solution:
MOV A,#0 ;clear A(A=0)
MOV R5,A ;clear R5
ADD A,#79H ;A=0+79H=79H
JNC N_1 ;if no carry, add next number
INC R5 ;if CY=1, increment R5
N_1: ADD A,#0F5H ;A=79+F5=6E and CY=1
JNC N_2 ;jump if CY=0
INC R5 ;If CY=1 then increment R5(R5=1)
N_2: ADD A,#0E2H ;A=6E+E2=50 and CY=1
JNC OVER ;jump if CY=0
INC R5 ;if CY=1, increment 5
OVER: MOV R0,A ;Now R0=50H, and R5=02
Example 3-6
Using the following list file, verify the jump forward address calculation.
Line PC Opcode Mnemonic Operand
01 0000 ORG 0000
02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
04 0004 6003 JZ NEXT
05 0006 08 INC R0
06 0007 04 AGAIN: INC A
07 0008 04 INC A
08 0009 2477 NEXT: ADD A,#77h
09 000B 5005 JNC OVER
10 000D E4 CLR A
11 000E F8 MOV R0,A
12 000F F9 MOV R1,A
13 0010 FA MOV R2,A
14 0011 FB MOV R3,A
15 0012 2B OVER: ADD A,R3
16 0013 50F2 JNC AGAIN
17 0015 80FE HERE: SJMP HERE
18 0017 END
Example 3-6
Solution:
First notice that the JZ and JNC instructions both jump forward. The target
address for a forward jump is calculated by adding the PC of the following
instruction to the second byte of the short jump instruction, which is called the
relative address. In line 4 the instruction “JZ NEXT” has opcode of 60 and
operand of 03 at the addresses of 0004 and 0005. The 03 is the relative address,
relative to the address of the next instruction INC R0, which is 0006. By adding
0006 to 3, the target address of the label NEXT, which is 0009, is generated. In
the same way for line 9, the “JNC OVER” instruction has opcode and operand of
50 and 05 where 50 is the opcode and 05 the relative address. Therefore, 05 is
added to 000D, the address of instruction “CLR A”, giving 12H, the address of
label OVER.
Example 3-7
Verify the calculation of backward jumps in Example 3-6.
Solution:
In that program list, “JNC AGAIN” has opcode 50 and relative address F2H.
When the relative address of F2H is added to 15H, the address of the
instruction below the jump, we have 15H + F2H = 07 (the carry is dropped).
Notice that 07 is the address of label AGAIN. Look also at “SJMP HERE”, which
has 80 and FE for the opcode and relative address, respectively. The PC of the
following instruction, 0017H, is added to FEH, the relative address, to get
0015H, address of the HERE label (17H + FEH = 15H). Notice that FEH is -2 and
17H + (-2) = 15H. For further discussion of the addition of negative numbers, see
Chapter 6.
Example 3-8
Write a program to toggle all the bits of port 1 by sending to it the values 55H and AAH continuously.
Put a time delay in between each issuing of data to port 1. This program will be used to test the ports
of the 8051 in the next chapter.
Solution:
ORG 0
BACK: MOV A,#55H ;load A with 55H
MOV P1,A ;send 55H to port 1
LCALL DELAY ;time delay
MOV A,#0AAH ;load A with AA (in hex)
MOV P1,A ;send AAH to port 1
LCALL DELAY
SJMP BACK ;keep doing this indefinitely
;—————— this is the delay subroutine
ORG 300H ;put time delay at address 300H
DELAY: MOV R5,#0FFH ;R5 = 255(FF in hex),the counter
AGAIN: DJNZ R5,AGAIN ;stay here until R5 becomes 0
RET ;return to caller (when R5 = 0)
END ;end of asm file
Example 3-9
Analyze the stack contents after the execution of the first LCALL in the following.
Solution:
001 0000 ORG 0
002 0000 7455 BACK: MOV A,#55H ;load A with 55H
003 0002 F590 MOV P1,A ;send 55H to port 1
004 0004 120300 LCALL DELAY ;time delay
005 0007 74AA MOV A,#0AAH ;load A with AAH
006 0009 F590 MOV P1,A ;send AAH to port 1
007 000B 120300 LCALL DELAY
008 000E 80F0 SJMP BACK ;keep doing this
009 0010
010 0010 ;————————this is the delay subroutine
011 0300 ORG 300H
012 0300 DELAY:
013 0300 7DFF MOV R5,#0FFH ;R5=255
014 0302 DDFE AGAIN: DJNZ R5,AGAIN ;stay here
015 0304 22 RET ;return to caller
016 0305 END ;end of asm file
Example 3-10
Analyze the stack for the first LCALL instruction in the following program.
01 0000 ORG 0
02 0000 7455 BACK: MOV A,#55H ;load A with 55H
03 0002 F590 MOV P1,A ;send 55H to port 1
04 0004 7C99 MOV R4,#99H
05 0006 7D67 MOV R5,#67H
06 0008 120300 LCALL DELAY ;time delay
07 000B 74AA MOV A,#0AAH ;load A with AA
08 000D F590 MOV P1,A ;send AAH to port 1
09 000F 120300 LCALL DELAY
10 0012 80EC SJMP BACK ;keep doing this
11 0014 ;————————this is the delay subroutine
12 0300 ORG 300H
13 0300 C004 DELAY: PUSH 4 ;PUSH R4
14 0302 C005 PUSH 5 ;PUSH R5
15 0304 7CFF MOV R4,#0FFH ;R4=FFH
16 0306 7DFF NEXT: MOV R5,#0FFH ;R5=255
17 0308 DDFE AGAIN: DJNZ R5,AGAIN
18 030A DCFA DJNZ R4,NEXT
19 030C D005 POP 5 ;POP into R5
20 030E D004 POP 4 ;POP into R4
21 0310 22 RET ;return to caller
22 0311 END ;end of asm file
Example 3-10
Solution:
First notice that for the PUSH and POP instructions we must specify the direct
address of the register being pushed or popped. Here is the stack frame.
;MAIN program calling subroutines
ORG 0
MAIN: LCALL SUBR_1
LCALL SUBR_2
LCALL SUBR_3
HERE: SJMP HERE

;————————end of MAIN
;
Figure 3-1. 8051 SUBR_1: ....
....
Assembly Main RET
Program That Calls ;————————end of subroutine 1
;
Subroutines SUBR_2: ....
....
RET
;————————end of subroutine 2
SUBR_3: ....
....
RET
;————————end of subroutine 3
END ;end of the asm file
Example 3-11
A developer is using the Atmel AT89C1051 microcontroller chip for a product. This
chip has only 1K byte of on-chip flash ROM. Which instruction, LCALL or ACALL, is
more useful in programming this chip?
Solution:
The ACALL instruction is more useful since it is a 2-byte instruction. It saves one
byte each time the call instruction is used.
Example 3-12
Rewrite Example 3-8 as efficiently as you can.

Solution:
ORG 0
MOV A,#55H ;load A with 55H
BACK: MOV P1,A ;issue value in reg A to port 1
ACALL DELAY ;time delay
CPL A ;complement reg A
SJMP BACK ;keep doing this indefinitely
;————————this is the delay subroutine

DELAY:
MOV R5,#0FFH ;R5=255(FF in hex), the counter
AGAIN: DJNZ R5,AGAIN ;stay here until R5 becomes 0
RET ;return to caller
END ;end of asm file
I/O PORT PROGRAMMING
Timers-Counters in 8051 µC
• In Intel 8051, there are two 16-bit timer registers. These registers are known as Timer-0
and Timer-1.
• The same timer registers can be used as Timer as well as Counter.
• The only difference between timer and counter operation is the source for incrementing
the timer registers.
• Both Timer 0 and Timer 1 are 16 bits wide. Since 8051 has an 8-bit architecture, each
16-bits timer is accessed as two separate registers of low byte (TLx) and high byte
(THx). These are accommodated in SFR memory area as shown here.
• Timer/counter registers can be Accessed as follows,
MOV TL0,#4FH
MOV R5,TH0
• TCON and TMOD registers are used for timer/counter control and mode selection.
Timer/Counter-0 looks like this

as a 16-bit register.
Timers-Counters in 8051 µC
• The only difference between timer and counter operation is the source for incrementing the timer registers.
Timer operation
• In the timer mode, the internal machine cycles are counted. So the timer increments in
each machine cycle.
• Which means, the timer operating frequency is equal to machine cycle frequency i.e.
(1/12) of XTAL (clock) frequency.
Counter operation
• In the counter mode, the external events are counted. Here, the timer/counter register
will be incremented for each 1 to 0 transition of the external input pin T0 (for counter-0)
and T1 (for counter-1). These type of transitions are treated as events.
• The external input pins are sampled once in each machine cycle, and to determine the
1or 0 transitions, another machine cycle will be needed.
• So in counter mode, at least two machine cycles are needed to increment the counter.
Hence the maximum operating frequency of counter is equal to (1/24) of XTAL (clock)
frequency.
• The maximum frequency of counter can be varied with XTAL (Crystal oscillator)
frequency.
Timers-Counters in 8051 µC – Format of TCON register
• TCON (Timer Control) is an SFR. The address of this register is 88H. This is bit-addressable.
Timers-Counters in 8051 µC – Format of TMOD register
• TMOD (Timer Mode) is an SFR. The address of this register is 89H. This is not bit-addressable.
Bit Details High Value (1) Low Value (0)
C/T’ Configure for the Counter operations Configure for the Timer operations
Gate (G) Timer0 or Timer1 will be in RunMode when Timer0 or Timer1 will be in RunMode when
TRX bit of TCON register is high. TRX bit of TCON register is high
and INT0 or INT1 is high.
M1 M0 00 (Mode-0) 01 (Mode-1) 10 (Mode-2) 11 (Mode-3)
8-bit timer/counter, 16-bit 8-bit auto reload timer/counter; Split mode, Timer split
with 5-bit pre-scaler. timer/counter THx holds a value which is to be in to two separate 8-bit
(Total 13-bits in use) reloaded into TLx each time it timers.
overflows.
Timers-Counters in 8051 µC – Generating delay using Timers
DELAY generated by timer=(Max.value –Initial value+1)*(Time period of one machine cycle)
• max. value = maximum count value a timer/counter can reach (based on selected mode
in TMOD register)
• Initial value= the value we need to load into timer to the get the required delay.
• +1 is required in the above equation as timer increments one more time (to roll over to
Zero) after reaching its maximum value. After rollover the timer will stop and TF
(timer overflow) flog in TCON (Timer control) register is Set.
NOTE: 8051 timers works at a rate of 1/12 of the CLK (XTAL) frequency (equal
to machine cycle frequency).
• If XTAL frequency is 11.0592MHz, then the delay required/generated for each
count (pulse) is as follows,
(11.0592MHz/12)=926kHz=1.085µsec
Q1: Indicate which mode and which timer are selected for each of the following.
(a) MOV TMOD,#01H (b) MOV TMOD, #20H (c) MOV TMOD, #12H
A1:
(a) TMOD = 00000001, mode 1 of TIMER 0 and mode 0 of Timer 1 are selected.
(b) TMOD = 00100000, mode 2 of TIMER 1 and mode 0 of Timer 1 are selected.
(c) TMOD = 00010010, mode 2 of TIMER 0, and mode 1 of TIMER 1 are selected.
Q2: Find the timer’s clock frequency and it’s period for various 8051 based systems,
with the following crystal frequencies (a) 12MHz (b) 16 MHz (c) 11.0592 MHz
A2:
(a)
(b)
(c)
XTAL Divide by
Oscillator 12
Q3: In the following program, we create a square wave of 50% duty cycle (with
equal portions high and low) on the P1.5 bit. Timer 0 is used to generate the time
delay. Analyze the program
Steps to generate a time delay using TIMERs:
1. Load the TMOD value register indicating the which timer is to be used and which
timer mode is selected.
2. Load the registers TL and TH with initial count value
3. Start the Timer
4. Keep monitoring the timer flag (TF) with JNB TFx, target instruction to see if it is raised
Get out of the loop when TF becomes high
5. Stop the timer
6. Clear the TF flag for the next round
7. Go back to Step 2 to load TH and TL again
Q4: Calculate the amount of time delay in the DELAY subroutine by the timer. Assume XTAL =
11.0592MHz.
A4:
• The timer works with a clock frequency and time period of
• The number of counts = FFFF-FFF2+1 = 0E H = 14 Decimal

• Therefore, total amount of time delay for half pulse =
• The total amount of time delay for entire pulse = 30.38 µs

Q5: Calculate the frequency of the square wave generated on pin P1.5..
A5:
Q6: The following program generates a square wave on P1.5 continuously using timer
1 for a time delay. Find the frequency of the square wave if XTAL = 11.0592 MHz. (In
your calculation do not include the overhead due to instructions in the loop).
Q7: Assume that XTAL = 11.0592MHz. What value do we need to load the timer’s
register if we want to have a time delay of 5 ms? Show the program for timer 0 to
create a pulse width of 5 ms on P2.3.
Q8: Assume that XTAL = 11.0592MHz. Write a program to generate a square wave of
2KHz frequency on pin P1.5.
Program:
Q9: Examine the following program and find the time delay (Exclude overhead).
Q10: Assume XTAL = 11.0592 MHz, find the frequency of the square wave generated
on pin P1.0 in the following program
Solution:
• In mode 2 we do not need to reload TH since it is auto-reload.
• Now, (256 - 05) * 1.0851µs = 272.33 µs in the high portion of the pulse.
• Since it is a 50% duty cycle,
Total time period is = 2* 272.33 µs = 544.67 µs
• The frequency = 1/T = 1.83597 KHz
Q11: Assume that clock pulses are fed into pin T1, write a program for counter 1 in
mode 2 to count the pulses and display the state of the TL1 count on P2, which
connects to 8 LEDs.
Q12
SERIAL COMMUNICATION in 8051
Types of serial communication based on direction of data transfer.

SERIAL COMMUNICATION in 8051
Serial data communication uses two methods
• Synchronous method transfers a block of data at a time
• Asynchronous method transfers a single byte at a time
There are special IC chips made by many manufacturers for serial communications.
UART (universal asynchronous Receiver-transmitter)
USART (universal synchronous- asynchronous Receiver-transmitter)
• 8051 supports asynchronous serial communication since it is provided with on-chip UART.
• There are two 8051 pins namely TXD (P3.1) and RXD (P3.0), used for transmitting and
receiving serial data bits.
• There are two dedicated registers available in 8051 for serial communication. They are
Serial Buffer register (SBUF) and Serial Control register (SCON). Both are accommodated
in SFR memory area.
• SBUF is a shift register which is used to store the received data bits in serial
communication. Same register can be used to hold the data bits to transmit them serially.
• SCON register is used to control the serial communication.
SERIAL COMMUNICATION in 8051-Asynchronous-
data frame
Baud rate
• Baud rate defines the rate at which serial communication is happening.

• Baud rate means number of characters received/transmitted per second.
How to select required Baud rate
The list of supported baud rates by 8051 microcontroller is given bellow. Default frequency of
serial communication.
Baud rate (upon RESET)
9600
4800
2400 Timer-1 Mode-2
to set the Baud
1200 rate
• These baud rates can be derived from the default serial communication frequency of 8051.
• The default serial communication frequency is the (1/32) of machine cycle frequency (which
is 1/12 of XTAL frequency).
• The default serial communication frequency (28800 Hz here) will be divided with a factor to
get the required baud rate. The 2’s complement of division factor will be loaded in to Timer-1
in Mode-2. For the considered XTAL frequency of 11.0592MHz, default frequency is 28800 Hz.
Baud rate 9600 4800 2400 1200
Division factor 3 (28800/3=9600) 6 (28800/6=4800) 12 (28800/12=2400) 24 (28800/24=1200)
SERIAL COMMUNICATION in 8051-Asynchronous –
Baud rate selection with Timer-1 Mode-2
• The bellow table shows the 2’s complement representations of division factors for
respective baud rates.
• The 2’s complement values will be loaded in to TH1 of Timer-1 since it is in Mode-2 (8-
bit auto reload mode.)
• Then the timer divides the default serial communication frequency with loaded factor and
generate the required baud rate.
For the considered XTAL frequency of 11.0592MHz, default serial communication frequency is 28800 Hz.
• In Mode-2. higher byte of timer will be loaded with initial value, which will be then auto
loaded in to TL1 (lower byte). Now, TL1 start acting as the timer.
Baud rate selection with Timer-1 Mode-2
Why loading 2’s
complement: For
example, when
timer is loaded with
2’s complement of
the factor 3 i.e. FD
H, it will take
exactly 3 steps to
reach overflow (roll
over). After
overflow, timer will
divide the default
frequency i.e. 28800
with 3 to get 9600
baud.
SERIAL COMMUNICATION in 8051- SCON Register format
Serial Control (SCON) Register
SM0 SM1
1 0 Mode-2
This mode send/receive data between
multiprocessors. (environment where
communication between multiple
8051 processors is required.)
Mode-0 and 3 are used to choose
frame length with 9-data bits (old
method).
Serial Transmission -example program 1
Write a program for the 8051 to transfer letter ‘A’ serially at 4800 baud, continuously.
{2’s complement of -6 that is FA H will be loaded in to TH1 as a
Solution: division factor to get 4800 baud rate (28800/6=4800).}
MOV TMOD,#20H ;timer 1,mode 2(auto reload)
MOV TH1,#-6 ;4800 baud rate
CLR P3.1 ; making TXD pin as output port
From FA H, timer will
AGAIN: MOV SBUF,#'A' ;letter ‘A’ to transfer
take 6 steps to reach
HERE: JNB TI,HERE ;wait for the last bit
overflow (roll over).
CLR TI ;clear TI for sending next byte
Then it will divide the
SJMP AGAIN ;keep sending A
default value i.e. 28800
END
with 6 to get 4800 baud.
Serial Transmission -example program 2
Write a program for the 8051 to transfer “YES” serially at 9600 baud, 8-bit data, 1 stop bit, do this continuously
{2’s complement of -3 that is FD H will be loaded in to TH1 as a division factor to get
Solution: 9600 baud rate (28800/3=9600).}
MOV TMOD,#20H ;timer 1,mode 2(auto reload) • Since SBUF is an 8-bit register, it
can hold one character (8-bit
MOV TH1,#-3 ;9600 baud rate
ASCII) at a time. So, SBUF need
MOV SCON,#50H ;Mode-1 (8-bit, 1 stop), REN enabled
to be loaded with first character
and reload with another character
AGAIN: MOV A,#'Y' ;transfer 'Y'
after sending previous character.
ACALL TRANS
• From FD H, timer will take 3
MOV A,#'E' ;transfer 'E'
steps to reach overflow (roll
ACALL TRANS
over). Then it will divide the
MOV A,#'S' ;transfer 'S'
default value i.e. 28800 with 3 to
ACALL TRANS
get 9600 baud.
SJMP AGAIN ;keep doing it
;serial data transfer subroutine (sub program, will be called from the main program when ever required)
TRANS: MOV SBUF,A ;load SBUF
HERE: JNB TI,HERE ;wait for the last bit transmission (transmit interrupt TI=1)
CLR TI ;get ready for sending next byte after clearing TI
RET
Serial Reception -example program 3
Write a program for the 8051 to receive bytes of data serially, and put them in P1, set the baud
rate at 4800, 8-bit data, and 1 stop bit
Solution: {2’s complement of -6 that is FA H will be loaded in to TH1 as a division
factor to get 4800 baud rate (28800/6=4800).}
MOV TMOD,#20H ;timer 1,mode 2(auto reload) From FA H, timer will take 6 steps to
MOV TH1,#-6 ;4800 baud rate reach overflow (roll over). Then it will
MOV SCON,#50H ;8-bit, 1 stop, REN enabled divide the default value i.e. 28800 with
SETB TR1 ;start timer 1 6 to get 4800 baud.
HERE: JNB RI,HERE ;wait for the last bit to receive (receive interrupt RI=1)
MOV A,SBUF ;saving incoming byte in A
MOV P1,A ;send to port 1
CLR RI ;get ready to receive next byte after clearing RI
SJMP HERE ;go back and receive the next byte.
Power control register (PCON) of 8051
SMOD X X X GF1 GF0 PD IDL
Unused bits
PCON is an 8-bit special function register (SFR) accommodated in SFR memory area with an
address 87H. It is not bit addressable.
SMOD
This bit if set (1), it will double the baud rate of serial communication.
GF0 and GF1: These are general purpose flag bits.
Idle mode
• When IDL bit of the PCON register is set, the microcontroller turns off the CPU unit while
peripheral units such as serial port, timers and interrupt system continue operating normally.
• In Idle mode, the state of all registers and I/O ports remains unchanged.
• To exit the Idle mode, it is necessary to enable and execute any interrupt or reset.
• It is recommended that, first three instructions to be executed after coming out of Idle mode
are NOP instructions to stabilize the microcontroller and prevents undesired changes on the
I/O ports.
Power control register (PCON) of 8051
Power down mode

• By setting the PD bit of the PCON register within the program, the microcontroller enters
Power down mode.
• Internal oscillator will be turned off and reduces power consumption.
• The microcontroller can operate using only 2V power supply in power- down mode.
• The only way to get the micro controller back to normal mode is by reset.
• While the microcontroller is in Power Down mode, the state of all SFR registers and I/O
ports remains unchanged.
• By setting it back into the normal mode, the contents of the SFR register is lost, but the
content of internal RAM is saved.
• Reset signal must be long enough, approximately 10mS, to enable stable operation of the
quartz oscillator.

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Item 66/22 - Annexure - 18

Course Code Course Title L T P C

Module:1 Overview of Microprocessors 3 hours

Module:2 Microprocessor Architecture and Interfacing: Intel x86 8 hours

Module:3 Microcontroller Architecture: Intel 8051 7 hours

Module:4 Microcontroller 8051 Peripherals 5 hours

Module:5 I/O interfacing with Microcontroller 8051 7 hours

Module:6 ARM Processor Architecture 5 hours

Module:7 ARM Instruction Set 8 hours

Module:8 Contemporary issues 2 hours

Proceedings of the 66th Academic Council (16.06.2022) 396

Total Lecture hours: 45 hours

Proceedings of the 66th Academic Council (16.06.2022) 397

A microcontroller can serve several devices by two ways

Six interrupts are allocated in 8051, as follows;

• Priority bit=1 assigns high priority

• In the 8051, a low-priority interrupt can be interrupted by a higher-priority Interrupt.

;—-Upon wake-up go to main, avoid using memory space ;allocated to Interrupt

data from P0 and ;—-ISR for Timer 0 to generate square wave

creating a square ;—-The main program for initialization

XTAL = 11.0592 MHz.

ORG 30H ;starting location for prog.

IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to

Since these are basically LEDs arranged as a group they can

Common Cathode: In this type of segments all the cathode

Common Anode: In this type of segments all the anodes

(a) Vout = 5 V + (5 V x sin q) = 5 V + 5 x sin 30° = 5 V + 5 x 0.5 = 7.5 V

(b) Vout = 5 V + (5 V x sin q) = 5 V + 5 x sin 60° = 5 V + 5 x 0.866 = 9.33 V

0000 AND Rd=RN and OP2 Logical bitwise AND operation.

0001 EOR Rd = RN XOR OP2 Logical bitwise EXOR operation.

0010 SUB Rd = RN-OP2 Subtract

0011 RSB Rd=OP2-RN Reverse subtraction

0100 ADD Rd=RN+OP2 Addition

ORR This will perform bitwise OR operation. Ex: ORR R0,R0,R1

OPCODE MNEMONIC OPERATION PERFORMED BRIEF INTERPRETATION

0100 MI N is set Signed negative condition is checked

0110 VS V is set Occurrence of overflow is checked

1000 HI C is set & Z is cleared Unsigned greater than condition

1001 LS C is cleared or Z is set Unsigned less than or equal condition

1010 GE N equals V Signed greater than or equal condition

1011 LT N is not V Signed less than condition

1100 GT Z is cleared & N equals V Signed greater than

1101 LE Z is set & N not V Signed less than

1110 AL Unconditional checking (Occurs always)

1111 NV No change Never occurs

LDR This instruction is helpful in loading. The syntax can be:

MUL The syntax of MUL is:

LSR Its logical shift right.

This is post LSR.

1. Addition of two numbers using ARM instruction set

MUL Multiply MUL Rd, Rs MULS Rd, Rs,Rd

MVN Move NOT Register MVN Rd, Rs MVNS Rd, Rs

NEG Negate NEG Rd, Rs RSBS Rd, Rs,#0

ORR Logical OR ORR Rd,Rs ORRS Rd, Rd,Rs

POP It is used to POP registers POP {Rlist} LDMIA R13!, {Rlist}

PUSH It is used to PUSH registers PUSH {Rlist} STMDB R13!, {Rlist}

ROR Rotate Right ROR Rd, Rs MOVS Rd, Rd,ROR Rs

STMIA Store multiple STMIA Rb!, {Rlist} STMIA Rb!, {Rlist}

AREA PROG_2_1, CODE, READONLY

2. Perform Multiplication operations in ARM7

X 'DWD UHVLGHV LQ GDWD VHJPHQW (IIHFWLYH DGGUHVV FRPSX