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EEE 306 Post LAB 5

This post lab report describes behavioral modeling of circuits using Verilog. It includes: 1) Truth tables and minimized logic expressions for two circuits, F1 and F2. 2) Verilog code for behavioral models of each circuit. 3) Test benches are provided to simulate and verify the models against the truth tables.

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Abu Saleh Bin Aftab
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41 views11 pages

EEE 306 Post LAB 5

This post lab report describes behavioral modeling of circuits using Verilog. It includes: 1) Truth tables and minimized logic expressions for two circuits, F1 and F2. 2) Verilog code for behavioral models of each circuit. 3) Test benches are provided to simulate and verify the models against the truth tables.

Uploaded by

Abu Saleh Bin Aftab
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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East West University

EEE Department
Post LAB Report

Course Code: EEE 306


Course Title: Embedded Systems
Section:01
Experiment No:05
Title: Behavioral Modelling of Circuits with Verilog.
Name: Abu Saleh Bin Aftab Sakib
ID: 2020-2-80-019
Date of Submission:12/06/23

Course Instructor: Muhammed Mazharul Islam, Assistant Professor.


1.
a) Truth Table:
A B C F1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

b) F1(A, B, C) = A'. B + B.C' + B.C + A.B'.C'


= B (A' + C') + B.C + A.B'.C'
= B.A' + B.C' + B.C + A.B'.C'
= B.A' + B + A.B'.C'
= B.A' + B + A.C'
The simplified expression can be used as the behavioral model:
F1(A, B, C) = B.A' + B + A.C'
c)
ⅰ.Verilog Code:

module Behavioral Model (


input A, B, C,
output reg F1
);
always @ (A, B, C) begin
if (~A & B) begin
F1 = 1'b1;
end
else if (B & ~C) begin
F1 = 1'b1;
end
else if (B & C) begin
F1 = 1'b1;
end
else if (A & ~B & ~C) begin
F1 = 1'b1;
end
else begin
F1 = 1'b0;
end
end

endmodule

ⅱ. Gate Level Schematic


ⅲ. Technology Schematic

ⅳ. Truth Table
ⅴ. Text Bench Code
module threeinput;

// Inputs
reg A;
reg B;
reg C;

// Outputs
wire F1;

// Instantiate the Unit Under Test (UUT)


BehavioralModel uut (
.A(A),
.B(B),
.C(C),
.F1(F1)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
C = 0;

// Wait 100 ns for global reset to finish


#100;
A = 0;B = 0;C = 0;#50;
A = 0;B = 0;C = 1;#50;
A = 0;B = 1;C = 0;#50;
A = 0;B = 1;C = 1;#50;
A = 1;B = 0;C = 0;#50;
A = 1;B = 0;C = 1;#50;
A = 1;B = 1;C = 0;#50;
A = 1;B = 1;C = 1;#50;

// Add stimulus here

end

endmodule
ⅵ. Timing Diagram

2.
a) Truth Table:

A B C F2
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
b) F2(A, B, C) =(A+B). (A+C)
Apply the Distributive Law: A. (B + C) = A. B + A. C
F2(A, B, C) = A. (B + C) = A. B + A. C
F2(A, B, C) = A. B + A. C

The simplified expression can be used as the behavioral model:


F2(A, B, C) = A. B + A. C

c) ⅰ.
Code:
module bb(

input wire A,

input wire B,

input wire C,

output reg F2

);

always @(A or B or C)

begin

case (1'b1)

A: F2 = 1;

(B & C): F2 = 1;

default: F2 = 0;

endcase

end

endmodule
ⅱ. Gate Level Schematic

ⅲ.Technology Schematic
ⅳ. LUT (Truth table)

ⅴ. Text Bench Code


module bb;

// Inputs
reg A;
reg B;
reg C;

// Outputs
wire F2;

// Instantiate the Unit Under Test (UUT)


BehavioralModel uut (
.A(A),
.B(B),
.C(C),
.F2(F2)
);
initial begin

// Initialize Inputs

A = 0;

B = 0;
C = 0;

// Wait 100 ns for global reset to finish

#100;

A=0; B=0; C=1;

#50

A=0; B=1; C=0;

#50

A=0; B=1; C=1;

#50

A=1; B=0; C=0;

#50

A=1; B=0; C=1;

#50

A=1; B=1; C=0;

#50

A=1; B=1; C=1;

// Add stimulus here

end

endmodule
ⅵ. Timing Diagram

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