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Verilog Test-Bench

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43 views

Verilog Test-Bench

Uploaded by

garvitsrivastav2004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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More into Verilog

Digital Design
(ECE/EEE/INSTR F215)
Dr. Anita Agrawal
Test Bench Creation
Why test benches are required at all?

➢ To verify the functionality of the circuit


➢ To apply stimulus to the designed circuit

module test_bench;
Test Verilog ➢Declare local reg and wire identifiers
bench module ➢Instantiate the design module under test
➢Specify a stopwatch, using $finish to terminate the
reg input
simulation
wire output ➢Generate stimulus using initial and always
statements
endmodule

For details2023
16 November on keywords with $, refer Section 4.12, Fourth Edition, M. Morris Mano et al.
Ruma Ghosh 2
Example

Q. Simulate a half adder design

(a)without using test bench


(b)Using test bench
Simulation Output without test bench
Test Bench Code for Half Adder
module Half_Adder;
reg A;
reg B; // Inputs

wire S;
wire C; // Outputs

initial begin
A = 0;
B = 0;
#100 A = 0;
#100 B = 1;
#100 A = 1;
#100 B = 0;
#100 A = 1;
#100 B = 1;
end
endmodule
Your Exercise

Q. Write a test bench code for

(a)Full adder
(b)4-bit Odd parity checker
Behavioral Model
✓Highest level of abstraction in HDL
✓Here any function or behavior of any digital system/gate is defined

1. Initial : Executed only once in simulation, time 0


initial begin
statement 1;
statement 2;
end

2. Always : Executed in an infinite loop


(a) always begin
statement 1;
statement 2;
end
(b) always @ (control event check)
begin
statements;
end
Example of ‘initial’ and ‘always’
constructs
module behavioral ();
reg a, b;
initial
begin
a = 1’b1;
b = 1’b0;
end
always
begin
#50 a = ~a;
end
always
begin
#100 b = ~b;
end
endmodule
3. Block statements
(a) Sequential block
✓ Uses begin and end keywords
(b) Parallel block
✓ Uses fork and join keywords ( refer from text book)

4. Conditional statement (if-else)


Difference between Data Flow and
Behavioral Model

Q. Write a verilog code for 2:1 MUX using

(a)Data Flow model


(b)Behavioral model
Data flow Model Behavioral Model

module 2_1_mux_struct (out, A, B, select); module 2_1_mux_behav(out, A, B, select);


output out; output out;
input select, A, B; input select, A, B;
assign out = select?B:A; reg out;
endmodule
always @ (A, B, select)
begin
if (select==0) out=A;
else out=B;
end
endmodule
Your Reading Assignments

Section 4.12, 5.6, 6.6: Registers not included.

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