Unit- 4

(Current Mirrors and differential Amplifiers)

4.1 Basic current mirror:

Why do we need current Mirrors?
Let us try to understand why current mirrors are very important in Analog circuit design. Let us
assume that the MOSFET M1 is biased using voltage divider network as shown in Fig.1

Fig.1

Let Iout be the current through M1 as shown in the above diagram and M1 is biased in saturation
region. Since M1 is in saturation region the output current through the device Iout can be expressed
using following expression,

in the above expression since the overdrive voltage is a function of VDD, threshold voltage (generally
this voltage vary from 50mV to 100mV from one wafer to other wafer) and both mobility of charge
Carriers and the threshold voltage exhibit temperature dependencies the output current of the MOS
device M1 does not remain constant at the required level which leads to biasing issues. To overcome
these issues related with voltage divider bias, Current Mirror Circuits are used in IC design.

Since the MOSFET M1 in Fig.1 is biased in the saturation region it acts like a constant current source
and in case of analog circuit design constant Current sources are based on copying currents from
the "Golden" reference (Bandgap Reference Circuits)which is already available, pictorial
representation is as shown below Fig.2

1
Analog Circuit Design
 Fig. 2

How do we generate copies of a reference current?

For a MOSFET, if ID = f (VGS), where f (·) denotes the dependence of ID upon VGS, then VGS = f −1 (ID).
That is, if a transistor is biased at IREF, then it produces VGS = f −1(I REF) [Fig. 3(a)]. Thus, if this voltage
is applied to the gate and source terminals of a second MOSFET, the resulting current is Iout = f [f
−1(I
REF )] = I REF [Fig. 3(b)]. From another point of view, two identical MOS devices that have equal

gate-source voltages and operate in saturation carry equal currents (if λ = 0).

Fig.3

The structure consisting of M1 and M2 in Fig. 3.(b) is called a “current mirror.” In the general case,
the transistors need not be identical. Neglecting channel-length modulation, we can write
1 𝑊
𝐼𝑅𝐸𝐹 = 𝜇𝑛 𝐶𝑜𝑥 ( 𝐿 ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 1

1 𝑊
𝐼𝑜𝑢𝑡 = 𝜇𝑛 𝐶𝑜𝑥 ( ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 𝐿 2

Obtaining

𝑊
( )
𝐿 2
𝐼𝑜𝑢𝑡 = ( 𝑊 ) 𝐼𝑅𝐸𝐹
( )
𝐿 1

2
Analog Circuit Design
The key property of this topology is that it allows precise copying of the current with no dependence
on process and temperature. The translation from IREF to Iout merely involves the ratio of device
dimensions, a quantity that can be controlled with reasonable accuracy.

Sizing Issues:

Suppose we wish to copy a reference current, IREF, and generate 2IREF. We begin with a width of WREF
for the diode-connected reference transistor and hence choose 2 WREF for the current source [Fig.
4(a)]. We thus prefer to employ a “unit” transistor and create copies by repeating such a device as
shown in [Fig. 4(b)].

Fig.4
(a) Fig.4 (b)

4.2 Cascode Current Mirrors:

In our discussion of current mirrors thus far, we have neglected channel-length modulation (CLM).
In practice, this effect produces significant error in copying currents, especially if minimum-length
transistors are used. Taking CLM in to account we can write expressions for drain current as follows
(Refer Fig. 3(b))
1 𝑊
𝐼𝐷1 = 𝜇 𝐶 ( ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (1 + 𝜆𝑉𝐷𝑆1 )
2 𝑛 𝑜𝑥 𝐿 1
1 𝑊
𝐼𝐷2 = 𝜇𝑛 𝐶𝑜𝑥 ( ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (1 + 𝜆𝑉𝐷𝑆2 )
2 𝐿 2

And hence
𝑊
𝐼𝐷2 ( ) (1+𝜆𝑉 )
𝐿 2
=𝑊 . (1+𝜆𝑉𝐷𝑆2 )
𝐼𝐷1 ( ) 𝐷𝑆1
𝐿 1

While VDS1 = VGS1 = VGS2, VDS2 may not equal VGS2, which leads to significant error in copying currents.
Now the question is how to suppress the effect of CLM in Fig. 3(b)? We know that, cascode device
can shield a current source, thereby reducing the voltage variations across it. As shown in Fig. 5(a),
even though the analog circuit may allow VP to vary substantially, VY remains relatively constant. But
how do we ensure that VDS2 = VDS1? We must generate Vb such that Vb − VGS3 = VDS1 (= VGS1), i.e., Vb
3
Analog Circuit Design
= VGS3 + VGS1. In other words, Vb can be established by two diode-connected devices in series [Fig.
5(b)], provided that VGS0 + VGS1 = VGS3 + VGS1, and hence VGS0 = VGS3. We now attach the Vb generator
of Fig. 5(b) to the cascode current source as shown in Fig. 5(c). The result allows accurate copying
of the current.

Fig. 5(a) Fig. 5(b) Fig. 5(c)

Note1:

Sizing of the transistors in Fig. 5(c) are warranted. We typically select L2 = L1 and scale W2 (in integer
units) with respect to W1 to obtain the desired multiple of IREF. Similarly, for VGS3 to be equal to VGS0,
we choose L3 = L0 and scale W 3 with respect to W0 by the same factor, i.e., (W3 /W0) = (W2 /W1) . In
practice, L3 and L0 are equal to the minimum allowable value so as to minimize their width.

Note2: Even though the Cascode topology is characterized by High output impedance and accurate
value the topology of Fig. 5(c) nonetheless consumes substantial voltage headroom. For simplicity,
let us neglect the body effect and assume that all of the transistors are identical. Then, the minimum
allowable voltage at node P is equal to,

Fig. 6(a) Fig. 6(b)

i.e., two overdrive voltages plus one threshold voltage. How does this value compare with that in
Fig. 5(a) if Vb could be chosen more arbitrarily? As shown in Fig. 6(a), Vb could be so low (= VGS3 +

4
Analog Circuit Design
VGS2 − VTH2) that the minimum allowable voltage at P is merely two overdrive voltages. Thus, the
cascode mirror of Fig. 5(c) “wastes” one threshold voltage in the headroom. This is because VDS2 =
VGS2, whereas VDS2 could be as low as VGS2 − VTH while maintaining M2 in saturation. In Fig. 6(b), a
higher accuracy is achieved, but the minimum level at P is higher by one threshold voltage.

4.3 Active Current Mirrors:

The Current Mirrors can be also used to process the signals, that is we can operate Current Mirrors
as Passive/Active Loads and these topologies are used in conjunction with differential pairs as
shown in Fig.7 (a)

Fig. 7(a) Fig. 7(b) Fig. 7(c)

To generate a single-ended output, we may simply discard one output of a differential pair as shown
in Fig. 7(a). Here, a current source in a “passive” mirror arrangement serves as the load. Now to find
the small-signal gain, Av = Vout /Vin, of this circuit we can use the lemma |Av | = Gm Rout.

To compute the short-circuit transconductance, Gm, from Fig.7 (b). We recognize that M1 and M2
become symmetric when the output is shorted to ac ground. Thus,

Gm= Iout/Vin = (gm1Vin /2) / Vin = g m1/ 2

As illustrated in Fig. 7(c), for the Rout calculation, M2 is degenerated by the source output impedance
of M1, Rdeg = (1/g m1) ||rO1, thereby exhibiting an output impedance equal to

(1+gm2 r 2)R deg + r O2 ≈ 2rO2

It follows that Rout = (2rO2) ||rO4

and

5
Analog Circuit Design
4.4 Differential Pair with Active Load
In the circuit of Fig. 7(a), the small-signal drain current of M1 is “wasted.” As conceptually shown in
Fig. 8(a), it is desirable to utilize this current with proper polarity at the output. This can be
accomplished by the Circuit shown in Fig. 8(b), where M 3 and M4 are identical and operate as an
active current mirror.

To see how M3 enhances the gain, suppose the gate voltages of M1 and M2 change by equal and
opposite amounts [Fig. 8(c)]. Consequently, ID1 increases, VF falls, and ID2 decreases. Thus, the output
voltage rises by means of two mechanisms: M2 draws less current from X to ground and M4 pushes
a greater current from VDD to X. By contrast, in the circuit of Fig. 7(a), M4 plays no active role in
changing Vout because its gate voltage is constant. The Circuit is also called a differential pair with
active load.

Fig.8 (a) Fig.8 (b) Fig.8(c)

Large-Signal Analysis of Differential pair with Active Current Mirror: The current source in Fig. 8(c)
is replaced by a MOSFET as shown in Fig. 9(a). If Vin1 is much more negative than Vin2, M1 is off, and
so are M3 and M4. Since no current can flow from VDD, both M2 and M5 operate in the deep triode
region, carrying zero current. Thus, Vout = 0. As Vin1 approaches Vin2, M1 turns on, drawing a fraction
of ID5 from M3 and turning M4 on. The output voltage then depends on the difference between ID4
and ID2. For a small difference between Vin1 and Vin2, both M2 and M4 are saturated, providing a high
gain [Fig. 9(b)]. As Vin1 becomes more positive than Vin2, ID1, |I D3 |, and |I D4 | increase and I D2
decreases, allowing Vout to rise and eventually driving M4 into the triode region. If Vin1 − Vin2 is
sufficiently large, M2 turns off, M4 operates in the deep triode region with zero current, and Vout =
VDD.

Fig.9 (a) Differential pair with Active Current Mirror Fig.9 (b) large-signal input-output characteristic.

6
Analog Circuit Design
Note1: If Vin1 > VF + VTH, then M1 enters the triode region. Also, Vout is in-phase with respect to Vin1
but 180◦ out of phase with respect to Vin2.

Note2: Critical Drawback: For M2 to be saturated, the output voltage cannot be less than V in, CM−
VTH. Thus, to allow maximum output swings, the input CM level must be as low as possible, with the
minimum given by VGS1,2 + VDS5,min .The constraint imposed by the input CM level upon the output
swing in this circuit is a critical drawback.

Note3: This Circuit proves useful as a differential to a single-ended converter for large swings.

Small-Signal Analysis: To analyse the small-signal properties of the circuit shown in Fig. 9(a), let us
assume γ = 0 for simplicity. Using approximate analysis and the lemma |Av | = Gm Rout, let us evaluate
the small signal gain as follows.

For the calculation of Gm, consider Fig.10(a). The circuit is not quite symmetric, but because the
impedance seen at node F is relatively low and the swing at this node is small, the current returning
from F to P through rO1 is negligible, and node P can be approximated by a virtual ground [Fig. 10(b)].
Thus, ID1 = |I D3 | = |I D4 | = gm1,2Vin /2 and ID2 = −g m1,2Vin /2, yielding Iout = −gm1,2Vin , and hence |Gm
| = gm1,2 . Note that, by virtue of active current mirror operation, this value is twice the
transconductance of the circuit of Fig. 7(b).

Fig.10(a) Fig.10(b)

For the Calculation of Rout, consider the following circuits,

Fig.11 (a)

Fig.11 (b)

7
Analog Circuit Design
The current flowing into M1 must flow out of M2, and the role of the two transistors can be
represented by a resistor RXY = 2rO1,2 [Fig. 11(b)]. As a result the current drawn from VX by RXY is
mirrored by M3 onto M4 with unity gain. This current is equal to,

VX / [2r O1,2 + (1/gm3)||rO3 ]

and hence I x is equal to,

The overall voltage gain is approximately equal to |Av | = Gm Rout = gm1,2 (rO2|| rO4), somewhat higher
than that of the differential pair with passive load (Fig.7 (a)).

4.5 Common-Mode Properties: In this case our objective is to predict the consequences of a
finite output impedance in the tail current source. As depicted in Fig. 12 change in the input CM
level leads to a change in the bias current of all of the transistors. In this circuit [Fig.12] the output
signal of interest is sensed with respect to ground. Thus, we define the CM gain in terms of the single
ended output component produced by the input CM change as,

Fig.(12)

To determine ACM, we observe that if the transistors are symmetric, Vout = VF for any input CM level.
For example, as Vin, CM increases, VF drops and so does Vout. In other words, nodes F and X can be

8
Analog Circuit Design
shorted [Fig. 13(a)], resulting in the equivalent circuit shown in Fig. 13(b). Here, M 1 andM2 appear
in parallel and so do M3 and M4. It follows that

Fig.13 (a) Fig.13 (b)

Where we have assumed that 1/ (2g m3, 4) << rO3, 4 and neglected the effect of rO1, 2 /2. The CMRR is
then given by,

9
Analog Circuit Design
The final expression indicates that, even with perfect symmetry, the output signal is corrupted by
input CM variations. High-frequency common-mode noise therefore degrades the performance
considerably as the capacitance shunting the tail current source exhibits a lower impedance.

Problems: (Solved Examples)

Example1:

In the following circuit, find the drain current of M 4 if all of the transistors are in saturation.

Solution:

We have ID2 = IREF [(W/L) 2 / (W/L) 1]. Also, |ID3 | = |ID2 | and ID4 = ID3 × [(W/L) 4 / (W/L) 3]. Thus, |I D4 |
= αβ IREF , where α = (W/L) 2 / (W/L) 1 and β = (W/L) 4 / (W/L) 3. Proper choice of α and β can establish
large or small ratios between ID4 and IREF . For example, α = β = 5 yields a magnification factor of 25.
Similarly, α = β = 0.2 can be utilized to generate a small, well-defined current.

Example 2: Calculate the small-signal voltage gain of the circuit shown below.

Solution: The small-signal drain current of M1 is equal to g m1Vin . Since ID2 = ID1 and ID3 = ID2 (W/L) 3 /
(W/L) 2, the small-signal drain current of M3 is equal to gm1Vin (W/L) 3 / (W/L) 2, yielding a voltage
gain of

Av= gm1RL (W/L) 3 / (W/L) 2

10
Analog Circuit Design
Example 3:

In following diagram, sketch VX and VY as a function of IREF. If IREF requires 0.5 V to operate as a current
source, what is its maximum value?

Solution:

Since M2 and M3 are properly ratioed with respect to M1 and M0, we have,

2𝐼𝑅𝐸𝐹
𝑉𝑌 = 𝑉𝑌 ≈ √ + VTH1
𝜇 𝑛 𝐶𝑜𝑥 (W/L) 1

The behaviour is plotted as shown,

Also we now that,

𝑉𝑁 = 𝑉𝐺𝑆0 +𝑉𝐺𝑆1
2𝐼𝑅𝐸𝐹 𝐿 𝐿
= √
𝜇
[√(𝑊) + √(𝑊) ] +𝑉𝑇𝐻0 + 𝑉𝑇𝐻1
𝑛 𝐶𝑜𝑥 0 1

Thus

2𝐼𝑅𝐸𝐹 𝐿 𝐿
𝑉𝐷𝐷 − √ [√(𝑊) + √(𝑊) ] - 𝑉𝑇𝐻0 − 𝑉𝑇𝐻1 = 0.5V
𝜇𝑛 𝐶𝑜𝑥 0 1

11
Analog Circuit Design
And hence,
𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐷𝐷 −0.5𝑉−𝑉𝑇𝐻0 −𝑉𝑇𝐻1 )2
𝐼𝑅𝐸𝐹,𝑀𝐴𝑋 = 2
2 𝐿 𝐿
[√( ) + √( ) ]
𝑊 𝑊
0 1

Example 4:

Assuming perfect symmetry, sketch the output voltage of the circuit shown, as VDD varies from 3 V
to zero. Assume that for VDD = 3 V, all of the devices are saturated.

Solution:

For VDD = 3 V, symmetry requires that Vout = VF. As VDD drops, so do VF and Vout with a slope close to
unity [as shown in the plot below]. As VF and Vout fall below +1.5 V −VTHN, M1 and M2 enter the triode
region, but their drain currents are constant if M 5 is saturated. Further decrease in VDD and hence
VF and Vout causes VGS1 and VGS2 to increase, eventually driving M5 into the triode region. Thereafter,
the bias current of all of the transistors drops, lowering the rate at which V out decreases. For VDD <
|VTHP |, we have Vout = 0.

12
Analog Circuit Design
Differential Amplifiers:
4.6 Single-Ended and Differential Operation:
A “single-ended” signal is defined as one that is measured with respect to a fixed potential, usually
the ground [Fig. 14(a)]. A differential signal is defined as one that is measured between two nodes
that have equal and opposite signal excursions around a fixed potential [Fig.14 (b)]. In the strict
sense, the two nodes must also exhibit equal impedances to that potential. The “center” potential
in differential signaling is called the “common-mode” (CM) level. It is helpful to view the CM level
as the bias value of the voltages, i.e., the value in the absence of signals.

Fig. 14(a) Fig. 14(b)

An important advantage of differential operation over single-ended signalling is higher immunity to

“environmental” noise. Consider the following case [Fig. 14(a)], where two adjacent lines in a circuit
carry a small, sensitive signal and a large clock waveform. Due to capacitive coupling between the
lines, transitions on line L2 corrupt the signal on line L1. Now suppose, as shown in [Fig. 14(b)], the
sensitive signal is distributed as two equal and opposite phases. If the clock line is placed midway
between the two, the transitions disturb the differential phases by equal amounts, leaving the
difference intact. Since the common-mode level of the two phases is disturbed, but the differential
output is not corrupted, we say that this arrangement “rejects” common-mode noise

Fig. 14(a) Fig. 14(b)

13
Analog Circuit Design
Another example of common-mode rejection occurs with noisy supply voltages. In the CS stage of
Fig.15.(a), if VDD varies by small amount , then Vout changes by approximately the same amount, i.e.,
the output is quite susceptible to noise on VDD. Now consider the circuit in Fig. 15 (b). Here, if the
circuit is symmetric, noise on VDD affects VX and VY, but not VX − VY = Vout. Thus, the circuit of Fig.15.
(b) is much more robust in dealing with supply noise.

Fig.15 (a) Fig.15 (b)

Another useful property of differential signaling is the increase in maximum achievable voltage
swings. In the circuit of Fig.15, for example, the maximum output swing at X or Y is equal to V DD −
(VGS − VT H), whereas for VX − VY, the peak-to-peak swing is equal to 2[VDD − (VGS − VTH)]. Other
advantages of differential circuits over their single-ended counterparts include simpler biasing and
higher linearity. While differential circuits may occupy about twice as much area as single-ended
alternatives, in practice this is a minor drawback. The numerous advantages of differential operation
by far outweigh the possible increase in the area.

4.7 Basic Differential Pair: How do we amplify a differential signal? Two differential inputs, Vin1
and Vin2, having a certain CM level, Vin, CM, are applied to the gates as shown [Fig.16(a)].The outputs
are also differential and swing around the output CM level, Vout, CM. As the input CM level, Vin, CM,
changes, so do the bias currents of M1 and M2, thus varying both the transconductance of the
devices and the output CM level. The variation of the transconductance, in turn, leads to a change
in the small-signal gain. If the input CM level is excessively low, the minimum values of Vin1 and Vin2
may in fact turn off M1 and M2, leading to severe clipping at the output [Fig 16(b)]. Thus, it is
important that the bias currents of the devices have minimal dependence on the input CM level.

Fig.16 (a) Fig. 16(b)

14
Analog Circuit Design
To overcome this issue, Shown in Fig.17, the “differential pair” employs a current source ISS to make
ID1 + ID2 independent of Vin, CM. Thus, if Vin1 = Vin2, the bias current of each transistor equals ISS/2 and
the output common-mode level is VDD – (RD ISS)/2.

Fig.17

Qualitative Analysis:

Let us assume that [Fig. 17], Vin1 − Vin2 varies from −∞ to +∞. If Vin1 is much more negative than Vin2,
M1 is off, M2 is on, and ID2 = ISS. Thus, Vout1 = VDD and Vout2 = VDD − RD ISS. As Vin1 is brought closer to
Vin2, M1 gradually turns on, drawing a fraction of ISS from RD1 and hence lowering Vout1. Since ID1 +
ID2 = ISS, the drain current of M2 falls and Vout2 rises. As shown in Fig. 18(a), for Vin1 = Vin2, we have
Vout1 = Vout2 = VDD − RD ISS/2, which is the output CM level. As Vin1 becomes more positive than V in2,
M1 carries a greater current than does M2 and Vout1 drops below Vout2. For sufficiently large Vin1 −
Vin2, M1 “hogs” all of ISS, turning M2 off. As a result, Vout1 = VDD − RD ISS and Vout2 = VDD. Note that the
circuit contains three differential quantities: Vin1 − Vin2, Vout1 − Vout2, and ID1 − ID2.

Fig. 18(a) fig.18 (b)

15
Analog Circuit Design
4.8 Common-mode behavior:
As mentioned earlier, the role of the tail current source is to suppress the effect of input CM level
variations on the operation of M1 and M2 and the output level. Does this mean that Vin,CM can
assume arbitrarily low or high values? To answer this question, we set Vin1 = Vin2 = Vin,CM and vary
Vin,CM from 0 to VDD.

What happens if Vin,CM = 0? Since the gate potential of M1 and M2 is not more positive than their
source potential, both devices are off, yielding ID3 = 0. This indicates that M3 operates in the deep
triode region because Vb is high enough to create an inversion layer in the transistor. With ID1 = ID2
= 0, the circuit is incapable of signal amplification, Vout1 = Vout2 = VDD, and VP = 0.

Now suppose Vin,CM becomes more positive. Modeling M3 by a resistor as in Fig. 19 (b), we note
that M1 and M2 turn on if Vin,CM ≥ VT H. Beyond this point, ID1 and ID2 continue to increase, and
VP also rises [Fig. 19 (c)]. In a sense, M1 and M2 constitute a source follower, forcing VP to track
Vin,CM. For a sufficiently high Vin,CM, the drain-source voltage of M3 exceeds VGS3 − VT H3,
allowing the device to operate in saturation. The total current through M1 and M2 then remains
constant. We conclude that for proper operation, Vin,CM ≥ VGS1 + (VGS3 − VT H3).

Fig.19(a) Fig.19(b)

Fig.19(c)

What happens if Vin,CM rises further? Since Vout1 and Vout2 are relatively constant, we expect that
M1 and M2 enter the triode region if Vin,CM > Vout1 + VT H = VDD − RD ISS/2 + VT H. This sets an
upper limit on the input CM level. In summary, the allowable value of Vin,CM is bounded as follows:
16
Analog Circuit Design
Beyond the upper bound, the CM characteristics of Fig. 19(c) do not change, but the differential gain
drops.

Now the question is, How large can the output voltage swings of a differential pair be? Suppose the
circuit is biased with input and output bias levels Vin,CM and Vout,CM, respectively, and Vin,CM <
Vout,CM. Also, assume that the voltage gain is high, that is, the input swing is much less than the
output swing. As illustrated in Fig. 20, for M1 and M2 to be saturated, each output can go as high as
VDD but as low as approximately Vin,CM − VT H. In other words, the higher the input CM level, the
smaller the allowable output swings. For this reason, it is desirable to choose a relatively low Vin,CM,
but, of course, no less than VGS1 + (VGS3 − VT H3). Such a choice affords a single-ended peak-to-
peak output swing of VDD −(VGS1 − VT H1)−(VGS3 − VT H3) (why?). The reader is encouraged to
repeat this analysis if the voltage gain is around unity.

FIG. 20

4.9 Small-Signal Analysis:

If a fully-symmetric differential pair senses differential inputs (i.e., the two inputs change by equal
and opposite amounts from the equilibrium condition), then the concept of “half circuit” can be
applied. We first prove a lemma.

Lemma Consider the symmetric circuit shown in Fig. 21(a), where D1 and D2 represent any three
terminal active device. Suppose Vin1 and Vin2 change differentially, the former from V0 to V0 +_Vin
and the latter from V0 to V0 − _Vin [Fig. 21 (b)]. Then, if the circuit remains linear, VP does not
change. Assume λ = 0.

17
Analog Circuit Design
 Fig.21(a) Fig.21(b) Fig.21(c)

Proof. The lemma can be proved by invoking symmetry. As long as the operation remains linear, so
that the difference between the bias currents of D1 and D2 is negligible, the circuit is symmetric.
Thus, VP cannot “favor” the change at one input and “ignore” the other.

From another point of view, the effect of D1 and D2 at node P can be represented by Thevenin
equivalents (Fig. 22). If VT 1 and VT 2 change by equal and opposite amounts and RT 1 and RT 2 are
equal, then VP remains constant. We emphasize that this is valid if the changes are small enough
that we can assume RT 1 = RT 2 (e.g., 1/gm1 = 1/gm2).6 This perspective suggests the lemma’s
validity even if the tail current source is not ideal.

Fig.22

We now offer a more formal proof. Let us assume that V1 and V2 have an equilibrium value of Va
and change by ΔV1 and ΔV2, respectively [Fig. 4.20(c)]. The output currents therefore change by
gmΔV1 and gmΔV2. Since I1 + I2 = IT, we have gmΔV1 + gmΔV2 = 0, i.e., ΔV1 = −ΔV2. We also know
that Vin1 − V1 = Vin2 − V2, and hence V0 +ΔVin −(Va +ΔV1) = V0 −ΔVin −(Va +ΔV2). Consequently,
2ΔVin = ΔV1−ΔV2 = 2ΔV1. In other words, if Vin1 and Vin2 change by+ ΔVin and −ΔVin, respectively,
then V1 and V2 change by the same values, i.e., a differential change in the inputs is simply
“absorbed” by V1 and V2. In fact, since VP = Vin1−V1, and since V1 exhibits the same change as Vin1,
VP does not change.

The above lemma greatly simplifies the small-signal analysis of differential amplifiers. As shown in
Fig. 23, since VP experiences no change, node P can be considered “ac ground” (or a “virtual
ground”), and the circuit can be decomposed into two separate halves. We say that we have applied
the “half-circuit concept” [1]. We can write VX /Vin1 = −gm RD and VY /(−Vin1) = −gm RD, where
Vin1 and −Vin1 denote the voltage change on each side. Thus, (VX − VY )/(2Vin1) = −gm RD.

18
Analog Circuit Design
 Fig.23(a) Fig.23(b)

4.10 Common-Mode Response:

We first assume that the circuit is symmetric, but the current source has a finite output impedance,
RSS [Fig. 24(a)]. As Vin,CM changes, so does VP , thereby increasing the drain currents of M1 and
M2 and lowering both VX and VY . Owing to symmetry, VX remains equal to VY and, as depicted in
Fig. 24(b), the two nodes can be shorted together. Since M1 and M2 are now “in parallel,” i.e., they
share all of their respective terminals, the circuit can be reduced to that in Fig. 24 (c). Note that the
composite device, M1 + M2, has twice the width and the bias current of each of M1 and M2 and,
therefore, twice their transconductance. The “common-mode gain” of the circuit is thus equal to,

Where gm denotes the transconductance of each of M1 and M2 and λ = γ = 0.

Fig. 24(a) Fig. 24(b) Fig. 24(c)

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Analog Circuit Design
How significant is common-mode to differential conversion?

To understand this Let us study the asymmetry resulting from mismatches between M1 and M2 in
Fig. 25(a). Owing to dimension and threshold voltage mismatches, the two transistors carry slightly
different currents and exhibit unequal transconductances. We assume that λ = γ = 0. To calculate
the small-signal gain from Vin,CM to X and Y , we use the equivalent circuit in Fig. 25(b), writing ID1
= gm1(Vin,CM − VP ) and ID2 = gm2(Vin,CM − VP ). Since (ID1 + ID2)RSS = VP ,

Fig. 25(a) Fig. 25(b)

And

We now obtain the output voltages as,

And

The differential component at the output is therefore given by

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Analog Circuit Design
The circuit converts input CM variations to a differential error by a factor equal to

Where ACM−DM denotes common-mode to differential-mode conversion and Δgm = gm1 − gm2.

Now, we define the “common-mode rejection ratio” (CMRR) as the desired gain divided by the
undesired gain:

Where gm denotes the mean value, that is, gm = (gm1+gm2)/2.

4.11 Differential Pair with MOS Loads:

The load of a differential pair need not be implemented by linear resistors. Differential pairs can
employ diode-connected or current-source loads (Fig. 26(b)). The small-signal differential gain can
be derived using the half-circuit concept.

Fig. 26(a) Fig. 26(b)

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Analog Circuit Design
For Fig. 26(a),

For Fig. 4.37(b), we have

In the circuit of Fig. 4.37(a), the diode-connected loads consume voltage headroom, thus creating a
trade-off between the output voltage swings, the voltage gain, and the input CM range. To achieve
a higher gain, (W/L)P must decrease, thereby increasing |VGSP − VT HP| and lowering the CM level
at nodes X and Y .

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Analog Circuit Design