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Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018
1.Arrive on time, every time (Max delay is 15 minutes then the door
will be closed)
Operating System Concepts – 10th Edition 9.2 Silberschatz, Galvin and Gagne ©2018
Course Plan
Lecture # Content
Orientation
Lecture 1
Chapter 1: Introduction
Lecture 2
Chapter 2: Operating-System Services
Lecture 3
Lecture 4
Chapter 3: Processes
Lecture 5
Lecture 7
Chapter 5: CPU Scheduling
Lecture 8
Operating System Concepts – 10th Edition 9.3 Silberschatz, Galvin and Gagne ©2018
Chapter 9: Memory Management
▪ Background
▪ Paging
▪ Swapping
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Background
▪ Program must be brought (from disk) into memory and placed within a
process for it to be run
▪ Main memory and registers are only storage CPU can access directly
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Protection
▪ Need to ensure that a process can access only those addresses in
its address space.
▪ We can provide this protection by using a pair of base and limit
registers define the logical address space of a process
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Hardware Address Protection
▪ CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user
▪ the instructions to loading the base and limit registers are privileged
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Address Binding
▪ Programs on disk, ready to be brought into memory to execute form
an input queue
• Without support, must be loaded into address 0000
▪ Inconvenient to have first user process physical address always at
0000
• How can it not be?
▪ Addresses represented in different ways at different stages of a
program’s life
• Source code addresses usually symbolic
• Compiled code addresses bind to relocatable addresses
i.e., “14 bytes from beginning of this module”
• Linker or loader will bind relocatable addresses to absolute
addresses
i.e., 74014
• Each binding maps one address space to another
Operating System Concepts – 10th Edition 9.8 Silberschatz, Galvin and Gagne ©2018
Binding of Instructions and Data to Memory
▪ Address binding of instructions and data to memory addresses
can happen at three different stages
• Execution time: Binding delayed until run time if the process can
be moved during its execution from one memory segment to
another
Need hardware support for address maps (e.g., base and limit
registers)
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Multistep Processing of a User Program
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Logical vs. Physical Address Space
▪ The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management
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Memory-Management Unit (MMU)
▪ Hardware device that at run time maps virtual to physical address
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Memory-Management Unit (Cont.)
▪ The user program deals with logical addresses; it never sees the real
physical addresses
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Memory-Management Unit (Cont.)
▪ Consider simple scheme. which is a generalization of the base-
register scheme.
▪ The base register now called relocation register
▪ The value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
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Contiguous Allocation
▪ Main memory must support both OS and user processes
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Hardware Support for Relocation and Limit Registers
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Variable Partition
▪ Multiple-partition allocation
• Degree of multiprogramming limited by number of partitions
• Variable-partition sizes for efficiency (sized to a given process’ needs)
• Hole – block of available memory; holes of various size are scattered
throughout memory
• When a process arrives, it is allocated memory from a hole large enough to
accommodate it
• Process exiting frees its partition, adjacent free partitions combined
• Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
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Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
▪ Worst-fit: Allocate the largest hole; must also search entire list
First-fit and best-fit better than worst-fit in terms of speed and storage
utilization
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Fragmentation
▪ First fit analysis reveals that given N blocks allocated, 0.5 N blocks
lost to fragmentation
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Fragmentation (Cont.)
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Fragmentation (Cont.)
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Paging
▪ Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
▪ Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
▪ Divide logical memory into blocks of same size called pages
▪ Keep track of all free frames
▪ To run a program of size N pages, need to find N free frames and
load program
▪ Set up a page table to translate logical to physical addresses
▪ Backing store likewise split into pages
▪ Still have Internal fragmentation
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Address Translation Scheme
▪ Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
• Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
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Paging Hardware
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Paging Model of Logical and Physical Memory
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Paging Example
▪ Logical address: n = 2 and m = 4. Using a page size of 4 bytes and
a physical memory of 32 bytes (8 pages)
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Swapping
▪ A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
▪ Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
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Swapping (Cont.)
▪ Does the swapped out process need to swap back into same physical
addresses?
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Schematic View of Swapping
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Swapping with Paging
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End of Chapter 9
Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018