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    Saurabh Resume

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    Milin Raijada
    Saurabh Srivastava is a Design Verification Engineer at Qualcomm. He has experience developing test cases to verify clocks and power management units for Wi-Fi and IoT chips. He has collaborated with CPU architects to validate designs and identify issues. Saurabh has a Bachelor's degree in Electronics and Computer Engineering from National Institute of Technology Tiruchirappalli with a minor in Computer Science Engineering and a GPA of 9.76/10. He has worked on internships in Germany and India related to vehicular networks and real-time analytics.

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    Saurabh Resume

    Uploaded by

    Milin Raijada
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    Saurabh Srivastava is a Design Verification Engineer at Qualcomm. He has experience developing test cases to verify clocks and power management units for Wi-Fi and IoT chips. He has collaborated with CPU architects to validate designs and identify issues. Saurabh has a Bachelor's degree in Electronics and Computer Engineering from National Institute of Technology Tiruchirappalli with a minor in Computer Science Engineering and a GPA of 9.76/10. He has worked on internships in Germany and India related to vehicular networks and real-time analytics.

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    Saurabh Srivastava is a Design Verification Engineer at Qualcomm. He has experience developing test cases to verify clocks and power management units for Wi-Fi and IoT chips. He has collaborated with CPU architects to validate designs and identify issues. Saurabh has a Bachelor's degree in Electronics and Computer Engineering from National Institute of Technology Tiruchirappalli with a minor in Computer Science Engineering and a GPA of 9.76/10. He has worked on internships in Germany and India related to vehicular networks and real-time analytics.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views1 page

    Saurabh Resume

    Uploaded by

    Milin Raijada
    Saurabh Srivastava is a Design Verification Engineer at Qualcomm. He has experience developing test cases to verify clocks and power management units for Wi-Fi and IoT chips. He has collaborated with CPU architects to validate designs and identify issues. Saurabh has a Bachelor's degree in Electronics and Computer Engineering from National Institute of Technology Tiruchirappalli with a minor in Computer Science Engineering and a GPA of 9.76/10. He has worked on internships in Germany and India related to vehicular networks and real-time analytics.

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    Saurabh Srivastava

    Design Verification Engineer

    EXPERIENCE EDUCATION
    QUALCOMM | DESIGN VERFICATION ENGINEER NATIONAL INSTITUTE OF
    June 2021 – Current | Chennai, India TECHNOLOGY
    Ô Worked on development of constrained-random and directed test cases to verify TIRUCHIRAPALLI
    Clocks and Power Management Units for Wi-Fi and IoT chips across technology BACHELOR OF ENGINEERING
    nodes ranging from 28LP CMOS to 7FF Fin-FET. July 2017 ‑ May 2021 | Tiruchirapalli,
    Ô Collaborated closely with CPU architects to validate and verify intricate design India
    concepts, resulting in the identification and correction of potential architectural Electronics and Computer
    bottlenecks. Engineering
    Ô Successfully designed, implemented, and executed comprehensive full chip Minor in Computer Science
    testbenches, leading to the detection and resolution of critical design flaws prior to Engineering CGPA: 9.76 / 10
    tape-out, minimizing post-silicon issues by 15
    Ô Improving design coverage and bug rates by adopting a hybrid approach of SKILLS
    Functional and Formal verification.
    Ô Optimizing the verification timeline by automating the generation of test bench PROGRAMMING
    components using scripting languages like Perl & Python. C++ • Python
    TU BERLIN GERMANY | DAAD WISE INTERN
    July 2012 – March 2016 | Metropolis VERIFICATION
    METHODOLOGIES
    Ô Worked on the project optimization of communication channel for vehicular
    networks under Prof. Falko Dressler at CCS Labs in Germany. UVM • Formal Testbench
    Ô The project involved mobility prediction of the vehicles using dataset generated by (using SVA) • System Verilog
    SUMO simulator.
    TOOLS
    RAPTEE ENERGY INC | AWS INTERN
    Synopsys VCS • Verdi • VC
    July 2020 – Jan 2021 | Chennai, India
    Formal
    Ô Worked on development of real time analytics pipeline for the company’s web
    dashboard and application interface.
    EXTRACURRICULARS
    Ô Used various AWS services which include AWS CloudFront, AWS Lambda, S3, IoT
    Core, Kinesis Firehose Delivery, AWS Glue, Athena, Quicksight and Amplify to
    • Manager at Festember Media
    implement the model.
    Relations.
    • Co-ordinator at Infotainment
    Pragyan.
    PROJECTS • Member of NSS.
    DIGITAL ERROR CORRECTION IN 14‑BT SAR ADC USING 180NM SCL
    TECHNOLOGY NIT TRICHY
    July 2020‑March 2021
    Ô Design of capacitor layout for digital error correction based on split capacitor
    architecture and monotonic switching.
    Ô The capacitors were tested in Cadence Virtuoso using SCL library.

    ACADEMIC ACHIEVEMENTS
    2020 Selected as DAAD WISE Scholar for research opportunities in Germany
    2020 Selected as MITACS GLOBALINK Scholar for rearch in Canada
    2015 Qualified NTSE (National Talent Search Examination) Stage 1

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