A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Penryn uFCPGA with Intel
3
Cantiga_PM+ICH9-M core logic 3

LA-4082P Vader Discrete (NB9P-GS,NB9M-GE)

2007-12-26 Rev 0.4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 1 of 58
A B C D E
 A B C D E

Compal confidential
Montevina Consumer Discrete
Dual-Core Thermal Sensor CK505 72QFN
EMC1402
Mobile Penryn Clock Generator
VRAM DDR2 Quad-Core Thermal Sensor
1
256/512MB SLG8SP553V 1
EMC1403
P4 P15
P22,23,24,25 uFCPGA-478 CPU
128 bits
P4, 5, 6
Fan conn P4
H_A#(3..35)
Discrete FSB
H_D#(0..63) 667/800/1066 MHz 1.05V
Nvidia NB9P-GE
Nvidia NB9M-GE DDR2 SO-DIMM X2
P18,19,20,21 DDR2 667MHz 1.8V BANK 0, 1, 2, 3 P13, 14

Intel Cantiga MCH Dual Channel

LVDS Panel
Interface P17 FCBGA 1329
USB conn x3
P7, 8, 9, 10, 11, 12 P38
CRT
2
P16 2

USB2.0*7
Support V1.3
DMI X4 C-Link BT Conn Touch Screen Conn
P38
HDMI P44 P38

USB Camera
P17
PCI-E BUS*5 & USB2.0 *3 Azalia
FPR Conn
Intel ICH9-M SATA Master-1
SATA Master-2
P42

SATA Slave
Realtek 8111C Mini-Card*3 New Card Discrete mBGA-676 Audio CKT AMP & Audio Jack
SATA Slave Codec_IDT9271B7 MIC & SPKR
(GLAN) WLAN & Robson &TV USB2.0*1 Flash Memory Card / P26,27,28,29 P34 P36
USB2.0*2 PCIE*1 TPA6020
PCIE*3 1394 Controller
P31 P32,35 P32
JM380 USB2.0 X1
CardReader/1394 M DC Sub-woofer & EQ
P35
P33
P37
RJ45/11 CONN
3 P31 LPC BUS SATA HDD Connector 3
P30
1394 port
Discrete only P33
SATA 2nd HDD Dock
ACCELEROMETER-1 Option Connector P30
USB2.0*1
P39
5 in1 Slot ENE RGB
P33
KB926 SATA ODD Connector RJ45
P30
ACCELEROMETER-2 P40 SPDIF
P39 CIR
e-SATA Combo Connector
Touch Pad CONN. Int.KBD USB2.0*1 & SATA*1 P38
MIC*1
LED RTC CKT.
P41 P40 LINE-OUT*1
P41 P27
SPI SPDIF

SPI ROM P42

Capsense switch Conn
P41
25LF080A P39
4 4

K/B backlight Conn

P41

Security Classification Compal Secret Data Compal Electronics, Inc.

2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P43 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 2 of 58
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

SMBus Control Table

+5VS
+3VS SERIAL Thermal MINI
SOURCE INVERTER BATT EEPROM Sensor SODIMM CLK CHIP CARD LCD Sensor
+1.5VS
power board
+0.9V SMB_EC_CK1
plane
+VCCP SMB_EC_DA1
KB926 X V V X X X X X V
+5VALW +1.8V +CPU_CORE SMB_EC_CK2
+B SMB_EC_DA2
KB926 X X X V X X X X X
+3VALW +VGA_CORE SMB_CK_CLK1
+2.5VS SMB_CK_DAT1
ICH9 X X X X V V V X X
State +1.8VS DDC2_CLK
+1.2VS DDC2_DATA
NB9M X X X X X X X V X
+0.9VGA

USB PCIe Symbol Note :

S0
O O O O assignment: assignment:
USB-0 Right side PCIe-1 TV tuner/WWAN/Robeson
S1 USB-1 Right side PCIe-2 X
: means Digital Ground
O O O O
USB-2 Left side(with ESATA) PCIe-3 WLAN
S3 USB-3 Dock PCIe-4 New Card
O O O X : means Analog Ground
USB-4 Camera PCIe-5 Card
S5 S4/AC USB-5 WLAN reader
PCIe-6 GLAN (Marvell)
O O X X @ : means just reserve , no build
USB-6 Bluetooth
S5 S4/ Battery only
DEBUG@ : means just reserve
O USB-7 Finger Printer
X X X for debug.
USB-8 MiniCard(WWAN/TV)
S5 S4/AC & Battery USB-9 Express
don't exist X X X X card
1
USB-10 X 1

USB-11 X

EC SM Bus1 address EC SM Bus2 address

Device HEX Address Device HEX Address

Smart Battery 16H 0001 011X CPU EMC1402 4CH 1001 1000b
24C16 A0H 1010 000X VGA 4DH 1001 1010b
CAP BOARD -- Cypress 38H
CAP BOARD -- ST b0H

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 3 of 58
A
 5 4 3 2 1

+3VS

@ R730
ITP-XDP Connector XDP_DBRESET#_R 1 2 1K_0402_5%

Change value in 5/02 +VCCP

CONN@
JP42 XDP_TDI R731 1 2 54.9_0402_1%
1 GND0 GND1 2
XDP_BPM#5 3 4 XDP_TMS R732 1 2 54.9_0402_1%
D XDP_BPM#4 OBSFN_A0 OBSFN_C0 D
5 OBSFN_A1 OBSFN_C1 6
7 8 XDP_TDO R733 1 2 54.9_0402_1%
XDP_BPM#3 GND2 GND3
9 OBSDATA_A0 OBSDATA_C0 10
XDP_BPM#2 11 12 XDP_BPM#5 R734 1 2 54.9_0402_1%
OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
XDP_BPM#1 15 16 XDP_HOOK1 @ R735 1 2 54.9_0402_1%
XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
17 OBSDATA_A3 OBSDATA_C3 18
19 20 XDP_TRST# R792 1 2 54.9_0402_1%
7 H_A#[3..16] GND6 GND7
JCPUA 1025 For Support Dual core and Quad core 21 22
H_A#3 H_ADS# OBSFN_B0 OBSFN_D0 XDP_TCK R737 54.9_0402_1%
J4 A[3]# ADS# H1 H_ADS# 7 23 OBSFN_B1 OBSFN_D1 24 1 2

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 25 26
A[4]# BNR# H_BNR# 7 GND8 GND9
H_A#5 L4 G5 H_BPRI# XDP_BPM2#0 27 28
A[5]# BPRI# H_BPRI# 7 OBSDATA_B0 OBSDATA_D0
H_A#6 K5 XDP_BPM2#1 29 30 This shall place near CPU
H_A#7 A[6]# H_DEFER# OBSDATA_B1 OBSDATA_D1
M3 A[7]# DEFER# H5 H_DEFER# 7 31 GND10 GND11 32
H_A#8 N2 F21 H_DRD Y# XDP_BPM2#2 33 34
A[8]# DRDY# H_DRDY# 7 OBSDATA_B2 OBSDATA_D2
H_A#9 J1 E1 H_DBSY# 6 XDP_BPM2#3 XDP_BPM2#3 35 36
A[9]# DBSY# H_DBSY# 7 OBSDATA_B3 OBSDATA_D3
H_A#10 N3 1K_0402_5% 37 38
H_A#11 A[10]# H_BR0# GND12 GND13
P5 A[11]# BR0# F1 H_BR0# 7 5,27 H_PWRGOOD R738 1 2 H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP CLK_CPU_XDP 15
H_A#12 P2 XDP_HOOK1 41 42 CLK_CPU_XDP# CLK_CPU_XDP# 15
H_A#13 A[12]# H_IERR# T1 HOOK1 ITPCLK#/HOOK5
L2 D20 43 44

CONTROL
A[13]# IERR# +VCCP VCC_OBS_AB VCC_OBS_CD +VCCP
H_A#14 P4 B3 H_INIT# 2 1 45 46 H_RESET#_R R739 1 2 1K_0402_1% H_RESET#
A[14]# INIT# H_INIT# 27 HOOK2 RESET#/HOOK6
H_A#15 P1 Place TP with a C851 0.1U_0402_16V4Z 47 48 XDP_DBRESET#_R R740 1 2 0_0402_1% XDP_DBRESET#
H_A#16 A[15]# H_LOCK# HOOK3 DBR#/HOOK7
R1 A[16]# LOCK# H4 H_LOCK# 7 GND 0.1" away 49 GND14 GND15 50
H_ADSTB#0 M1 51 52 XDP_TDO
7 H_ADSTB#0 ADSTB[0]# SDA TD0
C1 H_RESET# Removed at 53 54 XDP_TRST#
RESET# H_RESET# 7 SCL TRST#
H_REQ#0 K3 F3 H_RS#0 55 56 XDP_TDI
7 H_REQ#0
H_REQ#1 H2
REQ[0]# RS[0]#
F4 H_RS#1
H_RS#0 7 5/30.(Follow XDP_TCK 57
TCK1 TDI
58 XDP_TMS 0_0402_5%
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7 TCK0 TMS
7 H_REQ#2
H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2
H_RS#2 7 Chimay) 59 GND16 GND17 60 XDP_PRE R741 1 2
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1 SAMTE_BSH-030-01-L-D-A Place R191 within 200ps (~1")
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7 to CPU
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# 7 C
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1

H_A#20 W6 AD3 XDP_BPM#1 QC@

H_A#21 A[20]# BPM[1]# XDP_BPM#2 U78
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3 +3VS
H_A#23 A[22]# BPM[3]# XDP_BPM#4
U1 A[23]# PRDY# AC2
XDP/ITP SIGNALS

H_A#24 R4 AC1 XDP_BPM#5 1 10 SMB_EC_CK2

A[24]# PREQ# VDD SMCLK

0.1U_0402_16V4Z
H_A#25 T5 AC5 XDP_TCK Delete H_PROCHOT# off-page due to 1
H_A#26 A[25]# TCK XDP_TDI QC@ H_THERMDA SMB_EC_DA2
T3 AA6 2 9
H_A#27 W2
A[26]# TDI
AB3 XDP_TDO VR doesn't have it's input pin @08/31 C2113 QC@ C2114 DP1 SMDATA
H_A#28 A[27]# TDO XDP_TMS H_THERMDC
W5 A[28]# TMS AB5 1 2 3 DN1 ALERT# 8
H_A#29 XDP_TRST# 2 +3VS 2200P_0402_50V7K
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# H_THERMDA2 4 7 THERM#
A[30]# DBR# XDP_DBRESET# 28 DP2 THERM#
H_A#31 V4 QC@ C2115
H_A#32 A[31]#
W3 A[32]#
10/08 follow Intel suggestion to change value 1 2 H_THERMDC2 5 DN2 GND 6

0.1U_0402_16V4Z
H_A#33 AA4 THERMAL 1 2200P_0402_50V7K
H_A#34 A[33]# H_PROCHOT# R7
AB2 A[34]# 1 2 49.9_0402_1% +VCCP
H_A#35 AA3 D21 C1 EMC1403-1-AIZL-TR_MSOP10
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R8 H_THERMDA
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 1 2 0_0402_5% U55
H_THERMDC_R R9 2
THERMDC B25 1 2 0_0402_5% H_THERMDC
H_A20M# A6
27 H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 8 SMB_EC_CK2 SMB_EC_CK2 20,40

27 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 7,27,40 VDD SMCLK
H_IGNNE# C4
27 H_IGNNE# IGNNE# H_THERMDA 2 7 SMB_EC_DA2
DP SMDATA SMB_EC_DA2 20,40
H_STPCLK# D5
27 H_STPCLK# STPCLK#
H_INTR C6 H CLK C2 1 2 H_THERMDC 3 6
27 H_INTR LINT0 DN ALERT#
H_NMI B4 A22 CLK_CPU_BCLK 2200P_0402_50V7K
27 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 15
H_SMI# A3 A21 CLK_CPU_BCLK# THERM# 4 5
27 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15 THERM# GND
XDP_BPM2#1 M4 R10
QC@ R2088 0_0402_5% XDP_BPM2#0 RSVD[01]/BPM_2#[1]
N5 RSVD[02]/BPM_2#[0] H_THERMDA, H_THERMDC routing +3VS 1 2
H_THERMDA2 1 2 H_THERMDA2_R T2 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
B H_THERMDC2 1 2 H_THERMDC2_R V3
RSVD[03]/THRMDA_2 together, Trace width / Spacing = 10 / 10 B
RSVD[04]/THRMDC_2
QC@ R2089 0_0402_5% XDP_BPM2#2 B2 RSVD[05]/BPM_2#[2]
mils Address:100_1100
D2 RSVD[06]
+H_GTLREF2 D22 RSVD[07]/GTLREF_2
D3 RSVD[08]/TDO_M
+VCCP 1 2 1 2 F6 RSVD[09]/TDI_M
R54 0_0402_5%
51_0402_1% QC@
QC@ R53 DC_RESERVED/QC PWM Fan Control circuit
Penryn +5VS
H_THERMDA2, H_THERMDC2 routing
CONN@
together, Trace width / Spacing = 10 / 10 +VCCP JP2
mils 1 1
1025 For Support Dual core and Quad core 2 2

1
1 1
1

@ D1 C3 C4 3
R12 4.7U_0805_10V4Z 0.1U_0402_16V4Z GND
4 GND
56_0402_5% RB751V_SOD323
2 2 ACES_88231-02001

2
CPU GTLREF_C GTLREF2
2 2

+VCCP
B

Dual core (DC) GND 0V +FAN

E

Quad core (QC) Floating 2/3Vtt H_PROCHOT# 3 1 OCP#

OCP# 28

1
2
5
6

1
C

@ Q2
1

QC@ MMBT3904_NL_SOT23-3 D Q1 @ D2
R43 +3VS G
1K_0402_5% 3 RLZ5.1B_LL34
+VCCP 40 FAN_PWM S SI3456BDV-T1-E3_TSOP6

2
2

4
1

+H_GTLREF2 QC@ +VCCP

1

A R45 A
100K_0402_5% R1
1

R44 56_0402_5%
1

QC@ D R51
2

2K_0402_5% 2 QC@ 10K_0402_5%

2

G 10K_0402_5% QC@
S H_IERR#
R49
2

1
1

BSS138_SOT23~D
Q3
B
2 1 2 GTLREF2 6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
QC@ E
Penryn(1/3)-AGTL+/ITP-XDP
3

Q4 MMBT3904_NL_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
QC@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 4 of 58
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
7 H_D#[0..15] H_D#[32..47] 7
JCPUB JCPUC
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 V23 A13 AC12

DATA GRP 2
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 D[5]# D[37]# T22 A15 VCC[006] VCC[073] AC13
H_D#6 E25 U25 H_D#38 A17 AC15
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E23 D[7]# D[39]# U23 A18 VCC[008] VCC[075] AC17
H_D#8 K24 Y25 H_D#40 A20 AC18
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7 VCC[017] VCC[084]
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]
H_D#21
H_D#22
M24 D[21]# DATA GRP 1 D[53]# AC26 H_D#53
H_D#54
D10 VCC[027] VCC[094] AF10
L22 AD20 D12 AF12
DATA GRP 3
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
M23 D[23]# D[55]# AE22 D14 VCC[029] VCC[096] AF14
H_D#24 P25 AF23 H_D#56 D15 AF15
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
P23 D[25]# D[57]# AC25 D17 VCC[031] VCC[098] AF17
H_D#26 P22 AE21 H_D#58 D18 AF18
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R13
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21 +VCCPA 1 2 0_0402_5%
H_D#30 T25 AF22 H_D#62 E12 V6 +VCCPB 1 2 0_0402_5%
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R14 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] + C5
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R7
+V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R15 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@ R16 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6
T3 TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R17 R18 R19 R20 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# 7,27,51 VCC[047] VCCP[13]
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# 27 VCC[048] VCCP[14]

1
54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PW RGOOD F20 W21
15 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 4,27 VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# DC@ R52 1 2 0_0402_5% AA7
15 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]/BR1#
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
15 CPU_BSEL2 BSEL[2] PSI# H_PSI# 51 VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

0.01U_0402_16V7K
10U_0805_6.3V6M
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 51
AA15 VCC[056] VID[1] AF5 CPU_VID1 51 1 1
* Route the TEST3 and TEST5 signals through AA17 VCC[057] VID[2] AE5 CPU_VID2 51
C6 C7
AA18 VCC[058] VID[3] AF4 CPU_VID3 51
a ground referenced Zo = 55-ohm trace that AA20 AE3 CPU_VID4 51
VCC[059] VID[4] 2 2
ends in a via that is near a GND via and is AB9 VCC[060] VID[5] AF3 CPU_VID5 51
AC10 VCC[061] VID[6] AE2 CPU_VID6 51
accessible through an oscilloscope Resistor placed within 0.5" AB10 VCC[062]
connection. AB12 VCC[063]
of CPU pin.Trace should be AB14 AF7 VCCSENSE VCCSENSE 51
VCC[064] VCCSENSE
at least 25 mils away from AB15 VCC[065]
any other toggling signal.
AB17
AB18
VCC[066]
AE7 VSSSENSE Near pin B26
VCC[067] VSSSENSE VSSSENSE 51
B COMP[0,2] trace width is 18 Penryn B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
mils. COMP[1,3] trace width .
is 4 mils. 1025 For Support Dual core and Quad core
166 0 1 1
Length match within 25 mils.
200 0 1 0 The trace width/space/other
is 20/7/25.
+VCCP
266 0 0 0
1

R21
1K_0402_1%
+VCC_CORE
2

+V_CPU_GTLREF

R22 1 2 100_0402_1% VCCSENSE

1

R23
2K_0402_1% R24 1 2 100_0402_1% VSSSENSE
2

Close to CPU pin within

Close to CPU pin 500mils.
A
AD26 within A

500mils.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

5
1 1 1 1 1 1 1 1
Place these C8 C9 C10 C11 C12 C13 C14 C15
capacitors on L8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
(North 2 2 2 2 2 2 2 2
side,Secondary
D D
Layer)
JCPUD +VCC_CORE
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21 5
A11 VSS[003] VSS[084] P24 1 1 1 1 1 1 1 1
A14 R2 Place these C16 C17 C18 C19 C20 C21 C22 C23
VSS[004] VSS[085]
A16 VSS[005] VSS[086] R5 capacitors on L8
A19 R22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[006] VSS[087] (North 2 2 2 2 2 2 2 2
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1 side,Secondary
B6 VSS[009] VSS[090] T4 Layer)
B8 VSS[010] VSS[091] T23
+VCC_CORE
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 5
B19 VSS[014] VSS[095] U21 1 1 1 1 1 1 1 1
B21 U24 Place these C24 C25 C26 C27 C28 C29 C30 C31
VSS[015] VSS[096]
B24 VSS[016] VSS[097] V2 capacitors on L8
C5 V5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[017] VSS[098] (North 2 2 2 2 2 2 2 2
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25 side,Secondary
C14 VSS[020] VSS[101] W1 Layer)
C16 VSS[021] VSS[102] W4
+VCC_CORE
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 5
C25 VSS[025] VSS[106] Y6 1 1 1 1 1 1 1 1
D1 Y21 Place these C32 C33 C34 C35 C36 C37 C38 C39
DC@ VSS[026] VSS[107]
D4 VSS[027] VSS[108] Y24 capacitors on L8
R2055 1 2 D8 AA2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
0_0402_5% VSS[028]/RSVD_0 VSS[109] DC@ (North 2 2 2 2 2 2 2 2
D11 VSS[029] VSS[110] AA5
C R2056 side,Secondary C
D13 VSS[030] RSVD_1/VSS[111] AA8 1 2
D16 AA11 0_0402_5%
VSS[031] VSS[112] Layer)
D19 VSS[032] VSS[113] AA14
D23 AA16
D26
VSS[033] VSS[114]
AA19
Mid Frequence Decoupling
VSS[034] VSS[115]
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 AB4
E14
E16
VSS[038]
VSS[039]
VSS[119]
VSS[120] AB8
AB11
ESR <= 1.5m ohm
VSS[040] VSS[121]
E19 VSS[041] VSS[122] AB13 Capacitor >
E21
E24
VSS[042] VSS[123] AB16
AB19
Near CPU CORE regulator
DC@
R2033 1 GTLREF2
F5
VSS[043]
VSS[044]
VSS[124]
VSS[125] AB23 1980uF
2 F8 VSS[045]/GTLREF_C VSS[126] AB26
0_0402_5% F11 AC3
VSS[046] VSS[127] DC@ +VCC_CORE
F13 VSS[047] VSS[128] AC6
F16 AC8 R2057 1 2
VSS[048] RSVD_2/VSS[129] 0_0402_5% 330U_D2E_2.5VM_R7
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21 1 1 1 1
G1 VSS[054] VSS[135] AC24
G23 AD2 C40 + C41 + @ C42 + C43 +
VSS[055] VSS[136] 330U_D2E_2.5VM_R7
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
2 2 2 2
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 AD19 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 AE4 DC@ R2054
VSS[065] VSS[146] XDP_BPM2#3
K4 VSS[066] BPM_2#[3]/VSS[147] AE8 1 2
K23 AE11 0_0402_5%
VSS[067] VSS[148]
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5
M22
VSS[074] VSS[155] AF6
AF8 +VCCP Inside CPU center cavity in 2 rows
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11 5
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16 1 1 1 1 1 1
N23 AF19 C45 C46 C47 C48 C49 C50
VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
P3 A25 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS[081] VSS[162] 2 2 2 2 2 2
VSS[163] AF25

Penryn
.

1025 For Support Dual core and Quad core

A GTLREF2 A
GTLREF2 4
XDP_BPM2#3
XDP_BPM2#3 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4 U57B
5 H_D#[0..63] U57A

DDR CLK/ CONTROL/COMPENSATION

A14 H_A#3 M36
H_A#_3 T7 RESERVED
H_D#0 F2 C15 H_A#4 N36 AP24 M_CLK_DDR0 M_CLK_DDR0 13
H_D#_0 H_A#_4 T8 RESERVED SA_CK_0

0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#1 G8 F16 H_A#5 R33 AT21 M_CLK_DDR1 M_CLK_DDR1 13
H_D#_1 H_A#_5 T9 RESERVED SA_CK_1
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 14
H_D#_2 H_A#_6 +1.8V T10 RESERVED SB_CK_0
H_D#3 E6 C18 H_A#7 AH9 AU20 M_CLK_DDR3 M_CLK_DDR3 14
H_D#_3 H_A#_7 T11 RESERVED SB_CK_1
H_D#4 G2 M16 H_A#8 AH10
H_D#_4 H_A#_8 T12 RESERVED
H_D#5 H6 J13 H_A#9 1 1 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 T13 RESERVED SA_CK#_0 M_CLK_DDR#0 13

1
C51

C52
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 T14 RESERVED SA_CK#_1 M_CLK_DDR#1 13
H_D#7 F6 R16 H_A#11 R25 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 T15 RESERVED SB_CK#_0 M_CLK_DDR#2 14
H_D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 T16 RESERVED SB_CK#_1 M_CLK_DDR#3 14
H_D#9 H3 M13 H_A#13 AK34
H_D#_9 H_A#_13 T17 RESERVED
H_D#10 M9 E17 H_A#14 AN35 BC28 DDR_CKE0_DIMMA
T18 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RESERVED SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 T19 AM35 RESERVED SA_CKE_1 AY28 DDR_CKE1_DIMMA 13
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 80% of 1.8V VCC_SM T20 T24 RESERVED SB_CKE_0 AY36 DDR_CKE2_DIMMB 14

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 14

RSVD
H_D#14 N12 B19 H_A#18 R26 B31
H_D#_14 H_A#_18 T21 RESERVED
H_D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR_CS0_DIMMA#
H_D#_15 H_A#_19 T22 RESERVED SA_CS#_0 DDR_CS0_DIMMA# 13
H_D#16 P2 E20 H_A#20 20% of 1.8V VCC_SM M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 T23 RESERVED SA_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 L2 H16 H_A#21 AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# 14
H_D#19 N9 L17 H_A#23 AY21
H_D#_19 H_A#_23 T24 RESERVED

1
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#20 L6 A17 H_A#24 BD17 M_ODT0 M_ODT0 13
H_D#21 H_D#_20 H_A#_24 H_A#25 R27 SA_ODT_0 M_ODT1
M5 H_D#_21 H_A#_25 B17 1 1 SA_ODT_1 AY17 M_ODT1 13 +1.8V

C53

C54
H_D#22 J3 L16 H_A#26 1K_0402_1% BF15 M_ODT2 M_ODT2 14
H_D#23 H_D#_22 H_A#_26 H_A#27 SB_ODT_0 M_ODT3
N2 H_D#_23 H_A#_27 C21 T26 BG23 RESERVED SB_ODT_1 AY13 M_ODT3 14
H_D#24 R1 J17 H_A#28 BF23
T27

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RESERVED SMRCOMP R28
N5 H_D#_25 H_A#_29 H20 T28 BH18 RESERVED SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R29 1 2 80.6_0402_1%
H_D#_26 H_A#_30 T29 RESERVED SM_RCOMP#
H_D#27 P13 K17 H_A#31 Follow Design Guide
H_D#28 H_D#_27 H_A#_31 H_A#32 SMRCOMP_VOH
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28 For Cantiga: 80.6ohm
H_D#29 L7 F21 H_A#33 BH28 SMRCOMP_VOL
H_D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21 1009 Follow Design Guide
H_D#31 M3 L20 H_A#35 AV42 +V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 +3VS SM_VREF SM_PWROK R30
Y3 H_D#_32 SM_PWROK AR36 1 2 0_0402_5%
H_D#33 AD14 H12 H_ADS# BF17 SM_REXT R31 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# 4 SM_REXT
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 R32 1 2 10K_0402_5% BC36 TP_SM_DRAMRST# T30 PAD
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 SM_DRAMRST#
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
H_D#36 Y12 A9 H_BNR# B38
H_D#_36 H_BNR# H_BNR# 4 DPLL_REF_CLK
H_D#37 Y14 F11 H_BPRI# PM_EXTTS#1 R33 1 2 10K_0402_5% A38 1015 Follow Design Guide
H_D#_37 H_BPRI# H_BPRI# 4 DPLL_REF_CLK#
H_D#38 Y7 G12 H_BR0# E41
H_D#_38 H_BREQ# H_BR0# 4 DPLL_REF_SSCLK
H_D#39 W2 E9 H_DEFER# F41
HOST

H_D#_39 H_DEFER# H_DEFER# 4 DPLL_REF_SSCLK#

H_D#40 AA8 B10 H_DBSY# CLKREQ#_7 R34 1 2 10K_0402_5%
H_D#_40 H_DBSY# H_DBSY# 4

CLK
H_D#41 Y9 AH7 CLK_MCH_BCLK F43 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK 15 PEG_CLK CLK_MCH_3GPLL 15
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 15 PEG_CLK# CLK_MCH_3GPLL# 15
H_D#43 AA9 J11 H_DPWR#
C H_D#_43 H_DPWR# H_DPWR# 5 C
H_D#44 AA11 F9 H_DRD Y#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12 H_HITM# AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 28
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 28
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 28
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 28
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_TXP0 28
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_TXP1
H_D#_52 15 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 28
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 5 15 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 28
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 5 15 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 28
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_RXN0 28
H_D#57 AC1 CFG5 C25 AE43 DMI_RXN1
H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 28
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_RXN2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 9 CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 28
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 28
H_D#60 AE11 AA5 H_DSTBN#2 CFG8 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 9 CFG8 CFG_8

CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_DSTBN#3 5 9 CFG9 DMI_RXP0 28

DMI
H_D#62 H_D#_61 H_DSTBN#_3 CFG10 CFG_9 DMI_TXP_0 DMI_RXP1
AG2 H_D#_62 9 CFG10 C24 CFG_10 DMI_TXP_1 AE44 DMI_RXP1 28
H_D#63 AD6 L9 H_DSTBP#0 CFG11 N21 AF46 DMI_RXP2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5 9 CFG11 CFG_11 DMI_TXP_2 DMI_RXP2 28
M8 H_DSTBP#1 CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 5 9 CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 28
AA6 H_DSTBP#2 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 5 9 CFG13 CFG_13
+H_SWNG C5 AE5 H_DSTBP#3 CFG14 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 5 9 CFG14 CFG_14
H_RCOMP E3 CFG15 M20
H_RCOMP 9 CFG15 CFG_15
B15 H_REQ#0 CFG16 L21

GRAPHICS VID
H_REQ#_0 H_REQ#0 4 9 CFG16 CFG_16
K13 H_REQ#1 CFG17 H21
H_REQ#_1 H_REQ#1 4 9 CFG17 CFG_17
F13 H_REQ#2 CFG18 P29
H_REQ#_2 H_REQ#2 4 9 CFG18 CFG_18
B13 H_REQ#3 CFG19 R28
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20 GFX_VID_0 T31
5 H_CPUSLP# H_CPUSLP# E11 B32
H_CPUSLP# GFX_VID_1 T32
B6 H_RS#0 H_RS#0 4 G33
H_RS#_0 GFX_VID_2 T33
F12 H_RS#1 H_RS#1 4 F33
B H_RS#_1 GFX_VID_3 T34 B
C8 H_RS#2 H_RS#2 4 28 PM_BMBUSY# PM_BMBUSY# R29 E33
H_RS#_2 PM_SYNC# GFX_VID_4 T35
+H_VREF A11 H_DPRSTP# B7
H_AVREF 5,27,51 H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
14 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
28,40 PM_PWROK PWROK GFX_VR_EN T36 +VCCP
layout note: R943 1 2 AT11
18,26,31,32,33,35 PLT_RST# RSTIN#
4,27,40 H_THERMTRIP# R35 1 2 100_0402_5% THERMTRIP# T20
0_0402_5% DPRSLPVR THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace width, 28,51 DPRSLPVR R32 DPRSLPVR

1
spacing and impedance (55 ohm) same as FSB data AH37 CL_CLK0 R36
CL_CLK CL_CLK0 28

0.1U_0402_16V4Z
traces AH36 CL_DATA0 1K_0402_1%
CL_DATA CL_DATA0 28
1 @ BG48 AN36 M_PWROK
NC CL_PWROK M_PWROK 28,40
C55 BF48 AJ35 CL_RST#
CL_RST# 28

2
NC CL_RST# +CL_VREF
Layout Note: V_DDR_MCH_REF trace BD48 AH34

ME
NC CL_VREF
Layout Note: width and spacing is 20/20. BC48 NC

1
2 0621 add CLK and DAT for DVI
BH47 1
H_RCOMP / H_VREF / H_SWNG BG47
NC C56 R37
NC 0.1U_0402_16V4Z 499_0402_1%
trace width and spacing is 10/20 +1.8V
BE47 NC DDPC_CTRLCLK N28 T37
+V_DDR_MCH_REF generated by DC-DC BH46 NC DDPC_CTRLDATA M28 T38 2
BF46 G36

2
+VCCP NC SDVO_CTRLCLK

NC
BG45 NC SDVO_CTRLDATA E36
1

+VCCP BH44 K36 CLKREQ#_7

MISC
NC CLKREQ# CLKREQ#_7 15
R38 BH43 H36 MCH_ICH_SYNC#
NC ICH_SYNC# MCH_ICH_SYNC# 28
221_0603_1%
1K_0402_1%

1K_0402_1% BH6 NC
1

BH5 NC *R37*Follow Intel

R39 R40 BG4 B12 TSATN#
feedback
2

+V_DDR_MCH_REF NC TSATN# 56_0402_5%

13,14 +V_DDR_MCH_REF BH3 NC
BF3 NC 1 2 +VCCP
1
0.1U_0402_16V4Z

BH2 R42
2

+H_VREF H_RCOMP +H_SWNG R41 NC

1 BG2 NC HDA_BCLK B28 Delete Off-page
C57 1K_0402_1% BE2 B30 0906 delete
NC HDA_RST# @1028
0.1U_0402_16V4Z
24.9_0402_1%

BG1 NC HDA_SDI B29

1

1
100_0402_1%
0.1U_0402_16V4Z

A A
1 1 BF1 C29
2

2 NC HDA_SDO
2K_0402_1%

R46 C58 R47 R48 C59 BD1 A28

NC HDA_SYNC

HDA
BC1 NC
F1 NC
2 2 0830 Add pull-up and pull-down resistor.
A47
2

NC
CANTIGA ES_FCBGA1329
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U57D U57E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 13 SB_DQ_0 SB_BS_0 DDR_B_BS0 14
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 13 SB_DQ_1 SB_BS_1 DDR_B_BS1 14
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 13 SB_DQ_2 SB_BS_2 DDR_B_BS2 14
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 13 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# 13 SB_DQ_5 SB_RAS# DDR_B_RAS# 14
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# 13 DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# 14
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# 14
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] 13 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] 14
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

A
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 DDR_A_DQS[0..7] 13 BF43 AK2

B
DDR_A_D20 SA_DQ_19 DDR_A_DQS0 DDR_B_D20 SB_DQ_19 SB_DM_7
AV41 SA_DQ_20 SA_DQS_0 AJ44 BE45 SB_DQ_20 DDR_B_DQS[0..7] 14
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 BC37 DDR_A_DQS3 DDR_B_D23 BF41 BG41 DDR_B_DQS2
DDR_A_D24 AY37
SA_DQ_23 MEMORY SA_DQS_3
AW12 DDR_A_DQS4 DDR_B_D24 BG38
SB_DQ_23 SB_DQS_2
BG37 DDR_B_DQS3

MEMORY
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] 13 BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] 14 C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] 13 SB_DQ_35 SB_DQS#_6
DDR_A_D36 DDR_B_D36 DDR_B_DQS#7
SYSTEM

AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5

DDR_A_D37 DDR_A_MA0 DDR_B_D37

SYSTEM
AV13 SA_DQ_37 SA_MA_0 BA21 BF11 SB_DQ_37 DDR_B_MA[0..14] 14
DDR_A_D38 BD12 BC24 DDR_A_MA1 DDR_B_D38 BF8 AV17 DDR_B_MA0
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
DDR_A_D40 BB9 BH24 DDR_A_MA3 DDR_B_D40 BC5 BC25 DDR_B_MA2
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
DDR_A_D42 AU10 BA24 DDR_A_MA5 DDR_B_D42 AY3 AW25 DDR_B_MA4
DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
DDR_A_D44 BA11 BG27 DDR_A_MA7 DDR_B_D44 BF6 AU28 DDR_B_MA6
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW28
DDR_A_D46 AY8 AW24 DDR_A_MA9 DDR_B_D46 BA1 AT33 DDR_B_MA8
DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
DDR_A_D48 AV5 BG26 DDR_A_MA11 DDR_B_D48 AV2 BB16 DDR_B_MA10
SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
DDR

DDR_A_D49 AV7 BH26 DDR_A_MA12 DDR_B_D49 AU3 AW33 DDR_B_MA11

SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

DDR
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

U57C 000 = FSB 1066MHz
CFG[2:0] FSB Freq select
PEGCOMP trace width 010 = FSB 800MHz Selected By CPU
L32
+VCC_PEG and spacing is 20/25 mils. 011 = FSB 667MHz
L_BKLT_CTRL R50
G32 L_BKLT_EN PEG_COMPI T37 1 2 Others = Reserved
M32 T36 49.9_0402_1%
L_CTRL_CLK PEG_COMPO
M33 L_CTRL_DATA CFG[4:3] Reserved
K33 H44 PEG_RXN0
L_DDC_CLK PEG_RX#_0 PEG_RXN0 18
J33 J46 PEG_RXN1 0 = DMI x 2
D L_DDC_DATA PEG_RX#_1 PEG_RXN1 18 D
L44 PEG_RXN2 CFG5 (DMI select)
PEG_RX#_2 PEG_RXN2 18 1 = DMI x 4
M29 L_VDD_EN
PEG_RX#_3
PEG_RX#_4
L40
N41
PEG_RXN3
PEG_RXN4
PEG_RXN3 18
PEG_RXN4 18
*
0 = The iTPM Host Interface is enable
C44 P48 PEG_RXN5 CFG6
LVDS_IBG PEG_RX#_5 PEG_RXN5 18
B43 N44 PEG_RXN6 1 = The iTPM Host Interface is disable
E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_6
PEG_RX#_7 T43
U43
PEG_RXN7
PEG_RXN8
PEG_RXN6 18
PEG_RXN7 18
0 =(TLS)chiper suite with no confidentiality
*
LVDS_VREFL PEG_RX#_8 PEG_RXN8 18

LVDS
C41 Y43 PEG_RXN9 CFG7 (Intel Management
LVDSA_CLK# PEG_RX#_9 PEG_RXN9 18
C40 Y48 PEG_RXN10 1 =(TLS)chiper suite with confidentiality
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11 Y36
AA43
PEG_RXN11
PEG_RXN12
PEG_RXN10 18
PEG_RXN11 18
Engine Crypto strap)
*
LVDSB_CLK PEG_RX#_12 PEG_RXN12 18
AD37 PEG_RXN13
PEG_RX#_13 PEG_RXN13 18
H47 AC47 PEG_RXN14 CFG8 Reserved
LVDSA_DATA#_0 PEG_RX#_14 PEG_RXN14 18
E46 AD39 PEG_RXN15
LVDSA_DATA#_1 PEG_RX#_15 PEG_RXN15 18
G40 LVDSA_DATA#_2
A40 H43 PEG_RXP0 CFG9 0 = Reverse Lane,15->0, 14->1
LVDSA_DATA#_3 PEG_RX_0 PEG_RXP0 18
J44 PEG_RXP1
PEG_RX_1 PEG_RXP1 18
H48 L43 PEG_RXP2 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
PEG_RXP2 18

GRAPHICS
LVDSA_DATA_0 PEG_RX_2 PEG_RXP3
D45 L41
F40
B40
LVDSA_DATA_1
LVDSA_DATA_2
PEG_RX_3
PEG_RX_4 N40
P47
PEG_RXP4
PEG_RXP5
PEG_RXP3 18
PEG_RXP4 18
0 = Enable
*
LVDSA_DATA_3 PEG_RX_5 PEG_RXP5 18
N43 PEG_RXP6 CFG10 (PCIE Lookback enable)
PEG_RX_6 PEG_RXP6 18
A41 T42 PEG_RXP7 1 = Disable
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42
PEG_RXP8
PEG_RXP9
PEG_RXP7 18
PEG_RXP8 18
CFG11 Reserved
*
LVDSB_DATA#_2 PEG_RX_9 PEG_RXP9 18
J37 W47 PEG_RXP10
LVDSB_DATA#_3 PEG_RX_10 PEG_RXP10 18
Y37 PEG_RXP11 CFG[13:12] (XOR/ALLZ) 00 = Reserved
PEG_RX_11 PEG_RXP11 18
B42 AA42 PEG_RXP12 01 = XOR Mode Enabled
LVDSB_DATA_0 PEG_RX_12 PEG_RXP12 18
G38 AD36 PEG_RXP13 10 = All Z Mode Enabled
LVDSB_DATA_1 PEG_RX_13 PEG_RXP13 18
F37 AC48 PEG_RXP14 11 = Normal Operation(Default)
K37
LVDSB_DATA_2
LVDSB_DATA_3
PEG_RX_14
PEG_RX_15 AD40 PEG_RXP15
PEG_RXP14 18
PEG_RXP15 18
CFG[15:14] Reserved
*

PCI-EXPRESS
C PEG_TXN0 C1289 0.1U_0402_16V4Z C
PEG_TX#_0 J41 1 2 PEG_M_TXN0 18
M46 PEG_TXN1 C1290 1 2 0.1U_0402_16V4Z PEG_M_TXN1 18
PEG_TX#_1 PEG_TXN2 C1291 0.1U_0402_16V4Z
F25 TVA_DAC PEG_TX#_2 M47 1 2 PEG_M_TXN2 18 CFG16 (FSB Dynamic ODT) 0 = Disabled
H25 M40 PEG_TXN3 C1292 1 2 0.1U_0402_16V4Z PEG_M_TXN3 18
TVB_DAC PEG_TX#_3 PEG_TXN4 C1293 0.1U_0402_16V4Z
K25 M42 1 2 1 = Enabled
TVC_DAC PEG_TX#_4 PEG_M_TXN4 18
*
TV

R48 PEG_TXN5 C1294 1 2 0.1U_0402_16V4Z PEG_M_TXN5 18

PEG_TX#_5 PEG_TXN6 C1295 0.1U_0402_16V4Z
H24 TV_RTN PEG_TX#_6 N38 1 2 PEG_M_TXN6 18
T40 PEG_TXN7 C1296 1 2 0.1U_0402_16V4Z PEG_M_TXN7 18 CFG[18:17] Reserved
PEG_TX#_7 PEG_TXN8 C1297 0.1U_0402_16V4Z
PEG_TX#_8 U37 1 2 PEG_M_TXN8 18
U40 PEG_TXN9 C1298 1 2 0.1U_0402_16V4Z PEG_M_TXN9 18
PEG_TX#_9 PEG_TXN10 C1299 0.1U_0402_16V4Z
C31 Y40 1 2 CFG19 (DMI Lane Reversal) 0 = Normal Operation
E32
TV_DCONSEL_0
TV_DCONSEL_1
PEG_TX#_10
PEG_TX#_11 AA46
AA37
PEG_TXN11
PEG_TXN12
C1300
C1301
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN10 18
PEG_M_TXN11 18
PEG_M_TXN12 18 (Lane number in Order)
*
PEG_TX#_12 PEG_TXN13 C1302 0.1U_0402_16V4Z
PEG_TX#_13 AA40 1 2 PEG_M_TXN13 18
AD43 PEG_TXN14 C1303 1 2 0.1U_0402_16V4Z PEG_M_TXN14 18 1 = Reverse Lane
PEG_TX#_14 PEG_TXN15 C1304 0.1U_0402_16V4Z
PEG_TX#_15 AC46 1 2 PEG_M_TXN15 18
E28 CRT_BLUE PEG_TX_0 J42
L46
PEG_TXP0
PEG_TXP1
C1305
C1306
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP0 18
PEG_M_TXP1 18
CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
PEG_TX_1 PEG_TXP2 C1307 0.1U_0402_16V4Z
G28 CRT_GREEN PEG_TX_2 M48 1 2 PEG_M_TXP2 18 1 = PCIE/SDVO are operating simu.
M39 PEG_TXP3 C1308 1 2 0.1U_0402_16V4Z PEG_M_TXP3 18
PEG_TX_3 PEG_TXP4 C1309 0.1U_0402_16V4Z
J28 CRT_RED PEG_TX_4 M43 1 2 PEG_M_TXP4 18
VGA

R47 PEG_TXP5 C1310 1 2 0.1U_0402_16V4Z PEG_M_TXP5 18

PEG_TX_5 PEG_TXP6 C1311 0.1U_0402_16V4Z +3VS
G29 CRT_IRTN PEG_TX_6 N37 1 2 PEG_M_TXP6 18
T39 PEG_TXP7 C1312 1 2 0.1U_0402_16V4Z PEG_M_TXP7 18
PEG_TX_7 PEG_TXP8 C1313 0.1U_0402_16V4Z
H32 CRT_DDC_CLK PEG_TX_8 U36 1 2 PEG_M_TXP8 18
J32 U39 PEG_TXP9 C1314 1 2 0.1U_0402_16V4Z PEG_M_TXP9 18 R65 1 2
CRT_DDC_DATA PEG_TX_9 7 CFG7

1
J29 Y39 PEG_TXP10 C1315 1 2 0.1U_0402_16V4Z PEG_M_TXP10 18 R59 2.21K_0402_1%
CRT_HSYNC PEG_TX_10 PEG_TXP11 C1316 0.1U_0402_16V4Z 4.02K_0402_1%
E29 CRT_TVO_IREF PEG_TX_11 Y46 1 2 PEG_M_TXP11 18
L29 AA36 PEG_TXP12 C1317 1 2 0.1U_0402_16V4Z PEG_M_TXP12 18 R68 1 2
CRT_VSYNC PEG_TX_12 7 CFG9
AA39 PEG_TXP13 C1318 1 2 0.1U_0402_16V4Z PEG_M_TXP13 18 @ 2.21K_0402_1%
PEG_TX_13 PEG_TXP14 C1319 0.1U_0402_16V4Z
AD42 1 2 PEG_M_TXP14 18

2
B PEG_TX_14 PEG_TXP15 C1320 0.1U_0402_16V4Z CFG5 R71 B
PEG_TX_15 AD46 1 2 PEG_M_TXP15 18 7 CFG5 7 CFG10 1 2
@ 2.21K_0402_1%

1
@
CANTIGA ES_FCBGA1329 R63 R74 1 2
7 CFG11
2.21K_0402_1% @ 2.21K_0402_1%

R77 1 2
7 CFG12

2
2.21K_0402_1%

+3VS

R64 1 2 R66 1 2
7 CFG19 7 CFG13
@ 4.02K_0402_1% 2.21K_0402_1%

R67 1 2 R69 1 2
7 CFG20 7 CFG14
@ 4.02K_0402_1% @ 2.21K_0402_1%

R70 1 2 R72 1 2
7 CFG16 7 CFG15
4.02K_0402_1% @ 2.21K_0402_1%

R73 1 2 R75 1 2
7 CFG6 7 CFG17
@ 2.21K_0402_1% @ 2.21K_0402_1%

R76 1 2 R78 1 2
7 CFG8 7 CFG18
@ 2.21K_0402_1% @ 2.21K_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

+VCCP
+V1.05VS_AXF +VCCP
U57H R82
1 2
852mA U13 0_0603_5%
VTT

4.7U_0805_10V4Z
73mA T13 1
VTT

220U_6.3V_M
B27 VCCA_CRT_DAC VTT U12 1 1 1

C107

C110
A26 T12 + C108 C109
VCCA_CRT_DAC VTT
VTT U11
2.68mA T11 10U_0805_10V4Z
VTT 2 2 2 2
A25 U10

CRT
VCCA_DAC_BG VTT
B25 VSSA_DAC_BG VTT T10
D U9 1U_0603_10V4Z D
VTT
VTT T9
VTT U8
F47 64.8mA T8
VCCA_DPLLA VTT
U7

VTT
VTT +1.8V_SM_CK
L48 64.8mA T7 +1.8V

PLL
VCCA_DPLLB VTT R85
VTT U6
+1.05VS_HPLL AD1 24mA T6 10U_0805_10V4Z 1 2
VCCA_HPLL VTT 0_0805_5%
VTT U5
+1.05VS_MPLL AE1 139.2mA T5
VCCA_MPLL VTT
VTT V3 1 @ 1 1
13.2mA U3 C116 C117 C118

A LVDS
VTT

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
J48 VCCA_LVDS VTT V2
@ R87 U2 1 1 1
VTT 2 2 2
+3VS 1 2 J47 VSSA_LVDS VTT T2

C113

C114

C115
0_0603_5% V1
+1.5VS_PEG_BG 414uA VTT 10U_0805_10V4Z 0.1U_0402_16V4Z
VTT U1
R88 2 2 2
+1.5VS 1 2 AD48 VCCA_PEG_BG
0_0603_5%
1

A PEG
C122 +1.5VS_TVDAC +1.5VS
50mA +1.05VS_HPLL +VCCP R90
0.1U_0402_16V4Z +1.05VS_PEGPLL AA48 R89 1 2
2 VCCA_PEG_PLL
1 2
MBK2012121YZF_0805 0_0805_5%
AR20 VCCA_SM 1 1
AP20 1 1 C126 C125
VCCA_SM 720mA C123 C124
AN20

+1.05VS_A_SM
AR17
AP17
VCCA_SM
VCCA_SM
VCCA_SM
POWER 0.1U_0402_16V4Z
2 2
10U_0805_10V4Z
0.1U_0402_16V4Z
2 2
10U_0805_10V4Z

+VCCP AN17 VCCA_SM

AT16 VCCA_SM
AR16 VCCA_SM

A SM
R91 1 2 4.7U_0805_10V4Z AP16
C
0_0805_5% VCCA_SM C
1 1 1
C128 C129 C130

+VCC_PEG +VCCP
2 2 2
321.35mA +1.05VS_MPLL +VCCP R92
10U_0805_10V4Z 1U_0603_10V4Z AP28 R93 1 2
VCCA_SM_CK 0_0805_5%
AN28 VCCA_SM_CK VCC_AXF B22 +V1.05VS_AXF 1 2
AP25 26mA B21 MBK2012121YZF_0805 1

AXF
VCCA_SM_CK VCC_AXF
AN25 VCCA_SM_CK VCC_AXF A21 1
+1.05VS_A_SM_CK 26mA C131+ C132
AN24 VCCA_SM_CK 1 1
AM28 124mA C133 C134
VCCA_SM_CK_NCTF 220U_6.3V_M 10U_0805_10V4Z
AM26 VCCA_SM_CK_NCTF 2 2
R94 1
0_0603_5%
2 1U_0603_10V4Z AM25
AL25
VCCA_SM_CK_NCTF A CK BF21
0.1U_0402_16V4Z
2 2
10U_0805_10V4Z

SM CK
VCCA_SM_CK_NCTF VCC_SM_CK +1.8V_SM_CK
AM24 VCCA_SM_CK_NCTF VCC_SM_CK BH20
1 1 1 1 AL24 VCCA_SM_CK_NCTF VCC_SM_CK BG20
C135 C136 C137 C138 AM23 BF20
VCCA_SM_CK_NCTF VCC_SM_CK
AL23 VCCA_SM_CK_NCTF
1U_0603_10V4Z 118.8mA
2 2 2 2 TVA 24.15mA
+1.05VS_PEGPLL +VCCP +1.05VS_DMI +VCCP
TVB 39.48mA VCC_TX_LVDS K47
10U_0805_10V4Z 0.1U_0402_16V4Z B24 TVX 24.15mA L7 R95
VCCA_TV_DAC +3VS_HV
A24 C35 1 2 1 2
TV

VCCA_TV_DAC 105.3mA VCC_HV BLM18PG121SN1D_0603 0_0603_5%

VCC_HV B35
A35
HV

R2090 0_0402_5% VCC_HV

1 1

0.1U_0402_16V4Z
1 2 A32 50mA C140 C141 1
HDA

VCC_HDA C142
VCC_PEG V48 +VCC_PEG 1

C139
1732mA U48 0.1U_0402_16V4Z
VCC_PEG 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z
V47
PEG

VCC_PEG 2
10/08 add this power rail U47
D TV/CRT

58.67mA VCC_PEG 2
+1.5VS_TVDAC M25 VCCD_TVDAC VCC_PEG U46

B +1.5VS_QDAC L28 48.363mA B

VCCD_QDAC
VCC_DMI AH48 +1.05VS_DMI
+1.05VS_HPLL AF1 157.2mA AF48
VCCD_HPLL VCC_DMI
AH47
DMI

50mA VCC_DMI
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI AG47
+VCCP_D
456mA
M38
LVDS

VCCD_LVDS D3 R96 R97

L37 A8
VTTLF

VCCD_LVDS VTTLF
VTTLF L1 +VCCP 2 1 1 2 1 2 +3VS_HV
60.31mA AB2 10_0402_5% 0_0402_5%
VTTLF CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1212 Montevina DG 1 1 1
C143

C144

C145

CANTIGA ES_FCBGA1329

+1.5VS_QDAC +1.5VS 2 2 2

R2093
1 2
100_0603_1%
0.01U_0402_16V7K

0.1U_0402_16V4Z
C2116

C2117

1 1

2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

U57G
Extnal Graphic: 1210.34mA 3000mA
integrated Graphic: 1930.4mA AP33 W28
VCC_SM VCC_AXG_NCTF
AN33 VCC_SM VCC_AXG_NCTF V28
+1.8V BH32 VCC_SM VCC_AXG_NCTF W26
U57F BG32 V26
+VCCP VCC_SM VCC_AXG_NCTF
BF32 VCC_SM VCC_AXG_NCTF W25

0.01U_0402_16V7K
10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 VCC_SM VCC_AXG_NCTF V25
1 1 1 BC32 VCC_SM VCC_AXG_NCTF W24

C159

C160

C161
D
AG34 C158 + BB32 V24 D
VCC 330U_4V_M VCC_SM VCC_AXG_NCTF
AC34 VCC BA32 VCC_SM VCC_AXG_NCTF W23
AB34 VCC AY32 VCC_SM VCC_AXG_NCTF V23
2 2 2 2
AA34 VCC AW32 VCC_SM VCC_AXG_NCTF AM21
Y34 VCC AV32 VCC_SM VCC_AXG_NCTF AL21
V34 VCC AU32 VCC_SM VCC_AXG_NCTF AK21
U34 VCC AT32 VCC_SM VCC_AXG_NCTF W21
AM33 0317 change value AR32 V21
VCC VCC_SM VCC_AXG_NCTF
AK33 VCC AP32 VCC_SM VCC_AXG_NCTF U21

POWER
AJ33 VCC AN32 VCC_SM VCC_AXG_NCTF AM20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC BH31 VCC_SM VCC_AXG_NCTF AK20
220U_6.3V_M

10U_0805_10V4Z

1 AF33 BG31 W20

VCC CORE
VCC VCC_SM VCC_AXG_NCTF
1 1 1 1 BF31 VCC_SM VCC_AXG_NCTF U20
C162

C163

C164

C165

+ C166
AE33 VCC BG30 VCC_SM VCC_AXG_NCTF AM19
AC33 VCC BH29 VCC_SM VCC_AXG_NCTF AL19
AA33 VCC BG29 VCC_SM VCC_AXG_NCTF AK19
2 2 2 2 2
Y33 VCC BF29 VCC_SM VCC_AXG_NCTF AJ19
W33 VCC BD29 VCC_SM VCC_AXG_NCTF AH19
V33 BC29 AG19

VCC SM
VCC VCC_SM VCC_AXG_NCTF
U33 VCC BB29 VCC_SM VCC_AXG_NCTF AF19
AH28 VCC BA29 VCC_SM VCC_AXG_NCTF AE19
AF28 VCC AY29 VCC_SM VCC_AXG_NCTF AB19
AC28 VCC AW29 VCC_SM VCC_AXG_NCTF AA19
AA28 VCC AV29 VCC_SM VCC_AXG_NCTF Y19
AJ26 VCC AU29 VCC_SM VCC_AXG_NCTF W19
AG26 VCC AT29 VCC_SM VCC_AXG_NCTF V19
AE26 VCC AR29 VCC_SM VCC_AXG_NCTF U19
AC26 VCC AP29 VCC_SM VCC_AXG_NCTF AM17
AH25 VCC VCC_AXG_NCTF AK17
AG25 VCC BA36 VCC_SM/NC VCC_AXG_NCTF AH17
AF25 VCC BB24 VCC_SM/NC VCC_AXG_NCTF AG17
AG24 VCC BD16 VCC_SM/NC VCC_AXG_NCTF AF17
C
AJ23 +VCCP BB21 AE17 C
VCC VCC_SM/NC VCC_AXG_NCTF
AH23 VCC AW16 VCC_SM/NC VCC_AXG_NCTF AC17
AF23 VCC AW13 VCC_SM/NC VCC_AXG_NCTF AB17
POWER
VCC_NCTF AM32 AT13 VCC_SM/NC VCC_AXG_NCTF Y17
T32 VCC VCC_NCTF AL32 VCC_AXG_NCTF W17
VCC_NCTF AK32 6326.84mA VCC_AXG_NCTF V17

VCC GFX NCTF

VCC_NCTF AJ32 VCC_AXG_NCTF AM16
VCC_NCTF AH32 Y26 VCC_AXG VCC_AXG_NCTF AL16
VCC_NCTF AG32 AE25 VCC_AXG VCC_AXG_NCTF AK16
VCC_NCTF AE32 AB25 VCC_AXG VCC_AXG_NCTF AJ16
VCC_NCTF AC32 AA25 VCC_AXG VCC_AXG_NCTF AH16
VCC_NCTF AA32 AE24 VCC_AXG VCC_AXG_NCTF AG16
VCC_NCTF Y32 AC24 VCC_AXG VCC_AXG_NCTF AF16
VCC_NCTF W32 AA24 VCC_AXG VCC_AXG_NCTF AE16
VCC_NCTF U32 Y24 VCC_AXG VCC_AXG_NCTF AC16
VCC_NCTF AM30 AE23 VCC_AXG VCC_AXG_NCTF AB16
VCC_NCTF AL30 AC23 VCC_AXG VCC_AXG_NCTF AA16
VCC_NCTF AK30 AB23 VCC_AXG VCC_AXG_NCTF Y16
VCC_NCTF AH30 AA23 VCC_AXG VCC_AXG_NCTF W16
VCC_NCTF AG30 AJ21 VCC_AXG VCC_AXG_NCTF V16
VCC_NCTF AF30 AG21 VCC_AXG VCC_AXG_NCTF U16
VCC_NCTF AE30 AE21 VCC_AXG
VCC_NCTF AC30 AC21 VCC_AXG
VCC_NCTF AB30 AA21 VCC_AXG
VCC_NCTF AA30 Y21 VCC_AXG
Y30 AH20
VCC NCTF

VCC_NCTF VCC_AXG
VCC_NCTF W30 AF20 VCC_AXG
VCC_NCTF V30 AE20 VCC_AXG
VCC_NCTF U30 AC20 VCC_AXG
VCC_NCTF AL29 AB20 VCC_AXG
VCC_NCTF AK29 AA20 VCC_AXG
VCC_NCTF AJ29 T17 VCC_AXG
B B
VCC_NCTF AH29 T16 VCC_AXG
VCC_NCTF AG29 AM15 VCC_AXG
VCC_NCTF AE29 AL15 VCC_AXG
VCC_NCTF AC29 AE15 VCC_AXG
VCC_NCTF AA29 AJ15 VCC_AXG
VCC_NCTF Y29 AH15 VCC_AXG
VCC_NCTF W29 AG15 VCC_AXG
VCC_NCTF V29 AF15 VCC_AXG
VCC_NCTF AL28 AB15 VCC_AXG
VCC_NCTF AK28 AA15 VCC_AXG
AL26 Y15

VCC GFX
VCC_NCTF VCC_AXG
VCC_NCTF AK26 V15 VCC_AXG
VCC_NCTF AK25 U15 VCC_AXG
VCC_NCTF AK24 AN14 VCC_AXG
VCC_NCTF AK23 AM14 VCC_AXG
U14 VCC_AXG VCC_SM_LF AV44 VCCSM_LF1
T14 BA37 VCCSM_LF2

VCC SM LF
VCC_AXG VCC_SM_LF
VCC_SM_LF AM40 VCCSM_LF3
VCC_SM_LF AV21 VCCSM_LF4
VCC_SM_LF AY5 VCCSM_LF5
VCC_SM_LF AM10 VCCSM_LF6
CANTIGA ES_FCBGA1329
VCC_SM_LF BB13 VCCSM_LF7

C177 0.1U_0402_16V4Z

C178 0.1U_0402_16V4Z

C172

C173

C174

C175

C176
1 1 1 1 1 1 1

PAD T43 AJ14 VCC_AXG_SENSE

PAD T44 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 11 of 58
5 4 3 2 1
 5 4 3 2 1

U57J
U57I BG21 AH8
VSS VSS
L12 VSS VSS Y8
AU48 VSS VSS AM36 AW21 VSS VSS L8
AR48 VSS VSS AE36 AU21 VSS VSS E8
AL48 VSS VSS P36 AP21 VSS VSS B8
BB47 VSS VSS L36 AN21 VSS VSS AY7
AW47 VSS VSS J36 AH21 VSS VSS AU7
AN47 VSS VSS F36 AF21 VSS VSS AN7
AJ47 VSS VSS B36 AB21 VSS VSS AJ7
AF47 VSS VSS AH35 R21 VSS VSS AE7
D D
AD47 VSS VSS AA35 M21 VSS VSS AA7
AB47 VSS VSS Y35 J21 VSS VSS N7
Y47 VSS VSS U35 G21 VSS VSS J7
T47 VSS VSS T35 BC20 VSS VSS BG6
N47 VSS VSS BF34 BA20 VSS VSS BD6
L47 VSS VSS AM34 AW20 VSS VSS AV6
G47 VSS VSS AJ34 AT20 VSS VSS AT6
BD46 VSS VSS AF34 AJ20 VSS VSS AM6
BA46 VSS VSS AE34 AG20 VSS VSS M6
AY46 VSS VSS W34 Y20 VSS VSS C6
AV46 VSS VSS B34 N20 VSS VSS BA5
AR46 VSS VSS A34 K20 VSS VSS AH5
AM46 VSS VSS BG33 F20 VSS VSS AD5
V46 VSS VSS BC33 C20 VSS VSS Y5
R46 VSS VSS BA33 A20 VSS VSS L5
P46 VSS VSS AV33 BG19 VSS VSS J5
H46 VSS VSS AR33 A18 VSS VSS H5
F46 VSS VSS AL33 BG17 VSS VSS F5
BF44 VSS VSS AH33 BC17 VSS VSS BE4
AH44 VSS VSS AB33 AW17 VSS
AD44 P33 AT17 BC3
AA44
Y44
VSS
VSS
VSS
VSS
VSS
VSS
L33
H33
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
U44 VSS VSS N32 H17 VSS VSS R3
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS

VSS
VSS
VSS
VSS
F3
BA2
BC43 VSS VSS A31 VSS AW2
AV43 VSS VSS AN29 AU16 VSS VSS AU2
AU43 VSS VSS T29 AN16 VSS VSS AR2
AM43 VSS VSS N29 N16 VSS VSS AP2
J43 VSS VSS K29 K16 VSS VSS AJ2
C C
C43 VSS VSS H29 G16 VSS VSS AH2
BG42 VSS VSS F29 E16 VSS VSS AF2
AY42 VSS VSS A29 BG15 VSS VSS AE2
AT42 VSS VSS BG28 AC15 VSS VSS AD2
AN42 VSS VSS BD28 W15 VSS VSS AC2
AJ42 VSS VSS BA28 A15 VSS VSS Y2
AE42 VSS VSS AV28 BG14 VSS VSS M2
N42 VSS VSS AT28 AA14 VSS VSS K2
L42 VSS VSS AR28 C14 VSS VSS AM1
BD41 VSS VSS AJ28 BG13 VSS VSS AA1
AU41 VSS VSS AG28 BC13 VSS VSS P1
AM41 VSS VSS AE28 BA13 VSS VSS H1
AH41 VSS VSS AB28
AD41 VSS VSS Y28 VSS U24
AA41 VSS VSS P28 AN13 VSS VSS U28
Y41 VSS VSS K28 AJ13 VSS VSS U25
U41 VSS VSS H28 AE13 VSS VSS U29
T41 VSS VSS F28 N13 VSS
M41 VSS VSS C28 L13 VSS
G41 VSS VSS BF26 G13 VSS VSS_NCTF AF32
B41 VSS VSS AH26 E13 VSS VSS_NCTF AB32
BG40 VSS VSS AF26 BF12 VSS VSS_NCTF V32
BB40 VSS VSS AB26 AV12 VSS VSS_NCTF AJ30
AV40 VSS VSS AA26 AT12 VSS VSS_NCTF AM29
AN40 VSS VSS C26 AM12 VSS VSS_NCTF AF29
H40 B26 AA12 AB29

VSS NCTF
VSS VSS VSS VSS_NCTF
E40 VSS VSS BH25 J12 VSS VSS_NCTF U26
AT39 VSS VSS BD25 A12 VSS VSS_NCTF U23
AM39 VSS VSS BB25 BD11 VSS VSS_NCTF AL20
AJ39 VSS VSS AV25 BB11 VSS VSS_NCTF V20
AE39 VSS VSS AR25 AY11 VSS VSS_NCTF AC19
N39 VSS VSS AJ25 AN11 VSS VSS_NCTF AL17
B B
L39 VSS VSS AC25 AH11 VSS VSS_NCTF AJ17
B39 VSS VSS Y25 VSS_NCTF AA17
BH38 VSS VSS N25 Y11 VSS VSS_NCTF U17
BC38 VSS VSS L25 N11 VSS
BA38 VSS VSS J25 G11 VSS
AU38 G25 C11 BH48

VSS SCB
VSS VSS VSS VSS_SCB
AH38 VSS VSS E25 BG10 VSS VSS_SCB BH1
AD38 VSS VSS BF24 AV10 VSS VSS_SCB A48
AA38 VSS VSS AD12 AT10 VSS VSS_SCB C1
Y38 VSS VSS AY24 AJ10 VSS VSS_SCB A3
U38 VSS VSS AT24 AE10 VSS
T38 VSS VSS AJ24 AA10 VSS NC E1
J38 VSS VSS AH24 M10 VSS NC D2
F38 VSS VSS AF24 BF9 VSS NC C3
C38 VSS VSS AB24 BC9 VSS NC B4
BF37 VSS VSS R24 AN9 VSS NC A5
BB37 VSS VSS L24 AM9 VSS NC A6
AW37 VSS VSS K24 AD9 VSS NC A43
AT37 VSS VSS J24 G9 VSS NC A44
AN37 G24 B9 B45

NC
VSS VSS VSS NC
AJ37 VSS VSS F24 BH8 VSS NC C46
H37 VSS VSS E24 BB8 VSS NC D47
C37 VSS VSS BH23 AV8 VSS NC B47
BG36 VSS VSS AG23 AT8 VSS NC A46
BD36 VSS VSS Y23 NC F48
AK15 VSS VSS B23 NC E48
AU36 VSS VSS A23 NC C48
VSS AJ6 NC B48

CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 12 of 58
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

8 DDR_A_DQS#[0..7] +V_DDR_MCH_REF
+V_DDR_MCH_REF 7,14

8 DDR_A_D[0..63] JDIMM1 CONN@

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2

C179

C180
8 DDR_A_DM[0..7] 3 4 DDR_A_D6 1 1
DDR_A_D4 VSS DQ4 DDR_A_D0
5 DQ0 DQ5 6
8 DDR_A_DQS[0..7] DDR_A_D1 7 8
DQ1 VSS DDR_A_DM0
9 VSS DM0 10
DDR_A_DQS#0 2 2
8 DDR_A_MA[0..14] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
Layout Note: 19 DQ3 DQ12 20
DDR_A_D12
21 VSS DQ13 22
Place near DDR_A_D8 23 24
DDR_A_D14 DQ8 VSS DDR_A_DM1
JP3 25 DQ9 DM1 26
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 7
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 7
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C182

C183

C184

C185

C186

C187

C188

C189

C190
+ C181 47 48
330U_D2_2.5VM_R15 DDR_A_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#0 7
DDR_A_DQS2 51 52 DDR_A_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
1113 Change type for layout 53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
C
Layout Note: DDR_CKE0_DIMMA
77 VSS VSS 78
DDR_CKE1_DIMMA C
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
Place one cap close to every 81 82
VDD VDD
2 pullup DDR_A_BS2
83 NC NC/A15 84
DDR_A_MA14
8 DDR_A_BS2 85 BA2 NC/A14 86
resistors terminated to +0.9VS 87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
+0.9V A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 8
5 10 DDR_A_BS0 107 108 DDR_A_RAS#
8 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

111 VDD VDD 112

DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
7 M_ODT1 M_ODT1 119 120
NC/ODT1 NC
121 VSS VSS 122
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_D37 DDR_A_D39
123 DQ32 DQ36 124
C191

C192

C193

C194

C195

C196

C197

C198

C199

C200

C201

C202

C203

DDR_A_D36 125 126 DDR_A_D38

DQ33 DQ37
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D34
DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
+0.9V
Layout Note: DDR_A_D41
149 VSS VSS 150
DDR_A_D47
151 DQ42 DQ46 152
56_0404_4P2R_5% RP1 RP2 56_0404_4P2R_5% Place these resistor DDR_A_D46 153 154 DDR_A_D42
DDR_A_MA8 DQ43 DQ47
1 4 4 1 DDR_A_BS2 closely JP3,all 155 VSS VSS 156
DDR_A_MA5 2 3 3 2 DDR_CKE0_DIMMA DDR_A_D49 157 158 DDR_A_D52
trace length Max=1.5" DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
56_0404_4P2R_5% RP3 RP4 56_0404_4P2R_5% 163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 7
DDR_A_MA1 1 4 4 1 DDR_A_MA7 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_MA3 2 3 3 2 DDR_A_MA6 DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
56_0404_4P2R_5% RP5 RP6 56_0404_4P2R_5% DDR_A_D54 173 174 DDR_A_D51
DDR_A_RAS# DQ50 DQ54
1 4 4 1 DDR_A_MA9 DDR_A_D50 175 DQ51 DQ55 176 DDR_A_D55
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 177 178
DDR_A_D61 VSS VSS DDR_A_D57
179 DQ56 DQ60 180
DDR_A_D60 181 182 DDR_A_D56
56_0404_4P2R_5% RP7 RP8 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_A_BS0 1 4 4 1 DDR_A_MA4 DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_MA10 DM7 DQS7#
2 3 3 2 DDR_A_MA2 187 VSS DQS7 188 DDR_A_DQS7
DDR_A_D59 189 190
DDR_A_D58 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
56_0404_4P2R_5% RP9 RP10 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA0 14,15 CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_BS1 CLK_SMBCLK 197 198
14,15 CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
201 G1 G2 202

1
10K_0402_5%

10K_0402_5%
2.2U_0603_6.3V4Z

56_0404_4P2R_5% RP11 RP12 56_0404_4P2R_5% 1 1

0.1U_0402_16V4Z

DDR_CS1_DIMMA# 2 3 4 1 M_ODT0

R106

R107
A M_ODT1 A
1 4 3 2 DDR_A_MA13 C204 C205 FOX_AS0A426-N4RN-7F~D
2 2
SO-DIMM A

2
RP13 56_0404_4P2R_5%
4 1 DDR_CKE1_DIMMA
DDR_A_MA11 1 2 3 2 DDR_A_MA14

R108 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
8 DDR_B_DQS#[0..7]

8 DDR_B_D[0..63] +V_DDR_MCH_REF
+V_DDR_MCH_REF 7,13

8 DDR_B_DM[0..7] JDIMM2 CONN@

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
8 DDR_B_DQS[0..7] 3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
5 DQ0 DQ5 6

C206

C207
8 DDR_B_MA[0..14] DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
Layout Note: DDR_B_D3
17 DQ2 VSS 18
DDR_B_D12
19 DQ3 DQ12 20
Place near 21 22 DDR_B_D13
DDR_B_D8 VSS DQ13
JP10 23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 7
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS
5
41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C208

C209

C210

C211

C212

C213

C214

C215

C216
47 VSS VSS 48
+ C244 DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#1 7
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
2 DDR_B_D18 DDR_B_D22
55 DQ18 DQ22 56
DDR_B_D19 57 58 DDR_B_D23
DQ19 DQ23
59 VSS VSS 60
330U_4V_M DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
Layout Note: DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C Place one cap close to every 77 78 C
DDR_CKE2_DIMMB VSS VSS DDR_CKE3_DIMMB
2 pullup 7 DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB 7
81 VDD VDD 82
resistors terminated to +0.9VS 83 NC NC/A15 84
DDR_B_BS2 85 86 DDR_B_MA14
8 DDR_B_BS2 BA2 NC/A14
87 VDD VDD 88 0612 add
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
+0.9V DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
5 10 103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 8
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_BS0 107 108 DDR_B_RAS#

8 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
1 1 1 1 1 1 1 1 1 1 1 1 1 111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
2 2 2 2 2 2 2 2 2 2 2 2 2 M_ODT3
7 M_ODT3 119 NC/ODT1 NC 120
C217

C218

C219

C220

C221

C222

C223

C224

C225

C226

C227

C228

C229

121 VSS VSS 122

DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
Layout Note: DDR_B_D41
141 DQ40 DQ45 142
143 DQ41 VSS 144
Place these resistor 145 146 DDR_B_DQS#5
+0.9V DDR_B_DM5 VSS DQS5# DDR_B_DQS5
closely JP3,all 147 DM5 DQS5 148
149 VSS VSS 150
trace length Max=1.5" DDR_B_D42 151 DQ42 DQ46 152 DDR_B_D46
56_0404_4P2R_5% RP14 RP15 56_0404_4P2R_5% DDR_B_D43 153 154 DDR_B_D47
DDR_B_MA1 DDR_B_MA9 DQ43 DQ47
1 4 4 1 155 VSS VSS 156
DDR_B_MA3 2 3 3 2 DDR_B_MA12 DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
56_0404_4P2R_5% RP16 RP17 56_0404_4P2R_5% 163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 7
DDR_B_BS0 1 4 4 1 DDR_B_MA14 165 166 M_CLK_DDR#3
VSS CK1# M_CLK_DDR#3 7
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
56_0404_4P2R_5% RP18 RP19 56_0404_4P2R_5% DDR_B_D51 173 174 DDR_B_D54
DDR_B_MA0 DDR_B_MA5 DDR_B_D50 DQ50 DQ54 DDR_B_D55
1 4 4 1 175 DQ51 DQ55 176
DDR_B_BS1 2 3 3 2 DDR_B_MA8 177 178
DDR_B_D56 VSS VSS DDR_B_D60
179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
56_0404_4P2R_5% RP20 RP21 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_CS2_DIMMB# 2 DDR_B_MA6 DM7 DQS7# DDR_B_DQS7
3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
56_0404_4P2R_5% RP22 RP23 56_0404_4P2R_5% 193 194 DDR_B_D63
DDR_B_CAS# DDR_B_MA4 CLK_SMBDATA VSS DQ63
1 4 4 1 13,15 CLK_SMBDATA 195 SDA VSS 196
DDR_B_WE# 2 3 3 2 DDR_B_MA2 CLK_SMBCLK 197 198 R109
13,15 CLK_SMBCLK SCL SA0
+3VS 199 VDDSPD SA1 200 1 2 +3VS

G1
G2

1
10K_0402_5%
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

56_0404_4P2R_5% RP24 RP25 56_0404_4P2R_5% 1 1 10K_0402_5%

R110
A DDR_CS3_DIMMB# 2 M_ODT2 A
3 4 1

201
202
M_ODT3 1 4 3 2 DDR_B_MA13 C230 C231 FOX_AS0A426-N8RN-7F
2 2

2
RP26 56_0404_4P2R_5%

DDR_CKE3_DIMMB 1 2
4
3
1
2
DDR_B_BS2
DDR_CKE2_DIMMB
SO-DIMM B
R111 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB R112
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1
0_0805_5%
2
1 1 1 1 1 1 1
C234 C235 C236 C237 C238 C239 C240
0 0 0 266 100 33.3 14.318 96.0 48.0 03/02 change
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
Routing the trace at least 10mil +VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0
CLK_XTAL_OUT

D CLK_XTAL_IN R113
Place close to U51 D
0 1 1 166 100 33.3 14.318 96.0 48.0
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
Y1
0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 2 1 14.31818MHZ_16P C245 C246 C247 C248 C249 C250 C944

2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1 1 0 400 100 33.3 14.318 96.0 48.0 C251 C252

18P_0402_50V8J 18P_0402_50V8J
1 1
1 1 1 Reserved
Vendor suggests 22pF
R118 +3VS_CK505 +1.05VS_CK505
1 2 +VCCP R2002 1 2 0_0402_5%
CLK_PCIE_CR# 33
R2003 1 2 0_0402_5% Card Reader
CLK_PCIE_CR 33
1

56_0402_5% CLK_SRC @ R2004 1 2 0_0402_5%

CLK_CPU_XDP 4
CLRP1 CLK_SRC# @ R2005 1 2 0_0402_5% XDP/ITP
CLK_CPU_XDP# 4
NO SHORT PADS R863 1 2 475_0402_1% R_CLKREQ#_7 CLK_MCH_3GPLL
7 CLKREQ#_7 CLK_MCH_3GPLL 7
2

R121 CLK_MCH_BCLK# CLK_MCH_3GPLL# 3G_PLL

7 CLK_MCH_BCLK# CLK_MCH_3GPLL# 7
FSA 1 2 1 2 NB CLK_MCH_BCLK R_CLKREQ#_6 R862 1 2 475_0402_1%
MCH_CLKSEL0 7 7 CLK_MCH_BCLK CLKREQ#_6 32
2.2K_0402_5% R122 CLK_CPU_BCLK#
4 CLK_CPU_BCLK# CLK_PCIE_MCARD2 32
R124 1K_0402_5% CPU CLK_CPU_BCLK TV
4 CLK_CPU_BCLK CLK_PCIE_MCARD2# 32
5 CPU_BSEL0 1 2 +3VS_CK505
0_0402_5%
1

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
R130 U51
1K_0402_5% +3VS_CK505 +1.05VS_CK505

SRC_8/CPU_ITP
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO

VSS_SRC

VDD_SRC
CPU_0

CPU_1

CLKREQ_7#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
SRC_6#
SRC_8#/CPU_ITP#
C C
2

@ R119 1 2 0_0402_5%
28,51 VGATE @ R120 1 2 0_0402_5%
+VCCP 51 CLK_ENABLE# R123 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#
28 CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# 28
FSB 2 53 H_STP_CPU#
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 28
3 VSS_REF VDD_SRC_IO 52
2

@ CLK_XTAL_OUT 4 51 CLK_PCIE_MCARD0#
XTAL_OUT SRC_10# CLK_PCIE_MCARD0# 32
R142 CLK_XTAL_IN 5 50 CLK_PCIE_MCARD0 WLAN
XTAL_IN SRC_10 CLK_PCIE_MCARD0 32
1K_0402_5% 6 49 R_CLKREQ#_10 R865 1 2 475_0402_1%
VDD_REF CLKREQ_10# CLKREQ#_10 32
R140 1 2 33_0402_1% FSC 7 48 CLK_PCIE_MCARD1
28 CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_MCARD1 35
8 47 CLK_PCIE_MCARD1# Robson
CLK_PCIE_MCARD1# 35
1

FSB CLK_SMBDATA REF_1 SRC_11# R_CLKREQ#_11 R866

1 2 MCH_CLKSEL1 7 13,14 CLK_SMBDATA 9 SDA CLKREQ_11# 46 1 2 475_0402_1% CLKREQ#_11 35
R148 CLK_SMBCLK 10 45 CLK_PCIE_LAN#
13,14 CLK_SMBCLK SCL SRC_9# CLK_PCIE_LAN# 31
R151 1K_0402_5% 11 44 CLK_PCIE_LAN GLAN
NC SRC_9 CLK_PCIE_LAN 31
1 2 @ 12 43 R_CLKREQ#_9 R864 1 2 475_0402_1%
5 CPU_BSEL1 VDD_PCI CLKREQ_9# CLKREQ#_9 31
0_0402_5% R127 1 2 33_0402_1% 13 42
PCI_1 VSS_SRC
1

39 CLK_DEBUG_PORT1 R126 1 2 33_0402_1% PCI2_TME 14 PCI_2 CLKREQ_4# 41 R_CLKREQ#_4 R861 1 2 475_0402_1% CLKREQ#_4 32
@ 32 CLK_DEBUG_PORT0 R131 27_SEL CLK_PCIE_NCARD#
1 2 33_0402_1% 15 PCI_3 SRC_4# 40 CLK_PCIE_NCARD# 32
R154 40 CLK_PCI_EC PCI_CLK3 CLK_PCIE_NCARD
16 PCI_4/SEL_LCDCL SRC_4 39 CLK_PCIE_NCARD 32 New Card

USB_1/CLKREQ_A#
0_0402_5% R133 1 2 33_0402_1% ITP_EN 17 38

LCDCLK#/27M_SS
26 CLK_PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 37 R_CLKREQ#_C R860 1 2 475_0402_1% CLKREQ#_C 28
2

VSS_PCI CLKREQ_3#

SRC_0/DOT_96

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
1025 Add R127 to meet Intel CLK design

VDD_PLL3

VSS_PLL3

VSS_SRC
+VCCP

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
1

@
R169 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1K_0402_5% +3VS_CK505

B R170 CLK_PCIE_SATA# B
CLK_PCIE_SATA# 27
2

FSC 1 2 1 2 R136 1 2 33_0402_1% FSA CLK_PCIE_SATA SATA

MCH_CLKSEL2 7 28 CLK_48M_ICH CLK_PCIE_SATA 27
10K_0402_5% R171
R174 1K_0402_5% CLK_PCIE_ICH#
CLK_PCIE_ICH# 28
1 2 +1.05VS_CK505 CLK_PCIE_ICH ICH
5 CPU_BSEL2 CLK_PCIE_ICH 28
0_0402_5% +1.05VS_CK505
1

R2102
@ VGA (Discrete) CLK_PCIE_VGA R2006 1 2 0_0402_5% CLK_VGA 27M_SSC_CLOCK 1 2 33_0402_1% 27M_SSC
18 CLK_PCIE_VGA 27M_SSC 19
R175 CLK_PCIE_VGA# R2007 1 2 0_0402_5% CLK_VGA# 27M_CLK_CLOCK 1 2 33_0402_1% 27M_CLK 27MHZ For VGA
18 CLK_PCIE_VGA# 27M_CLK 19
0_0402_5% R2103
2

1212 Add R and R

+3VS
+3VS

0 = SRC8/SRC8#
ITP_EN +3VS
1 = ITP/ITP# R158 R159
0 = Enable DOT96 & SRC1(UMA) 2.2K_0402_5% 2.2K_0402_5%
PCI_CLK3 @ C232 CLK_48M_ICH
1 = Enable SRC0 & 27MHz(DIS) 2 1
2

5P_0402_50V8C
@ C233 2 1 CLK_14M_ICH
28,32,35,39 ICH_SMBDATA 6 1 CLK_SMBDATA 4.7P_0402_50V8C
+3VS +3VS @ C241 2 1 CLK_PCI_ICH
5

SB, MINI PCI 2N7002DW-7-F_SOT363-6 4.7P_0402_50V8C

Q75A @ C242 2 1 CLK_PCI_EC
1

@ 28,32,35,39 ICH_SMBCLK 3 4 CLK_SMBCLK 4.7P_0402_50V8C

R176 R178 @ C243 2 1 CLK_DEBUG_PORT0
10K_0402_5% 10K_0402_5% 2N7002DW-7-F_SOT363-6 5P_0402_50V8C
A A
Q75B
2

ITP_EN PCI_CLK3
1

@
R179 R181
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
Clock Generator CK505
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 15 of 58
5 4 3 2 1
 A B C D E

+5VS +RCRT_VCC +CRTVDD

CRT D4 F1 BLUE_CRT
GREEN_CRT
2 1 1 2 W=40mils
Connector CH491D_SC59 1.1A_6VDC_FUSE
1 RED_CRT
Place close to
1106 EMI request 0.1U_0402_16V4Z JCRT

1
C253 2 @ D5 @ D6 @ D7

DAN217_SC59

DAN217_SC59

DAN217_SC59
6
R2069 0_0603_5% 11
1 RED RED_CRT 1
42 RED 1 2 1
+5VS
7

3
R2070 0_0603_5% 12
GREEN 1 2 GREEN_CRT 2
42 GREEN
8
R2071 0_0603_5% 13
BLUE 1 2 BLUE_CRT 3 JCRT
42 BLUE
9 CONN@
14 SUYIN_070546FR015S265ZR
42 D_HSYNC 4
+5VS +5VS 10
42 D_VSYNC 15
C254 C255 5
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 1020 change size to meet NV request 16 GND
17 GND
+3VS
+CRTVDD +CRTVDD +3VS
5
1
U6
P SN74AHCT1G125GW_SOT353-5 R193
OE#

1
2 HSYNC_G_A 2 0_0603_5% D_HSYNC
18 M_HSYNC A Y 4 1
R197 R198 R199 R200
G

5
1
2.2K_0402_5% 2.2K_0402_5%

5
R196 2.2K_0402_5% 2.2K_0402_5%

P
OE#
3

2 4 VSYNC_G_A 1 2 0_0603_5% D_ VSYNC

18 M_VSYNC

2
A Y D_DDCDATA 3 4 M_DDCDATA 18

G
U7 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C262 C263

3
Q69B
1

@ @
R204 R205 5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6

2
51K_0402_5% 51K_0402_5% 2 2

2 D_DDCCLK 2
6 1 M_DDCCLK 18
2

Q69A
1102 R204,R205 no stuff 2N7002DW-7-F_SOT363-6
D_DDCDATA 42
D_DDCCLK 42

CRT Termination/EMI Filter Note: CRT / TV-out should route to JP30

first then to the JP1 & JP2 on system side.

3 3
L13 1 2 HLC0603CSCCR11JT_0603 RED
18 VGA_RED

L15 1 2 HLC0603CSCCR11JT_0603 GREEN

18 VGA_GRN

L17 1 2 HLC0603CSCCR11JT_0603 BLUE

18 VGA_BLU
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1
C314 C315 C316 22P_0402_50V8J @ C317 @ C318 @ C319

22P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J

2

2 2 2 2 2 2

R241 R242 R243 22P_0402_50V8J

10P_0402_50V8J

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 16 of 58
A B C D E
 5 4 3 2 1

1108 EMI request

+LCDVDD +3VS
+LCDVDD +LCDVDD +5VALW Q7
DMIC_CLK SI2301BDS-T1-E3_SOT23-3
change to 0805

1
DMIC_DAT

S
1 3

4.7U_0805_10V4Z
R207 R208 1
1 1 1 1 470_0805_5% 1M_0402_5% C264
@ C2110 C2111 C266 C267 1

G
2
4.7U_0805_10V4Z C265

6 2

2
220P_0402_25V8J 220P_0402_25V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
+LCDVDD INVPWR_B+ 2 2 2 2
Q71A 2
D 2N7002DW-7-F_SOT363-6 D
2 R209 1 2 100K_0402_5%

C270 C271

1
C268

680P_0402_50V7K

680P_0402_50V7K
1 1000P_0402_25V
LVDS CONN

3
2
2 JLVDS 2N7002DW-7-F_SOT363-6
20 ENAVDD 5
1 2 LVDS_A2- Q71B
1 2 LVDS_A2- 18
3 4 LVDS_A2+
LVDS_A2+ 18

4
3 4

1
5 6 LVDS_A1-
5 6 LVDS_A1- 18
7 8 LVDS_A1+ R210
7 8 LVDS_A1+ 18
9 10 LVDS_A0- 2.2K_0402_5%
9 10 LVDS_A0- 18
11 12 LVDS_A0+
11 12 LVDS_A0+ 18
28 USB20_P4 R565 1 2 0_0402_5% USB20_P4_R 13 14 LVDS_ACLK-
LVDS_ACLK- 18

2
R564 1 13 14
28 USB20_N4 2 0_0402_5% USB20_N4_R 15 15 16 16 LVDS_ACLK+
LVDS_ACLK+ 18
17 17 18 18
19 19 20 20 Limited Current < 1A
21 21 22 22
+3VS LVDS_BCLK+ DMIC_DAT
18 LVDS_BCLK+
LVDS_BCLK-
23 23 24 24
DMIC_CLK
DMIC_DAT 34 Avoid Panel display garbage after
18 LVDS_BCLK- 25 25 26 26 DMIC_CLK 34
27 28 +5V_LOGO R462 1 2 +5VS
power on.
LVDS_B0+ 27 28 INV_PWM 100_0805_5%
18 LVDS_B0+ 29 29 30 30 INV_PWM 40
680P_0402_50V7K

LVDS_B0- 31 32 BKOFF# BKOFF# 40

18 LVDS_B0- 31 32
LVDS_B1+ 33 34 DAC_BRIG
18 LVDS_B1+ 33 34 DAC_BRIG 40
1

C269 LVDS_B1- 35 36 +USB_CAM

18 LVDS_B1- 35 36
LVDS_B2+ 37 38 DDC2_CLK
18 LVDS_B2+ 37 38 DDC2_CLK 20 B+ INVPWR_B+
LVDS_B2- 39 40 DDC2_DATA
18 LVDS_B2-
2

39 40 DDC2_DATA 20 @
41 GND GND 42 1 1 1
C L8 0_0805_5% C
1 2
ACES_88242-4001 C272 C2120 Logo LED
CONN@ 470P_0402_50V8J 470P_0402_50V8J
2 2 2 L9
1102 Change size to 0805 1 2
FBMA-L11-201209-221LMA30T_0805

+5VALW
@ C273
0308_Reserve L8 and
1212 EMI request
D17 470P_0402_50V8J +3VS install L9.
4 2 USB20_P4_R
VIN IO1
USB20_N4_R 3 1
IO2 GND

2
PRTR5V0U2X_SOT143-4
R212 R213
2.2K_0402_5% 2.2K_0402_5%

1
DDC2_CLK
DDC2_DATA

B B

USB Camera Power

1106 Add SB control pin
+5VALW +5VS
+USB_CAM
1

1
@ PJP5 PJP4 U54
PAD-OPEN 2x2m PAD-OPEN 2x2m 1 5
IN OUT

1
2 GND 1
R891 C952
2

3 4 53.6_0402_1%
SHDN BYP 4.7U_0805_10V4Z
1 2
C1288 G916-390T1UF_SOT23-5

2
2

10U_0805_10V4Z R2072

1
2 0_0402_5%
R892
24.9_0402_1%
1

@
R2073 1 2 0_0402_5%
28 GPIO20

2
SA000025F00
A A
S IC G916T1UF SOT23 5P ADJUSTABLE
LDO

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 17 of 58
5 4 3 2 1
 A B C D E

+PCIE

LVDS & DAC Interface U71A

1/16 PCI_EXPRESS

PEG Interface 500 mA

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
AK16
AK17
AK21
AK24
1
C1021
0.1U_0402_16V4Z

1
C1022
1
C1023
1U_0603_10V4Z

1
C1024
1
C1025
1
C1026
U71I PEX_IOVDD AK27
7/16 IFPAB
AM12 2 2 2 2 2 2
IFPA_TXC LVDS_ACLK- 17
IFPA_TXC AM11 LVDS_ACLK+ 17 22U_0805_6.3VAM
PEX_IOVDDQ AG11 0.1U_0402_16V4Z 4700P_0402_16V7K 4.7U_0603_6.3V6K
PEX_IOVDDQ AG12
IFPA_TXD0 AL8 LVDS_A0- 17 PEX_IOVDDQ AG13
+1.8VS IFPA_TXD0 AM8 PEX_IOVDDQ AG15
1 LVDS_A0+ 17 1
L61 BLM18PG181SN1D_0603 PEX_IOVDDQ AG16
1 2 IFPAB_PLLVDD AK9 IFPAB_PLLVDD 1600 mA PEX_IOVDDQ AG17
32 mA IFPA_TXD1 AM9 PEX_IOVDDQ AG18 +PCIE
LVDS_A1- 17
IFPAB_RSET AJ11 IFPAB_RSET IFPA_TXD1 AM10 LVDS_A1+ 17 PEX_IOVDDQ AG22

1U_0402_6.3V4Z

4700P_0402_25V7K

220P_0402_50V7K
1 1 1 1 PEX_IOVDDQ AG23

1
C1018 C1033 C1019 C1034 AM16 PEX_RST PEX_IOVDDQ AG24 4700P_0402_16V7K 1U_0603_10V4Z
7,26,31,32,33,35 PLT_RST#
@ IFPA_TXD2 AL10 LVDS_A2- 17
4.7U_0603_6.3V6K R1044 IFPA_TXD2 AK10 LVDS_A2+ 17 AR13 PEX_CLKREQ PEX_IOVDDQ AG25 1 1 1 1 1 1
2 2 2 2 1K_0402_1% AG26 C1027 C1028 C1029 C1030 C1031 C1032
PEX_IOVDDQ
PEX_IOVDDQ AJ14

2
IFPA_TXD3 AL11 PEX_IOVDDQ AJ15
AK11 AJ19 2 2 2 2 2 2
IFPA_TXD3 PEX_IOVDDQ
PEX_IOVDDQ AJ21 22U_0805_6.3VAM
NB9M & NB9P-GS stuff PEX_IOVDDQ AJ22 0.1U_0402_16V4Z 4700P_0402_16V7K 4.7U_0603_6.3V6K
IFPB_TXC AN13 LVDS_BCLK- 17 PEX_IOVDDQ AJ24
IFPB_TXC AP13 LVDS_BCLK+ 17 PEX_IOVDDQ AJ25
+1.8VS R944 1 2 200_0402_1% AJ17 PEX_TSTCLK_OUT PEX_IOVDDQ AJ27
L62 BLM18PG181SN1D_0603 AJ18 PEX_TSTCLK_OUT PEX_IOVDDQ AK18
1 2 IFPAB_IOVDD AG9 IFPA_IOVDD IFPB_TXD4 AP8 LVDS_B0- 17 PEX_IOVDDQ AK20
145 mA IFPB_TXD4 AN8 LVDS_B0+ 17 15 CLK_PCIE_VGA AR16 PEX_REFCLK PEX_IOVDDQ AK23
4.7U_0603_6.3V6K

1U_0402_6.3V4Z

4700P_0402_25V7K

220P_0402_50V7K
1 AG10 IFPB_IOVDD 15 CLK_PCIE_VGA# AR17 PEX_REFCLK PEX_IOVDDQ AK26
C1035 1 1 1 1 PEX_IOVDDQ AL16
C1020 C1036 C1037 C1038 IFPB_TXD5 AN10 LVDS_B1- 17 C1039 1 2 0.1U_0402_16V4Z PEG_C_RXP0 AL17 PEX_TX0
9 PEG_RXP0
4.7U_0603_6.3V6K IFPB_TXD5 AP10 LVDS_B1+ 17 C1040 1 2 0.1U_0402_16V4Z PEG_C_RXN0 AM17 PEX_TX0
2 9 PEG_RXN0
2 2 2 2 AP17
9 PEG_M_TXP0 PEX_RX0
IFPB_TXD6 AR10 LVDS_B2- 17 9 PEG_M_TXN0 AN17 PEX_RX0
IFPB_TXD6 AR11 LVDS_B2+ 17
C1041 1 2 0.1U_0402_16V4Z PEG_C_RXP1 AM18 PEX_TX1
9 PEG_RXP1
C1042 1 2 0.1U_0402_16V4Z PEG_C_RXN1 AM19 PEX_TX1
9 PEG_RXN1
IFPB_TXD7 AP11
IFPB_TXD7 AN11 9 PEG_M_TXP1 AN19 PEX_RX1
9 PEG_M_TXN1 AP19 PEX_RX1
NB9P-GS_BGA 969~D
C1043 1 2 0.1U_0402_16V4Z PEG_C_RXP2 AL19 PEX_TX2 NC_1 A2
9 PEG_RXP2
C1044 1 2 0.1U_0402_16V4Z PEG_C_RXN2 AK19 PEX_TX2 NC_2 AB7
9 PEG_RXN2
NC_3 AD6
9 PEG_M_TXP2 AR19 PEX_RX2 NC_4 AF6
9 PEG_M_TXN2 AR20 PEX_RX2 NC_5 AG6
2 NC_6 AJ5 2
C1045 1 2 0.1U_0402_16V4Z PEG_C_RXP3 AL20 PEX_TX3 NC_7 AK15
9 PEG_RXP3
C1046 1 2 0.1U_0402_16V4Z PEG_C_RXN3 AM20 PEX_TX3 NC_8 AL7
9 PEG_RXN3
NC_9 D35
9 PEG_M_TXP3 AP20 PEX_RX3 NC_10 E35
9 PEG_M_TXN3 AN20 PEX_RX3 NC_11 E7
NC_12 F7
C1047 1 2 0.1U_0402_16V4Z PEG_C_RXP4 AM21 PEX_TX4 NC_13 H32
9 PEG_RXP4
U71G C1048 1 2 0.1U_0402_16V4Z PEG_C_RXN4 AM22 PEX_TX4 NC_14 M7
9 PEG_RXN4
6/16 DACC NC_15 P6
R945 1 2 AG7 DACC_VDD I2CB_SCL G3 9 PEG_M_TXP4 AN22 PEX_RX4 NC_16 P7
10K_0402_5% I2CB_SDA G2 9 PEG_M_TXN4 AP22 PEX_RX4 NC_17 R7
AK6 DACC_VREF NC_18 U7
C1049 1 2 0.1U_0402_16V4Z PEG_C_RXP5 AL22 PEX_TX5 NC_19 V6
9 PEG_RXP5
AH7 DACC_RSET DACC_HSYNC AM1 C1050 1 2 0.1U_0402_16V4Z PEG_C_RXN5 AK22 PEX_TX5
9 PEG_RXN5
DACC_VSYNC AM2 1009 change HDMI I2C channel for Nvidia suggestion
9 PEG_M_TXP5 AR22 PEX_RX5
1105 nVIDIA suggetion, add R 9 PEG_M_TXN5 AR23 PEX_RX5
DACC_RED AK4
1108 nVIDIA suggestion -- change HDMI DDC to I2CD C1051 1 2 0.1U_0402_16V4Z PEG_C_RXP6 AL23
DAC C DACC_GREEN AL4
9 PEG_RXP6
9 PEG_RXN6
C1052 1 2 0.1U_0402_16V4Z PEG_C_RXN6 AM23
PEX_TX6
PEX_TX6 +3VS

DACC_BLUE AJ4 9 PEG_M_TXP6 AP23 PEX_RX6 VDD33_1 J10 0.1U_0402_16V7K

9 PEG_M_TXN6 AN23 PEX_RX6 VDD33_2 J11

C1053 PEG_C_RXP7 AM24

110 mA VDD33_3 J12 1 1
C1055
9 PEG_RXP7 1 2 0.1U_0402_16V4Z PEX_TX7 VDD33_4 J13 C1058 C1054
C1056 1 2 0.1U_0402_16V4Z PEG_C_RXN7 AM25 PEX_TX7 VDD33_5 J9
9 PEG_RXN7
NB9P-GS_BGA 969~D
AN25 2 2
9 PEG_M_TXP7 PEX_RX7
9 PEG_M_TXN7 AP25 PEX_RX7 1U_0603_10V4Z
0.1U_0402_16V4Z
C1059 1 2 0.1U_0402_16V4Z PEG_C_RXP8 AL25 PEX_TX8
9 PEG_RXP8
C1060 1 2 0.1U_0402_16V4Z PEG_C_RXN8 AK25 PEX_TX8
9 PEG_RXN8

9 PEG_M_TXP8 AR25 PEX_RX8

9 PEG_M_TXN8 AR26 PEX_RX8

C1061 1 2 0.1U_0402_16V4Z PEG_C_RXP9 AL26 PEX_TX9

9 PEG_RXP9
U71F C1062 1 2 0.1U_0402_16V4Z PEG_C_RXN9 AM26 PEX_TX9
9 PEG_RXN9
L63 BLM18PG181SN1D_0603 4/16 DACA VDD_SENSE AD20 VDD_SENSE 52
3 3
+3VS 1 2 DACA_VDD AJ12 DACA_VDD 150 mA I2CA_SCL G1 9 PEG_M_TXP9 AP26 PEX_RX9 GND_SENSE AD19
M_DDCCLK 16
I2CA_SDA G4 M_DDCDATA 16 9 PEG_M_TXN9 AN26 PEX_RX9
DACA_VREF AK12 DACA_VREF
C1063 1 2 0.1U_0402_16V4Z PEG_C_RXP10 AM27 PEX_TX10
9 PEG_RXP10
4.7U_0603_6.3V6K

4700P_0402_16V7K

470P_0402_50V7K

0.1U_0402_16V4Z

1 1 1 1 AK13 DACA_RSET DACA_HSYNC AM13 C1064 1 2 0.1U_0402_16V4Z PEG_C_RXN10 AM28 PEX_TX10

M_HSYNC 16 9 PEG_RXN10
C1172 C1065 C1066 C1067 DACA_VSYNC AL13 M_VSYNC 16
1
124_0402_1%

9 PEG_M_TXP10 AN28 PEX_RX10

R1042 9 PEG_M_TXN10 AP28 PEX_RX10
2 2 2 2 AM15 +PCIE
DACA_RED

DAC A
VGA_RED 16
C1068 1 2 0.1U_0402_16V4Z PEG_C_RXP11 AL28 PEX_TX11
9 PEG_RXP11
DACA_GREEN AM14 C1069 1 2 0.1U_0402_16V4Z PEG_C_RXN11 AK28 PEX_TX11 L64
VGA_GRN 16 9 PEG_RXN11
2

PEX_PLLVDD AG14 1U_0603_10V4Z 1 2

DACA_BLUE AL14 VGA_BLU 16 9 PEG_M_TXP11 AR28 PEX_RX11
9 PEG_M_TXN11 AR29 PEX_RX11 100mA 10NH_LQG15HS10NJ02D_5%_0402

C1070 1 2 0.1U_0402_16V4Z PEG_C_RXP12 AK29 PEX_TX12 1 1 1 1

9 PEG_RXP12
1

C1260 C1057
150_0402_1%

150_0402_1%

150_0402_1%

C1072 1 2 0.1U_0402_16V4Z PEG_C_RXN12 AL29 PEX_TX12 C1073 C1071

9 PEG_RXN12
NB9P-GS_BGA 969~D R1590 R1591 R1592
9 PEG_M_TXP12 AP29 PEX_RX12 4.7U_0603_6.3V6M
AN29 2 2 2 2
9 PEG_M_TXN12 PEX_RX12
2

C1074 1 2 0.1U_0402_16V4Z PEG_C_RXP13 AM29 PEX_TX13 0.01U_0402_16V7K 0.1U_0402_16V4Z

9 PEG_RXP13
C1075 1 2 0.1U_0402_16V4Z PEG_C_RXN13 AM30 PEX_TX13
9 PEG_RXN13

9 PEG_M_TXP13 AN31 PEX_RX13

9 PEG_M_TXN13 AP31 PEX_RX13

C1076 1 2 0.1U_0402_16V4Z PEG_C_RXP14 AM31 PEX_TX14 PEX_RFU1 AG19

9 PEG_RXP14
C1077 1 2 0.1U_0402_16V4Z PEG_C_RXN14 AM32 PEX_TX14
9 PEG_RXN14

9 PEG_M_TXP14 AR31 PEX_RX14 PEX_RFU2 AG20

9 PEG_M_TXN14 AR32 PEX_RX14
U71H PEX_TERMP AG21 R1043 1 2 2.49K_0402_1%
5/16 DACB(TV) C1078 1 2 0.1U_0402_16V4Z PEG_C_RXP15 AN32 PEX_TX15
9 PEG_RXP15
R948 1 2 AC6 DACB_VDD C1079 1 2 0.1U_0402_16V4Z PEG_C_RXN15 AP32 PEX_TX15
9 PEG_RXN15
10K_0402_5% 1009 disable TV function
AC5 DACB_VREF 9 PEG_M_TXP15 AR34 PEX_RX15
AP34 AP35 R949 1 2 10K_0402_5%
AB6 DACB_RSET
DAC B 9 PEG_M_TXN15 PEX_RX15 TESTMODE

4 DACB_CSYNC AB5 4
1009 disable TV function NB9P-GS_BGA 969~D

DACB_RED AA4

DACB_GREEN AB4

DACB_BLUE Y4

NB9P-GS_BGA 969~D Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PEG & LVDS & DAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, December 26, 2007 Sheet 18 of 58
A B C D E
 5 4 3 2 1

U71P
15/16 GND
AA11 GND GND E15
AA12 GND GND E18
AA13 GND GND E24
AA14 GND GND E27
AA15 GND GND E30
AA16 GND GND E6
AA17 GND GND E9
AA18 GND GND F2
AA19 GND GND F31 +3VS
AA2 GND GND F34
AA20 GND GND F5

1
AA21 GND GND J2
AA22 GND GND J31 R950
AA23 GND GND J34 U71K
AA24 GND GND J5 U71D 10K_0402_5% 9/16 IFPEF
AA25 GND GND L9 13/16 MISC2 IFPE

2
D D
AA34 GND GND M11 @ C823 1 2 @ R611 1 2 J26 RFU ROM_CS C3 ROM_CS#
AA5 GND GND M13 J25 RFU
AB12 GND GND M15 15P_0402_50V8J 33_0402_5% ROM_SI D3 ROM_SI
ROM_SI 20
AB14 GND GND M17 ROM_SO C4 ROM_SO
ROM_SO 20
AB16 GND GND M19 ROM_SCLK D4 ROM_SCLK AUX AD4
ROM_SCLK 20
AB18 GND GND M2 AUX AE4
AB20 GND GND M21
AB22 GND GND M23 R387 1 2 0_0402_5% HDA_BITCLK_VGA D7 HDA_BCLK
27 HDA_VGA_BITCLK
AB24 GND GND M25 R388 1 2 0_0402_5% HDA_RST#_VGA D6 HDA_RST 1112 C1083,D48 no stuff DPL3_TXC AE5
27 HDA_VGA_RST#
AC9 GND GND M31 R415 1 2 10_0402_5%HDA_SDIN_VGA C7 HDA_SDI AJ6 IFPEF_PLLVDD DPL3_TXC AE6
27 HDA_SDIN2
AD11 GND GND M34 R422 1 2 0_0402_5% HDA_SDOUT_VGA B7 HDA_SDO 10K_0402_5%
27 HDA_VGA_SDOUT

1
AD13 GND GND M5 R427 1 2 0_0402_5% HDA_SYNC_VGA A7 HDA_SYNC R951 1 2 +3VS AL1 IFPEF_RSET DPL2_TXD0 AF5
27 HDA_VGA_SYNC +3VS
AD15 GND GND N11 DPL2_TXD0 AF4
AD17 GND GND N12 R952

1
AD2 GND GND N13 1109 nVIDIA suggestion -- R387,R388,R415,R422,R427 -- install I2CH_SCL F6 HDCP_SCL @ 10K_0402_5% DPL1_TXD1 AG4
AD21 GND GND N14 R978 DPL1_TXD1 AH4
Change R415 to 10 ohm

2
AD23 GND GND N15 I2CH_SDA G6 HDCP_SDA 24.3K_0402_1%
AD25 GND GND N16 DPL0_TXD2 AH5
AD31 GND GND N17 R953 1 2 +3VS DPL0_TXD2 AH6

2
AD34 GND GND N18 10K_0402_5%
AD5 GND GND N19 SPDIF A5 @ C1083 1 2 SPDIF_OUT 34
AE11 GND GND N20 0.01U_0402_25V7K
AE12 GND GND N21 BUFRST A4
AE13 GND GND N22 PGOOD_OUT C5

1
AE14 GND GND N23 R954 40.2K_0402_1% @ D48 IFPF
AE15 GND GND N24 1 2 N9 STRAP_REF_3V3 @R979
AE16 GND GND N25 RFU_GND AK14 BAV99-7-F_SOT23-3 3.4K_0402_1% AE7 IFPE_IOVDD
AE17 GND GND P12 1 2 M9 STRAP_REF_MIOB RFU_GND K9

1
AE18 GND GND P14 R955 40.2K_0402_1%

2
AE19 GND GND P16 NB9P-GS_BGA 969~D AD7 IFPF_IOVDD

3
AE20 GND GND P18 R956 AUX AF2

1
AE21 GND GND P20 10K_0402_5% AUX AF3
AE22 GND GND P22

2
AE23 GND GND P24 +3VS +3VS
AE24 GND GND R2 +3VS DPL3_TXC AH3
AE25 GND GND R31 DPL3_TXC AH2

2
1
AG2 GND GND R34
AG31 GND GND R5 1 R957 HDCP_SCL 1212 HDCP ROM -- R951 pull up,R959 no install R958 DPL2_TXD0 AH1
2.2K_0402_5% 10K_0402_5%
AG34 GND GND T11 HDCP DPL2_TXD0 AJ1

1
C AG5 GND GND T13 C1084 @ C
AK2 GND GND T15 ROM 0.1U_0402_16V4Z R959 DPL1_TXD1 AJ2

2
AK31 T17 2 HDCP_WP 10K_0402_5% AJ3
GND GND DPL1_TXD1
AK34 GND GND T19 U61
AK5 GND GND T21 1 8 DPL0_TXD2 AL3

2
A0 VCC HDCP_WP
AL12 GND GND T23 2 A1 WP 7 DPL0_TXD2 AL2
AL15 GND GND T25 3 6 HDCP_SCL
A2 SCL HDCP_SDA NB9P-GS_BGA 969~D
AL18 GND GND U11 4 GND SDA 5
AL21 GND GND U12
AL24 GND GND U13 AT24C02N-10SU-2.7_SO8
AL27 GND GND U14
AL30 GND GND U15
AL6 GND GND U16
AL9 GND GND U17
AN2 GND GND U18
AN34 GND GND U19
AP12 GND GND U20
AP15 GND GND U21
AP18 GND GND U22
AP21 GND GND U23
AP24 GND GND U24
AP27 GND GND U25 +IFPC_PLLVDD is 3.3V for NB9P-GE, but it is 1.1V for NB9P-GS/GE2 and NB9M-GS-B
AP3 GND GND V12 U71J
AP30 GND GND V14 8/16 IFPCD
AP33 GND GND V16 IFPC
AP6 GND GND V18
AP9 GND GND V2 1106 Delete R98,R1006,Q8,Q73
B12 GND GND V20
B15 GND GND V22
B21 GND GND V24 +1.8VS AUX AN3
B24 GND GND V31 AUX AP2 NB9M-GE & NB9P-GS --> 0.1uF
B27 GND GND V5
B3 GND GND V9
B30 GND GND Y11 L67 DPL3_TXC AR2 HDMI_C_CLK- C1335 1 2 0.1U_0402_16V4Z HDMI_CLK- 44
B33 GND GND Y13 1 2 1U_0402_6.3V4Z 4700P_0402_25V7K IFPCD_PLLVDD AJ9 IFPCD_PLLVDD DPL3_TXC AP1 HDMI_C_CLK+ C1336 1 2 0.1U_0402_16V4Z HDMI_CLK+ 44
B6 GND GND Y15 32 mA
B9 GND GND Y17 BLM18PG181SN1D_0603 IFPC_RSET AK7 IFPCD_RSET DPL2_TXD0 AM4 HDMI_C_TX0- C1337 1 2 0.1U_0402_16V4Z HDMI_TX0- 44
C2 GND GND Y19 DPL2_TXD0 AM3 HDMI_C_TX0+ C1338 1 2 0.1U_0402_16V4Z HDMI_TX0+ 44

1
C34 GND GND Y21 1 1 1 1 1
E12 GND GND Y23 C1091 C1092 C1093 C1094 C1095 DPL1_TXD1 AM5 HDMI_C_TX1- C1339 1 2 0.1U_0402_16V4Z HDMI_TX1- 44
B B
GND Y25 R971 DPL1_TXD1 AL5 HDMI_C_TX1+ C1340 1 2 0.1U_0402_16V4Z HDMI_TX1+ 44
4.7U_0603_6.3V6K 1K_0402_1%
NB9P-GS_BGA 969~D 2 2 2 2 2 AM6 HDMI_C_TX2- C1341 1 2 0.1U_0402_16V4Z
DPL0_TXD2 HDMI_TX2- 44

2
DPL0_TXD2 AM7 HDMI_C_TX2+ C1342 1 2 0.1U_0402_16V4Z HDMI_TX2+ 44
1109 Delete R99, Change +IFPC_PLLVDD to +PCIE 1U_0402_6.3V4Z 4700P_0402_16V7K

+PCIE 470P
IFPD
L87
1 2 1U_0402_6.3V4Z 4700P_0402_25V7K IFPC_PLLVDD AJ8 IFPC_IOVDD

BLM18PG181SN1D_0603 NB9M-GE & NB9P-GS-->Pull down 500 ohm resistor and 2N7002
AK8 IFPD_IOVDD
1 1 1 1 1 AUX AN4 HDMI_CLK- R967 1 2 499_0402_1%

1
C1258 C1259 C1257 C1256 C1255 AUX AP4 HDMI_CLK+ R966 1 2 499_0402_1%
R973
U71E 4.7U_0603_6.3V6K 10K_0402_5% HDMI_TX0- R965 1 2 499_0402_1%
14/16 XTAL_PLL 2 2 2 2 2 AR4 HDMI_TX0+ R964 1 2 499_0402_1%
DPL3_TXC
DPL3_TXC AR5

2
+PCIE L66 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z GPU_PLLVDD AE9 PLLVDD 1U_0402_6.3V4Z 4700P_0402_16V7K HDMI_TX1- R963 1 2 499_0402_1%
AD9 VID_PLLVDD 36 mA DPL2_TXD0 AP5 HDMI_TX1+ R962 1 2 499_0402_1%
BLM18PG181SN1D_0603 1 1 1 1 1 AF9 SP_PLLVDD DPL2_TXD0 AN5
C1261 C1085 C1086 C1087 C1088 HDMI_TX2- R961 1 2 499_0402_1%
470P DPL1_TXD1 AN7 HDMI_TX2+ R960 1 2 499_0402_1%
0.1U_0402_16V4Z DPL1_TXD1 AP7
2 2 2 2 2
DPL0_TXD2 AR7
1U_0402_6.3V4Z 1U_0402_6.3V4Z DPL0_TXD2 AR8
15 27M_SSC D2 XTALSSIN XTALOUTBUFF D1

1
NB9P-GS_BGA 969~D D
1

Q74 2 +3VS
@ R968 XTALIN B1 XTALIN XTALOUT B2 XTALOUT R969 2N7002_SOT23-3 G
10K_0402_5% 10K_0402_5% S

3
NB9P-GS_BGA 969~D NB9P-GS_BGA_969P
2

1 @
C1090
A 1 @ A
18P_0402_50V8J C1089
2
18P_0402_50V8J
2

R970 1 2 XTALIN
15 27M_CLK
0_0402_5%
1

@
R972
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Straps & HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, December 26, 2007 Sheet 19 of 58
5 4 3 2 1
 A

1102 R2046,R2047 no stuff

+3VS
GPIO I/O ACTIVE USAGE

VGA Core power GPIO0 IN N/A Primary DVI Hot-plug

1
1
@ @
1107 Swap THERMDN and THERMDP R2046 R2047
GPIO1 IN N/A 2nd DVI Hot-plug 2.2K_0402_5% 2.2K_0402_5%

U71N

2
2
GPIO2 OUT H Panel Back-Light PWM VGA_THERMDC
12/16 MISC1
I2CA_SDA R976 2
B4 THERMDN I2CS_SCL E2 1 0_0402_5% SMB_EC_CK2 4,40 Thermal
I2CS_SDA E1 I2CA_SCL R977 1 2 0_0402_5% SMB_EC_DA2 4,40
+NVVDD U71O +NVVDD +NVVDD GPIO3 OUT H Panel Power Enable DDC2_CLK
16/16 NVVDD Close to VGA
I2CC_SCL
I2CC_SDA
E3
E4 DDC2_DATA
DDC2_CLK 17 LVDS
DDC2_DATA 17
AB11 VDD VDD P21 GPIO4 OUT H Panel Back-Light Enable I2CD_SCL F4 HDMICLK_VGA 44
AB13
AB15
VDD
VDD
VDD
VDD
P23
P25 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K VGA_THERMDA B5 THERMDP
I2CD_SDA
I2CE_SCL
G5
D5 R2066 2.2K_0402_5%
HDMIDAT_VGA 44 HDMI
AB17 VDD VDD R11 GPIO5 OUT N/A NVVDD VID0 I2CE_SDA E5 2 1 +3VS
AB19 VDD VDD R12
AB21 VDD VDD R13 C1098 C1099 C1100 C1101 C1102 C1103 2 1 1109 nVIDIA suggestion -- change HDMI DDC to I2CD
AB23 VDD VDD R14 GPIO6 OUT N/A NVVDD VID1 GPIO0 K1 R2065 2.2K_0402_5%
AB25 VDD VDD R15 GPIO1 K2 HDMI_DETECT
HDMI_DETECT 44
AC11 VDD VDD R16 GPIO2 K3
AC12 VDD VDD R17 GPIO7 OUT N/A FBVDD VID0 GPIO3 H3 E NVDD ENAVDD 17
AC13 VDD VDD R18 0.1U_0402_16V7K 0.1U_0402_16V7K 10U_0603_6.3V6M GPIO4 H2 ENABLT
ENABLT 40
AC14 VDD VDD R19 GPIO5 H1 GPU_VID0 GPU_VID0 52
AC15 VDD VDD R20 GPIO8 IN L Thermal Alert GPIO6 H4 GPU_VID1
GPU_VID1 52
AC16 VDD VDD R21 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K GPIO7 H5 R994 0_0402_5%
AC17 VDD VDD R22 GPIO8 H6 THERM#_VGA_R 1 2 THERM_SCI#
THERM_SCI# 28,40
AC18 VDD VDD R23 GPIO9 OUT L FAN PWM JTAG_TCK AP14 JTAG_TCK GPIO9 J7 SNN_GPIO9 1 2 VGA_THERM_SCI#
T79
AC19 VDD VDD R24 C1104 C1105 C1106 C1107 C1108 C1109 JTAG_TMS AR14 JTAG_TMS GPIO10 K4 R995 0_0402_5%
T80
AC20 VDD VDD R25 JTAG_TDI AN14 JTAG_TDI GPIO11 K5
T81
AC21 VDD VDD T12 GPIO10 OUT N/A FBVref Select JTAG_TDO AN16 JTAG_TDO GPIO12 H7
T82
AC22 VDD VDD T14 JTAG_TRST AP16 JTAG_TRST GPIO13 J4
T83
AC23 VDD VDD T16 GPIO14 J6
AC24 VDD VDD T18 0.1U_0402_16V7K 0.1U_0402_16V7K 10U_0603_6.3V6M GPIO11 OUT N/A SLI SYNCO GPIO15 L1 ENABLT
AC25 VDD VDD T20 GPIO16 L2
AD12 VDD VDD T22 GPIO17 L4

2
AD14 VDD VDD T24 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K GPIO12 IN N/A AC Detect GPIO18 M4
AD16 VDD VDD V11 GPIO19 L7 R1016
AD18 VDD VDD V13 GPIO20 L5
AD22 VDD VDD V15 C1110 C1111 C1112 C1113 C1114 C1115 GPIO13 OUT L PS Control or HDMI_CEC GPIO21 K6 10K_0402_5%
AD24 VDD VDD V17 SWAP_RDY_A/GPIO22 L6

1
L11 VDD VDD V19 STEREO/GPIO23 M6
L12 VDD VDD V21 GPIO14 OUT H PS Control
L13 VDD VDD V23
L14 VDD VDD V25 4700P_0402_25V7K 4700P_0402_25V7K 10U_0603_6.3V6M NB9P-GS_BGA 969~D
L15 VDD VDD W11
L16 VDD VDD W12
L17 VDD VDD W13 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
L18 VDD VDD W14
L19 VDD VDD W15
L20 VDD VDD W16 C1117 C1118 C1119 C1120 C1116 U71L U71M
L21 VDD VDD W17 11/16 MIOB 10/16 MIOA
L22 VDD VDD W18 +3VS AA9 MIOB_VDDQ MIOBD0 Y1 MIOBD0 +3VS P9 MIOA_VDDQ MIOAD0 N1 MIOAD0
T87 T98
L23 VDD VDD W19 AB9 MIOB_VDDQ MIOBD1 Y2 MIOBD1 R9 MIOA_VDDQ MIOAD1 P4 MIOAD1
T85 T96
L24 VDD VDD W20 W9 MIOB_VDDQ MIOBD2 Y3 MIOBD2 T9 MIOA_VDDQ MIOAD2 P1 MIOAD2
T86 T94
L25 VDD VDD W21 4700P_0402_25V7K 4700P_0402_25V7K Y9 MIOB_VDDQ MIOBD3 AB3 MIOBD3 U9 MIOA_VDDQ MIOAD3 P2 MIOAD3
T84 T95
M12 VDD VDD W22 MIOBD4 AB2 MIOBD4 MIOAD4 P3 MIOAD4
T88 T97
M14 VDD VDD W23 MIOBD5 AB1 MIOBD5 MIOAD5 T3 MIOAD5
T93 T103
M16 VDD VDD W24 MIOBD6 AC4 MIOBD6 MIOAD6 T2 MIOAD6
T91 T101
M18 VDD VDD W25 MIOBD7 AC1 MIOBD7 MIOAD7 T1 MIOAD7
T89 T99
M20 VDD VDD Y12 MIOBD8 AC2 MIOBD8 MIOAD8 U4 MIOAD8
T90 T100
M22 VDD VDD Y14 MIOBD9 AC3 MIOBD9 MIOAD9 U1 MIOAD9
T92 T102
M24 VDD VDD Y16 MIOBD10 AE3 MIOBD11 MIOAD10 U2
T108
P11 VDD VDD Y18 AA7 MIOBCAL_PD_VDDQ MIOBD11 AE2 U5 MIOACAL_PD_VDDQ MIOAD11 U3
P13 VDD VDD Y20 MIOBD12 U6 MIOAD12 R6
P15 VDD VDD Y22 AA6 MIOBCAL_PU_GND MIOBD13 W6 T5 MIOACAL_PU_GND MIOAD13 T6
P17 VDD VDD Y24 MIOBD14 Y6 MIOAD14 N6
P19 VDD MIOBD15 W5 STRAP0
MIOBD16 W7 STRAP1
NB9P-GS_BGA 969~D AF1 MIOB_VREF MIOBD17 V7 STRAP2 N5 MIOA_VREF

1 1

MIOB_CTL3 W3 MIOB_CTL3 MIOA_CTL3 P5

T109
W1 MIO B_HSYNC N3 MIO A_HSYNC
MULTI LEVEL STRAPS For NB9M-Gx (64bit) MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
W2
Y5 MIOB_DE
T110

T105
MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
L3
N2 MIOA_DE
T111

T104

NB9P-GS and NB9P-GE2 is as same as NB9M-GE-B

MIOB_CLKOUT V4 MIOA_CLKOUT R4
MIOB_CLKOUT W4 MIOA_CLKOUT T4
MIOB_CLKIN AE1 MIOA_CLKIN N4
STRAP0

1
STRAP1 NB9P-GS NB9M-GE/NB9P-GE2
STRAP2 NB9P-GS_BGA 969~D R1029 NB9P-GS_BGA 969~D R983
ROM_SI STRAP0 pull up 45K pull up 45K
19 ROM_SI
ROM_SO 10K_0402_5% 10K_0402_5%
19 ROM_SO
ROM_SCLK STRAP1 pull down 10K pull down 10K
19 ROM_SCLK

2
+3VS
STRAP2 pull up 10K pull up 5K
@
R981 1 2 5.1K_0402_5% R982 1 2 45.3K_0402_5% ROM_SO pull up 5K pull up 5K
STRAP2 -- R987
@ ROM_CLK pull down 15K pull down 15K
R984 1 2 10K_0402_5% R985 1 2 5.1K_0402_5%

@
R986 1 2 5.1K_0402_5% R987 1 2 5.1K_0402_5% ROM_SI
@ Samsung 16Mx16 pull down 10K
R988 1 2 45.3K_0402_1% R989 1 2 5.1K_0402_5%
Hynix 16Mx16 pull down 20K
@
R990 1 2 5.1K_0402_5% R991 1 2 5.1K_0402_5% Samsung 32Mx16 pull down 30K

R992 1 2 15K_0402_5%
@
R993 1 2 5.1K_0402_5%
Hynix 32Mx16 pull down 45K R988
Qimonda 32Mx16 pull down 35K

VGA Thermal Sensor ADM1032ARMZ

+3VS
Closed to VGA +3VS

@ 2
2

C1096 @
R974
0.1U_0402_16V4Z 10K_0402_5%
1 @
U62 @
1

1 8 VGA_SM_CLK R1032 2 1 0_0402_5% SMB_EC_CK2

VDD SCLK @
VGA_THERMDA 2 7 VGA_SM_DA R980 1 2 0_0402_5% SMB_EC_DA2
@ C1097 D+ SDATA
1 2 VGA_THERMDC 3 6 VGA_THERM_SCI#
D- ALERT#
2200P_0402_50V7K THERM#_VGA 4 5
THERM# GND
@ R975
+3VS 1 2 ADM1032ARMZ REEL_MSOP8
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPIO & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, December 26, 2007 Sheet 20 of 58
A
 A

VRAM Interface
DATA Bus +1.8VS
Address 0..31 32..63
CMD0 A3
U71C
CMD1 A0 A0 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
24,25 MDB[63..0]
3/16 FBC
CMD2 A2 MDB0 D11 FBC_D0 FBVDDQ N27 1 1 1 1 1 1
MDB1 E11 FBC_D1 FBVDDQ P27 C1130 C1122 C1123 C1131 C1124 C1125
CMD3 A1 A1 MDB2 F10 FBC_D2 FBVDDQ R27
U71B +1.8VS MDB3 D8 FBC_D3 FBVDDQ T27
22,23 MDA[63..0] 2 2 2 2 2 2
2/16 FBA CMD4 A3 MDB4 F8 FBC_D4 FBVDDQ U27
MDA0 R30 FBA_D0 FBVDDQ J23 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K MDB5 F9 FBC_D5 FBVDDQ U29
MDA1 R32 FBA_D1 FBVDDQ J24 CMD5 A4 MDB6 E8 FBC_D6 FBVDDQ V27 0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0603_6.3V6K
MDA2 P31 FBA_D2 FBVDDQ J29 1 1 1 1 1 1 MDB7 F12 FBC_D7 FBVDDQ V29
MDA3 N30 FBA_D3 FBVDDQ AA27 C1132 C1133 C1126 C1134 C1135 C1136 CMD6 A5 MDB8 B11 FBC_D8 FBVDDQ V34
MDA4 L31 FBA_D4 FBVDDQ AA29 MDB9 C13 FBC_D9 FBVDDQ W27
MDA5 M32 FBA_D5 FBVDDQ AA31 CMD7 MDB10 A11 FBC_D10 FBVDDQ Y27 4700P_0402_25V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z
MDA6 M30 AB27 2 2 2 2 2 2 MDB11 B8
FBA_D6 FBVDDQ FBC_D11
MDA7 L30 FBA_D7 FBVDDQ AB29 CMD8 CS# CS# MDB12 A8 FBC_D12 1 1 1 1 1 1
MDA8 P33 FBA_D8 FBVDDQ AC27 0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0603_6.3V6K MDB13 C8 FBC_D13 C1137 C1138 C1139 C1127 C1140 C1141
MDA9 P34 FBA_D9 FBVDDQ AD27 CMD9 WE# WE# MDB14 C11 FBC_D14
MDA10 N35 FBA_D10 FBVDDQ AE27 MDB15 C10 FBC_D15
MDA11 MDB16 2 2 2 2 2 2
P35 FBA_D11 FBVDDQ AJ28 CMD10 BA0 BA0 D12 FBC_D16
MDA12 N34 FBA_D12 FBVDDQ B18 MDB17 E13 FBC_D17
MDA13 L33 FBA_D13 FBVDDQ E21 4700P_0402_25V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z CMD11 CKE CKE MDB18 F17 FBC_D18 4700P_0402_25V7K 4700P_0402_25V7K 0.1U_0402_16V4Z
MDA14 L32 FBA_D14 FBVDDQ G17 MDB19 F15 FBC_D19
MDA15 N33 FBA_D15 FBVDDQ G18 1 1 1 1 1 1 CMD12 ODT ODT MDB20 F16 FBC_D20
MDA16 K31 FBA_D16 FBVDDQ G22 C1142 C1143 C1144 C1145 C1146 C1147 MDB21 E16 FBC_D21
MDA17 K30 FBA_D17 FBVDDQ G8 CMD13 A2 MDB22 F14 FBC_D22
MDA18 G30 FBA_D18 FBVDDQ G9 MDB23 F13 FBC_D23
MDA19 2 2 2 2 2 2 MDB24
K32 FBA_D19 FBVDDQ H29 CMD14 A12 A12 D13 FBC_D24
MDA20 G32 FBA_D20 FBVDDQ J14 MDB25 A13 FBC_D25
MDA21 H30 FBA_D21 FBVDDQ J15 4700P_0402_25V7K 4700P_0402_25V7K 0.1U_0402_16V4Z CMD15 RAS# RAS# MDB26 B13 FBC_D26
MDA22 F30 FBA_D22 FBVDDQ J16 MDB27 A14 FBC_D27
MDA23 G31 FBA_D23 FBVDDQ J17 CMD16 A11 A11 MDB28 C16 FBC_D28
MDA24 H33 FBA_D24 FBVDDQ J20 MDB29 A17 FBC_D29
MDA25 K35 FBA_D25 FBVDDQ J21 CMD17 A10 A10 MDB30 B16 FBC_D30
MDA26 K33 FBA_D26 FBVDDQ J22 4700P_0402_25V7K 1U_0402_6.3V4Z 0.022U_0402_16V7K MDB31 D16 FBC_D31
MDA27 G34 FBA_D27 CMD18 BA1 BA1 MDB32 D24 FBC_D32
MDA28 K34 FBA_D28 1 1 1 1 1 1 MDB33 D26 FBC_D33
MDA29 E33 FBA_D29 C1148 C1128 C1149 C1150 C1151 C1129 CMD19 A8 A8 MDB34 E25 FBC_D34
MDA30 E34 FBA_D30 MDB35 F25 FBC_D35
MDA31 G33 FBA_D31 CMD20 A9 A9 MDB36 F27 FBC_D36
MDA32 AG30 2 2 2 2 2 2 MDB37 E28
FBA_D32 FBC_D37
MDA33 AH31 FBA_D33 CMD21 A6 A6 MDB38 F28 FBC_D38
MDA34 AG32 4700P_0402_25V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z MDB39 D29
MDA35 AF31
FBA_D34
FBA_D35 CMD22 A5 MDB40 A25
FBC_D39
FBC_D40
CKE CMDB11 R1025 1 2 10K_0402_5%
MDA36 AF30 MDB41 B25
MDA37 AD30
FBA_D36
FBA_D37 CMD23 A7 A7 MDB42 D25
FBC_D41
FBC_D42
ODT CMDB12 R1026 1 2 10K_0402_5%
MDA38 AC32 FBA_D38 MDB43 C26 FBC_D43
MDA39 AE30 FBA_D39 CMD24 A4 MDB44 C28 FBC_D44
MDA40 AE32 FBA_D40 MDB45 B28 FBC_D45
MDA41 AF33 FBA_D41 CMD25 CAS# CAS# MDB46 A28 FBC_D46
MDA42 AF34 FBA_D42 MDB47 A29 FBC_D47
MDA43 AE35 FBA_D43 CMD26 A13 A13 MDB48 E29 FBC_D48
MDA44 AE33 FBA_D44 MDB49 F29 FBC_D49
MDA45 AE34 FBA_D45 CMD27 BA2 BA2 MDB50 D30 FBC_D50
MDA46 AC35 FBA_D46 MDB51 E31 FBC_D51
MDA47 AB32 FBA_D47 CMD28 MDB52 C33 FBC_D52 FBC_CMD0 C17 CMDB0
CMDB0 24
MDA48 AN33 FBA_D48 MDB53 D33 FBC_D53 FBC_CMD1 B19 CMDB1
CMDB1 24,25
MDA49 AK32 FBA_D49 CMD29 MDB54 F32 FBC_D54 FBC_CMD2 D18 CMDB2
CMDB2 24
MDA50 AL33 FBA_D50 MDB55 E32 FBC_D55 FBC_CMD3 F21 CMDB3
CMDB3 24,25
MDA51 AM33 FBA_D51 CMD30 MDB56 B29 FBC_D56 FBC_CMD4 A23 CMDB4
CMDB4 25
MDA52 AL31 FBA_D52 FBA_CMD0 V32 CMDA0 MDB57 C29 FBC_D57 FBC_CMD5 D21 CMDB5
CMDA0 22 CMDB5 25
MDA53 AK30 FBA_D53 FBA_CMD1 W31 CMDA1 MDB58 B31 FBC_D58 FBC_CMD6 B23 CMDB6
CMDA1 22,23 CMDB6 25
MDA54 AJ30 FBA_D54 FBA_CMD2 U31 CMDA2 MDB59 C31 FBC_D59 FBC_CMD7 E20
CMDA2 22
MDA55 AH30 FBA_D55 FBA_CMD3 Y32 CMDA3 MDB60 B32 FBC_D60 FBC_CMD8 G21 CMDB8
CMDA3 22,23 CMDB8 24,25
1 MDA56 AM35 FBA_D56 FBA_CMD4 AB35 CMDA4 MDB61 C32 FBC_D61 FBC_CMD9 F20 CMDB9 1
CMDA4 23 CMDB9 24,25
MDA57 AH33 FBA_D57 FBA_CMD5 AB34 CMDA5 MDB62 B34 FBC_D62 FBC_CMD10 F19 CMDB10
CMDA5 23 CMDB10 24,25
MDA58 AH35 FBA_D58 FBA_CMD6 W35 CMDA6 MDB63 B35 FBC_D63 FBC_CMD11 F23 CMDB11
CMDA6 23 CMDB11 24,25
MDA59 AH32 FBA_D59 FBA_CMD7 W33 FBC_CMD12 A22 CMDB12
CMDB12 24,25
MDA60 AH34 FBA_D60 FBA_CMD8 W30 CMDA8 FBC_CMD13 C22 CMDB13
CMDA8 22,23 24,25 DQMB[7..0] CMDB13 25
MDA61 AM34 FBA_D61 FBA_CMD9 T34 CMDA9 DQMB0 F11 FBC_DQM0 FBC_CMD14 B17 CMDB14
CMDA9 22,23 CMDB14 24,25
MDA62 AL35 FBA_D62 FBA_CMD10 T35 CMDA10 DQMB1 D10 FBC_DQM1 FBC_CMD15 F24 CMDB15
CMDA10 22,23 CMDB15 24,25
MDA63 AJ33 FBA_D63 FBA_CMD11 AB31 CMDA11 DQMB2 D15 FBC_DQM2 FBC_CMD16 C25 CMDB16
CMDA11 22,23 CMDB16 24,25
FBA_CMD12 Y30 CMDA12 DQMB3 A16 FBC_DQM3 FBC_CMD17 E22 CMDB17
CMDA12 22,23 CMDB17 24,25
Y34 CMDA13 DQMB4 D27 C20 CMDB18
22,23 DQMA[7..0]
DQMA0 P30 FBA_DQM0
FBA_CMD13
FBA_CMD14 W32 CMDA14
CMDA13 23 ODT CMDA12 R1027 1 2 10K_0402_5% DQMB5 D28
FBC_DQM4
FBC_DQM5
FBC_CMD18
FBC_CMD19 B22 CMDB19
CMDB18 24,25
CMDA14 22,23 CMDB19 24,25
DQMA1 P32 AA30 CMDA15 DQMB6 D34 A19 CMDB20
DQMA2 J30
FBA_DQM1
FBA_DQM2
FBA_CMD15
FBA_CMD16 AA32 CMDA16
CMDA15 22,23 CKE CMDA11 R1028 1 2 10K_0402_5% DQMB7 A34
FBC_DQM6
FBC_DQM7
FBC_CMD20
FBC_CMD21 D22 CMDB21
CMDB20 24,25
CMDA16 22,23 CMDB21 24,25
DQMA3 H34 FBA_DQM3 FBA_CMD17 Y33 CMDA17 FBC_CMD22 D20 CMDB22
CMDA17 22,23 CMDB22 24
DQMA4 AF32 FBA_DQM4 FBA_CMD18 U32 CMDA18 FBC_CMD23 E19 CMDB23
CMDA18 22,23 24 QSB[3..0] CMDB23 24,25
DQMA5 AF35 FBA_DQM5 FBA_CMD19 Y31 CMDA19 QSB0 E10 FBC_DQS_WP0 FBC_CMD24 D19 CMDB24
CMDA19 22,23 CMDB24 24
DQMA6 AL32 FBA_DQM6 FBA_CMD20 U34 CMDA20 QSB1 A10 FBC_DQS_WP1 FBC_CMD25 F18 CMDB25
CMDA20 22,23 CMDB25 24,25
DQMA7 AL34 FBA_DQM7 FBA_CMD21 Y35 CMDA21 QSB2 D14 FBC_DQS_WP2 FBC_CMD26 C19
CMDA21 22,23
FBA_CMD22 W34 CMDA22 QSB3 C14 FBC_DQS_WP3 FBC_CMD27 F22
CMDA22 22 25 QSB[7..4]
FBA_CMD23 V30 CMDA23 QSB4 E26 FBC_DQS_WP4 FBC_CMD28 C23
22 QSA[3..0] CMDA23 22,23
QSA0 N31 FBA_DQS_WP0 FBA_CMD24 U35 CMDA24 QSB5 B26 FBC_DQS_WP5 FBC_CMD29 B20
CMDA24 22
QSA1 L34 FBA_DQS_WP1 FBA_CMD25 U30 CMDA25 QSB6 D32 FBC_DQS_WP6 FBC_CMD30 A20
CMDA25 22,23
QSA2 J32 FBA_DQS_WP2 FBA_CMD26 U33 QSB7 A32 FBC_DQS_WP7
QSA3 H35 FBA_DQS_WP3 FBA_CMD27 AB30
23 QSA[7..4]
QSA4 AE31 FBA_DQS_WP4 FBA_CMD28 AB33 24 QSB#[3..0]
QSA5 AC33 FBA_DQS_WP5 FBA_CMD29 T33 QSB#0 D9 FBC_DQS_RN0
QSA6 AJ32 FBA_DQS_WP6 FBA_CMD30 W29 QSB#1 B10 FBC_DQS_RN1
QSA7 AJ34 FBA_DQS_WP7 QSB#2 E14 FBC_DQS_RN2 FBC_CLK0 E17 CLKB0 CLKB0 24
QSB#3 B14 FBC_DQS_RN3 FBC_CLK0 D17 CLKB0# CLKB0# 24
25 QSB#[7..4]
FBA_CLK0 T32 CLKA0 CLKA0 22 QSB#4 F26 FBC_DQS_RN4 FBC_CLK1 D23 CLKB1 CLKB1 25
22 QSA#[3..0]
QSA#0 N32 FBA_DQS_RN0 FBA_CLK0 T31 CLKA0# CLKA0# 22 QSB#5 A26 FBC_DQS_RN5 FBC_CLK1 E23 CLKB1# CLKB1# 25
QSA#1 L35 FBA_DQS_RN1 FBA_CLK1 AC31 CLKA1 CLKA1 23 QSB#6 D31 FBC_DQS_RN6
QSA#2 H31 FBA_DQS_RN2 FBA_CLK1 AC30 CLKA1# CLKA1# 23 QSB#7 A31 FBC_DQS_RN7
QSA#3 G35 FBA_DQS_RN3
23 QSA#[7..4] +1.8VS
QSA#4 AD32 FBA_DQS_RN4
QSA#5 AC34 FBA_DQS_RN5
QSA#6 AJ31 FBA_DQS_RN6 G11 RFU FBC_DEBUG G19 R996 1 2
QSA#7 AJ35 FBA_DQS_RN7 G12 RFU 60.4_0402_1%
G14 RFU
P29 RFU +1.8VS G15 RFU
R29 RFU G24 RFU
L29 RFU FBA_DEBUG T30 R997 1 2 G25 RFU +PCIE
M29 RFU 60.4_0402_1% G27 RFU
AD29 RFU G28 RFU L68
AE29 RFU FBAC_DLLAVDD J19 0.01U_0402_25V7K 2 1
AG29 RFU FBAC_PLLAVDD J18
AH29 RFU 1 1 1 BLM18PG181SN1D_0603
C1152 C1153 C1154
+PCIE

L69 2 2 2
FB_DLLAVDD AG27 1U_0402_6.3V4Z 1 2 1U_0402_6.3V4Z4.7U_0603_6.3V6K
FB_PLLAVDD AF27
+1.8VS BLM18PG181SN1D_0603 FBCAL_PD_VDDQ K27 R998 1 2 30_0402_1% +1.8VS
1 1 1
C1155 C1156 C1157 FBCAL_PU_GND L27 R1000 1 2 30_0402_1%
1

@
R999 4.7U_0603_6.3V6K 0.057 Amps FBCAL_TERM_GND M27 R1001 1 2 40.2_0402_1%
Rt 2 2 2 @
1K_0402_1%
NB9P-GS_BGA 969~D
2

J27 FB_VREF 0.01U_0402_25V7K

1

1 @
@ C1158
R1002 Rb NB9P-GS_BGA 969~D for NB9P-GE, the R998/R1000 are 40 ohm
1K_0402_1% 0.1U_0402_16V4Z For NB9M-GS-B are 30.1 ohm.
2
2

VREF = 0.5 * FBVDDQ

Security Classification Compal Secret Data Compal Electronics, Inc.
DDR2: 1.0V = 2.0V * 1K/(1K + 1K) Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

FBVREF = FBVDDQ * Rb/(Rt + Rb) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, December 26, 2007 Sheet 21 of 58
A
 5 4 3 2 1

DATA Bus

VRAM DDR2 chips (256MB & 512MB) Address

CMD0
0..31
A3
32..63

32Mx16 DDR2 400MHz *8==>512MB CMD1 A0 A0

CMD2 A2
32Mx16 DDR2 400MHz *4==>256MB
CMD3 A1 A1
CMD4 A3
QSA[7..0]
D 21,23 QSA[7..0] D
CMD5 A4
QSA#[7..0]
21,23 QSA#[7..0]
CMD6 A5
DQMA[7..0]
21,23 DQMA[7..0]
CMD7
MDA[63..0]
21,23 MDA[63..0]
CMD8 CS# CS#
CMD9 WE# WE#
CMD10 BA0 BA0
CMD11 CKE CKE
U63 U64 CMD12 ODT ODT
CMDA10 L2 B9 MDA7 CMDA10 L2 B9 MDA27
21,23 CMDA10 BA0 DQ15 BA0 DQ15
CMDA18 L3 B1 MDA0 CMDA18 L3 B1 MDA28 CMD13 A2
21,23 CMDA18 BA1 DQ14 BA1 DQ14
D9 MDA5 D9 MDA24
CMDA14 DQ13 MDA2 CMDA14 DQ13 MDA31
21,23 CMDA14 R2 A12 DQ12 D1 R2 A12 DQ12 D1 CMD14 A12 A12
CMDA16 P7 D3 MDA3 CMDA16 P7 D3 MDA30
21,23 CMDA16 A11 DQ11 A11 DQ11
CMDA17 M2 D7 MDA4 CMDA17 M2 D7 MDA25 CMD15 RAS# RAS#
21,23 CMDA17 A10/AP DQ10 A10/AP DQ10
CMDA20 P3 C2 MDA1 CMDA20 P3 C2 MDA29
21,23 CMDA20 A9 DQ9 A9 DQ9
CMDA19 P8 C8 MDA6 CMDA19 P8 C8 MDA26 CMD16 A11 A11
21,23 CMDA19 A8 DQ8 A8 DQ8
CMDA23 P2 F9 MDA23 CMDA23 P2 F9 MDA15
21,23 CMDA23 A7 DQ7 A7 DQ7
CMDA21 N7 F1 MDA18 CMDA21 N7 F1 MDA9 CMD17 A10 A10
21,23 CMDA21 A6 DQ6 A6 DQ6
CMDA22 N3 H9 MDA20 CMDA22 N3 H9 MDA12
21 CMDA22 A5 DQ5 A5 DQ5
CMDA24 N8 H1 MDA16 CMDA24 N8 H1 MDA8 CMD18 BA1 BA1
21 CMDA24 A4 DQ4 A4 DQ4
CMDA0 N2 H3 MDA17 CMDA0 N2 H3 MDA11
21 CMDA0 A3 DQ3 A3 DQ3
CMDA2 M7 H7 MDA21 CMDA2 M7 H7 MDA13 CMD19 A8 A8
21 CMDA2 A2 DQ2 A2 DQ2
CMDA3 M3 G2 MDA19 CMDA3 M3 G2 MDA10
21,23 CMDA3 A1 DQ1 A1 DQ1
CMDA1 M8 G8 MDA22 CMDA1 M8 G8 MDA14 CMD20 A9 A9
21,23 CMDA1 A0 DQ0 A0 DQ0
C C
CMD21 A6 A6
CLKA0# K8 A9 CLKA0# K8 A9
CLKA0 CK VDDQ1 CLKA0 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 CMD22 A5
VDDQ3 C3 VDDQ3 C3
CMDA11 K2 C7 CMDA11 K2 C7 CMD23 A7 A7
21,23 CMDA11 CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9
VDDQ6 E9
+1.8VS VDDQ6 E9
+1.8VS
CMD24 A4
VDDQ7 G1 VDDQ7 G1
CMDA8 L8 G3 CMDA8 L8 G3 CMD25 CAS# CAS#
21,23 CMDA8 CS VDDQ8 CS VDDQ8
VDDQ9 G7 VDDQ9 G7
CMDA9 K3 G9 CMDA9 K3 G9 CMD26 A13 A13
21,23 CMDA9 WE VDDQ10 WE VDDQ10
CMDA15 K7 A1 CMDA15 K7 A1 CMD27 BA2 BA2
21,23 CMDA15 RAS VDD1 RAS VDD1
E1 L76 E1 L75
CMDA25 VDD2 CMDA25 VDD2
21,23 CMDA25 L7 CAS VDD3 J9 2 1 L7 CAS VDD3 J9 2 1 CMD28
VDD4 M9 VDD4 M9
DQMA2 F3 R1 FBMA-L10-160808-300LMT DQMA1 F3 R1 FBMA-L10-160808-300LMT CMD29
DQMA0 LDM VDD5 DQMA3 LDM VDD5
B3 UDM B3 UDM
VDDL J1 VDDL J1 CMD30
VSSDL J7 1 1 VSSDL J7 1 1
CMDA12 K9 C1161 C1162 CMDA12 K9 C1159 C1160
21,23 CMDA12 ODT ODT
0.1U_0402_16V4Z 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 4.7U_0805_6.3V6K
QSA2 2 2 QSA1 2 2
F7 LDQS F7 LDQS
+1.8VS QSA#2 E8 A7 QSA#1 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1

VSSQ4 D2 VSSQ4 D2
R1003 QSA0 B7 D8 QSA3 B7 D8
1K_0402_1% QSA#0 UDQS VSSQ5 QSA#3 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
VSSQ7 F2 VSSQ7 F2
F8 F8
2

B +MEM_VREFA0 VSSQ8 +MEM_VREFA0 VSSQ8 B

J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
VSSQ10 H8 VSSQ10 H8
1

1 A2 NC#A2 A2 NC#A2
R1004 C1163 E2 A3 E2 A3
NC#E2 VSS1 NC#E2 VSS1
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
1K_0402_1% 0.1U_0402_16V4Z R3 J3 R3 J3
2 NC#R3 VSS3 NC#R3 VSS3 CLKA0
R7 N1 R7 N1 21 CLKA0
2

NC#R7 VSS4 NC#R7 VSS4

R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

1
R1005
HY5PS561621F-25 HY5PS561621F-25 475_0402_1%

Vref= 0.5* 1.8V for NB9M, R1004=1K ohm

2
CLKA0#
21 CLKA0#
Vref= 0.5* 1.8V for NB9P-GS/GE2, R1004=1K ohm
475ohm 1% for NB9M
NB9P-GE, keep 240ohm

+1.8VS DDR2 BGA MEMORY +1.8VS DDR BGA MEMORY

1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1173 C1174 C1175 C1176 C1177 C1178 C1179 C1180 C1164 C1165 C1166 C1167 C1168 C1169 C1170 C1171

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHANNEL A EXT. 256M_1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 22 of 58
5 4 3 2 1
 5 4 3 2 1

DATA Bus
Address 0..31 32..63
VRAM DDR2 chips (256MB & 512MB) CMD0 A3
CMD1 A0 A0
32Mx16 DDR2 400MHz *8==>512MB
CMD2 A2
32Mx16 DDR2 400MHz *4==>256MB CMD3 A1 A1
CMD4 A3
DQMA[7..0] CMD5 A4
D 21,22 DQMA[7..0] D
QSA#[7..0] CMD6 A5
21,22 QSA#[7..0]
QSA[7..0] CMD7
21,22 QSA[7..0]
MDA[63..0] CMD8 CS# CS#
21,22 MDA[63..0]
CMD9 WE# WE#
CMD10 BA0 BA0
CMD11 CKE CKE
U65 U66 CMD12 ODT ODT
CMDA10 L2 B9 MDA39 CMDA10 L2 B9 MDA59
21,22 CMDA10 BA0 DQ15 BA0 DQ15
CMDA18 L3 B1 MDA32 CMDA18 L3 B1 MDA60 CMD13 A2
21,22 CMDA18 BA1 DQ14 BA1 DQ14
D9 MDA38 D9 MDA58
CMDA14 DQ13 MDA34 CMDA14 DQ13 MDA62
21,22 CMDA14 R2 A12 DQ12 D1 R2 A12 DQ12 D1 CMD14 A12 A12
CMDA16 P7 D3 MDA33 CMDA16 P7 D3 MDA63
21,22 CMDA16 A11 DQ11 A11 DQ11
CMDA17 M2 D7 MDA37 CMDA17 M2 D7 MDA56 CMD15 RAS# RAS#
21,22 CMDA17 A10/AP DQ10 A10/AP DQ10
CMDA20 P3 C2 MDA35 CMDA20 P3 C2 MDA61
21,22 CMDA20 A9 DQ9 A9 DQ9
CMDA19 P8 C8 MDA36 CMDA19 P8 C8 MDA57 CMD16 A11 A11
21,22 CMDA19 A8 DQ8 A8 DQ8
CMDA23 P2 F9 MDA44 CMDA23 P2 F9 MDA51
21,22 CMDA23 A7 DQ7 A7 DQ7
CMDA21 N7 F1 MDA43 CMDA21 N7 F1 MDA53 CMD17 A10 A10
21,22 CMDA21 A6 DQ6 A6 DQ6
CMDA6 N3 H9 MDA47 CMDA6 N3 H9 MDA48
21 CMDA6 A5 DQ5 A5 DQ5
CMDA5 N8 H1 MDA40 CMDA5 N8 H1 MDA55 CMD18 BA1 BA1
21 CMDA5 A4 DQ4 A4 DQ4
CMDA4 N2 H3 MDA41 CMDA4 N2 H3 MDA52
21 CMDA4 A3 DQ3 A3 DQ3
CMDA13 M7 H7 MDA46 CMDA13 M7 H7 MDA49 CMD19 A8 A8
21 CMDA13 A2 DQ2 A2 DQ2
CMDA3 M3 G2 MDA42 CMDA3 M3 G2 MDA54
21,22 CMDA3 A1 DQ1 A1 DQ1
CMDA1 M8 G8 MDA45 CMDA1 M8 G8 MDA50 CMD20 A9 A9
21,22 CMDA1 A0 DQ0 A0 DQ0

C
CMD21 A6 A6 C
CLKA1# K8 A9 CLKA1# K8 A9
CLKA1 CK VDDQ1 CLKA1 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 CMD22 A5
VDDQ3 C3 VDDQ3 C3
CMDA11 K2 C7 CMDA11 K2 C7 CMD23 A7 A7
21,22 CMDA11 CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9
VDDQ6 E9
+1.8VS VDDQ6 E9
+1.8VS
CMD24 A4
VDDQ7 G1 VDDQ7 G1
CMDA8 L8 G3 CMDA8 L8 G3 CMD25 CAS# CAS#
21,22 CMDA8 CS VDDQ8 CS VDDQ8
VDDQ9 G7 VDDQ9 G7
CMDA9 K3 G9 CMDA9 K3 G9 CMD26 A13 A13
21,22 CMDA9 WE VDDQ10 WE VDDQ10
CMDA15 K7 A1 CMDA15 K7 A1 CMD27 BA2 BA2
21,22 CMDA15 RAS VDD1 RAS VDD1
E1 L78 E1 L77
CMDA25 VDD2 CMDA25 VDD2
21,22 CMDA25 L7 CAS VDD3 J9 2 1 L7 CAS VDD3 J9 2 1 CMD28
VDD4 M9 VDD4 M9
DQMA5 F3 R1 FBMA-L10-160808-300LMT DQMA6 F3 R1 FBMA-L10-160808-300LMT CMD29
DQMA4 LDM VDD5 DQMA7 LDM VDD5
B3 UDM B3 UDM
VDDL J1 VDDL J1 CMD30
VSSDL J7 1 1 VSSDL J7 1 1
CMDA12 K9 C1183 C1184 CMDA12 K9 C1181 C1182
21,22 CMDA12 ODT ODT
0.1U_0402_16V4Z 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 4.7U_0805_6.3V6K
+1.8VS QSA5 2 2 QSA6 2 2
F7 LDQS F7 LDQS
QSA#5 E8 A7 QSA#6 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
1

VSSQ3 B8 VSSQ3 B8
R1008 D2 D2
1K_0402_1% QSA4 VSSQ4 QSA7 VSSQ4
B7 UDQS VSSQ5 D8 B7 UDQS VSSQ5 D8
QSA#4 A8 E7 QSA#7 A8 E7
UDQS VSSQ6 UDQS VSSQ6
F2 F2
2

VSSQ7 VSSQ7
VSSQ8 F8 VSSQ8 F8
+MEM_VREFA1 J2 H2 +MEM_VREFA1 J2 H2 CLKA1
B VREF VSSQ9 VREF VSSQ9 21 CLKA1 B
VSSQ10 H8 VSSQ10 H8
1

1
1 A2 NC#A2 A2 NC#A2
R1009 C1185 E2 A3 E2 A3 R1010
1K_0402_1% NC#E2 VSS1 NC#E2 VSS1 475_0402_1%
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
0.1U_0402_16V4Z R3 J3 R3 J3
2 NC#R3 VSS3 NC#R3 VSS3
R7 N1 R7 N1
2

2
NC#R7 VSS4 NC#R7 VSS4 CLKA1#
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 21 CLKA1#

HY5PS561621F-25 HY5PS561621F-25 475ohm 1% for NB9M

NB9P-GE, keep 240ohm
Vref= 0.5* 1.8V for NB9M, R1009=1K ohm 1107 Change R1010 to 475 ohm
Vref= 0.5* 1.8V for NB9P-GS/GE2, R1009=1K ohm

+1.8VS DDR2 BGA MEMORY +1.8VS DDR BGA MEMORY

1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1195 C1196 C1197 C1198 C1199 C1200 C1201 C1202 C1186 C1187 C1188 C1189 C1190 C1191 C1192 C1193

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHANNEL A EXT. 256M_2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 23 of 58
5 4 3 2 1
 5 4 3 2 1

DATA Bus

VRAM DDR2 chips (256MB & 512MB) Address

CMD0
0..31
A3
32..63

32Mx16 DDR2 400MHz *8==>512MB CMD1 A0 A0

CMD2 A2
DQMB[7..0] CMD3 A1 A1
21,25 DQMB[7..0]
QSB#[7..0] CMD4 A3
21,25 QSB#[7..0]
D QSB[7..0] CMD5 A4 D
21,25 QSB[7..0]
MDB[63..0] CMD6 A5
21,25 MDB[63..0]
CMD7
CMD8 CS# CS#
CMD9 WE# WE#
VRAM2@ VRAM2@ CMD10 BA0 BA0
U67 U68
CMDB10 L2 B9 MDB11 CMDB10 L2 B9 MDB0 CMD11 CKE CKE
21,25 CMDB10 BA0 DQ15 BA0 DQ15
CMDB18 L3 B1 MDB13 CMDB18 L3 B1 MDB6
21,25 CMDB18 BA1 DQ14 BA1 DQ14
D9 MDB9 D9 MDB2 CMD12 ODT ODT
CMDB14 DQ13 MDB14 CMDB14 DQ13 MDB4
21,25 CMDB14 R2 A12 DQ12 D1 R2 A12 DQ12 D1
CMDB16 P7 D3 MDB15 CMDB16 P7 D3 MDB5 CMD13 A2
21,25 CMDB16 A11 DQ11 A11 DQ11
CMDB17 M2 D7 MDB8 CMDB17 M2 D7 MDB3
21,25 CMDB17 A10/AP DQ10 A10/AP DQ10
CMDB20 P3 C2 MDB12 CMDB20 P3 C2 MDB7 CMD14 A12 A12
21,25 CMDB20 A9 DQ9 A9 DQ9
CMDB19 P8 C8 MDB10 CMDB19 P8 C8 MDB1
21,25 CMDB19 A8 DQ8 A8 DQ8
CMDB23 P2 F9 MDB18 CMDB23 P2 F9 MDB27 CMD15 RAS# RAS#
21,25 CMDB23 A7 DQ7 A7 DQ7
CMDB21 N7 F1 MDB21 CMDB21 N7 F1 MDB28
21,25 CMDB21 A6 DQ6 A6 DQ6
CMDB22 N3 H9 MDB17 CMDB22 N3 H9 MDB24 CMD16 A11 A11
21 CMDB22 A5 DQ5 A5 DQ5
CMDB24 N8 H1 MDB23 CMDB24 N8 H1 MDB30
21 CMDB24 A4 DQ4 A4 DQ4
CMDB0 N2 H3 MDB22 CMDB0 N2 H3 MDB31 CMD17 A10 A10
21 CMDB0 A3 DQ3 A3 DQ3
CMDB2 M7 H7 MDB16 CMDB2 M7 H7 MDB25
21 CMDB2 A2 DQ2 A2 DQ2
CMDB3 M3 G2 MDB20 CMDB3 M3 G2 MDB29 CMD18 BA1 BA1
21,25 CMDB3 A1 DQ1 A1 DQ1
CMDB1 M8 G8 MDB19 CMDB1 M8 G8 MDB26
21,25 CMDB1 A0 DQ0 A0 DQ0
CMD19 A8 A8
CLKB0# K8 A9 CLKB0# K8 A9 CMD20 A9 A9
CLKB0 CK VDDQ1 CLKB0 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C C
VDDQ3 C3 VDDQ3 C3 CMD21 A6 A6
CMDB11 K2 C7 CMDB11 K2 C7
21,25 CMDB11 CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9 CMD22 A5
VDDQ6 E9 VDDQ6 E9
G1 +1.8VS G1 +1.8VS CMD23 A7 A7
CMDB8 VDDQ7 CMDB8 VDDQ7
21,25 CMDB8 L8 CS VDDQ8 G3 L8 CS VDDQ8 G3
VDDQ9 G7 VDDQ9 G7 CMD24 A4
CMDB9 K3 G9 CMDB9 K3 G9
21,25 CMDB9 WE VDDQ10 WE VDDQ10
CMD25 CAS# CAS#
CMDB15 K7 A1 VRAM2@ CMDB15 K7 A1 VRAM2@
21,25 CMDB15 RAS VDD1 RAS VDD1
E1 L80 E1 L79 CMD26 A13 A13
CMDB25 VDD2 CMDB25 VDD2
21,25 CMDB25 L7 CAS VDD3 J9 2 1 L7 CAS VDD3 J9 2 1
VDD4 M9 VDD4 M9 CMD27 BA2 BA2
DQMB2 F3 R1 FBMA-L10-160808-300LMT DQMB3 F3 R1 FBMA-L10-160808-300LMT
DQMB1 LDM VDD5 DQMB0 LDM VDD5
B3 UDM B3 UDM CMD28
VDDL J1 VDDL J1
VSSDL J7 1 VRAM2@ 1 VRAM2@ VSSDL J7 1 VRAM2@ 1 VRAM2@ CMD29
CMDB12 K9 C1205 C1206 CMDB12 K9 C1203 C1204
21,25 CMDB12 ODT ODT
CMD30
0.1U_0402_16V4Z 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 4.7U_0805_6.3V6K
QSB2 2 2 QSB3 2 2
F7 LDQS F7 LDQS
+1.8VS QSB#2 E8 A7 QSB#3 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1

VRAM2@ D2 D2
R1013 QSB1 VSSQ4 QSB0 VSSQ4
B7 UDQS VSSQ5 D8 B7 UDQS VSSQ5 D8
QSB#1 A8 E7 QSB#0 A8 E7
1K_0402_1% UDQS VSSQ6 UDQS VSSQ6
VSSQ7 F2 VSSQ7 F2
F8 F8
2

+MEM_VREFB0 VSSQ8 +MEM_VREFB0 VSSQ8

J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
VSSQ10 H8 VSSQ10 H8
1

A2 NC#A2 A2 NC#A2
B VRAM2@ B
1 VRAM2@ E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3 21 CLKB0
CLKB0
R1014 C1207 L1 E3 L1 E3
NC#L1 VSS2 NC#L1 VSS2

1
R3 J3 R3 J3 VRAM2@
1K_0402_1% 0.1U_0402_16V4Z NC#R3 VSS3 NC#R3 VSS3 R1015
R7 N1 R7 N1
2

2 NC#R7 VSS4 NC#R7 VSS4 475_0402_1%

R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

2
HY5PS561621F-25 HY5PS561621F-25 CLKB0#
21 CLKB0#

Vref= 0.5* 1.8V for NB9M, R1014=1K ohm

475ohm 1% for NB9M
Vref= 0.5* 1.8V for NB9P-GS/GE2, R1014=1K ohm NB9P-GE, keep 240ohm

1107 Change R1015 to 475 ohm

DDR2 BGA MEMORY
+1.8VS +1.8VS DDR BGA MEMORY

1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@ 1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@
C1217 C1218 C1219 C1220 C1221 C1222 C1223 C1224 C1208 C1209 C1210 C1211 C1212 C1213 C1214 C1215

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHANNEL B EXT. 256M_1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 24 of 58
5 4 3 2 1
 5 4 3 2 1

DATA Bus

VRAM DDR2 chips (256MB & 512MB) Address

CMD0
0..31
A3
32..63

32Mx16 DDR2 400MHz *8==>512MB CMD1 A0 A0

CMD2 A2
DQMB[7..0]
21,24 DQMB[7..0]
CMD3 A1 A1
QSB#[7..0]
21,24 QSB#[7..0]
CMD4 A3
QSB[7..0]
D 21,24 QSB[7..0] D
CMD5 A4
MDB[63..0]
21,24 MDB[63..0]
CMD6 A5
CMD7
CMD8 CS# CS#
CMD9 WE# WE#
VRAM2@ VRAM2@ CMD10 BA0 BA0
U69 U70
CMDB10 L2 B9 MDB39 CMDB10 L2 B9 MDB49 CMD11 CKE CKE
21,24 CMDB10 BA0 DQ15 BA0 DQ15
CMDB18 L3 B1 MDB35 CMDB18 L3 B1 MDB55
21,24 CMDB18 BA1 DQ14 BA1 DQ14
D9 MDB38 D9 MDB51 CMD12 ODT ODT
CMDB14 DQ13 MDB33 CMDB14 DQ13 MDB53
21,24 CMDB14 R2 A12 DQ12 D1 R2 A12 DQ12 D1
CMDB16 P7 D3 MDB32 CMDB16 P7 D3 MDB54 CMD13 A2
21,24 CMDB16 A11 DQ11 A11 DQ11
CMDB17 M2 D7 MDB36 CMDB17 M2 D7 MDB48
21,24 CMDB17 A10/AP DQ10 A10/AP DQ10
CMDB20 P3 C2 MDB34 CMDB20 P3 C2 MDB52 CMD14 A12 A12
21,24 CMDB20 A9 DQ9 A9 DQ9
CMDB19 P8 C8 MDB37 CMDB19 P8 C8 MDB50
21,24 CMDB19 A8 DQ8 A8 DQ8
CMDB23 P2 F9 MDB45 CMDB23 P2 F9 MDB59 CMD15 RAS# RAS#
21,24 CMDB23 A7 DQ7 A7 DQ7
CMDB21 N7 F1 MDB43 CMDB21 N7 F1 MDB60
21,24 CMDB21 A6 DQ6 A6 DQ6
CMDB6 N3 H9 MDB46 CMDB6 N3 H9 MDB56 CMD16 A11 A11
21 CMDB6 A5 DQ5 A5 DQ5
CMDB5 N8 H1 MDB40 CMDB5 N8 H1 MDB63
21 CMDB5 A4 DQ4 A4 DQ4
CMDB4 N2 H3 MDB41 CMDB4 N2 H3 MDB62 CMD17 A10 A10
21 CMDB4 A3 DQ3 A3 DQ3
CMDB13 M7 H7 MDB47 CMDB13 M7 H7 MDB58
21 CMDB13 A2 DQ2 A2 DQ2
CMDB3 M3 G2 MDB42 CMDB3 M3 G2 MDB61 CMD18 BA1 BA1
21,24 CMDB3 A1 DQ1 A1 DQ1
CMDB1 M8 G8 MDB44 CMDB1 M8 G8 MDB57
21,24 CMDB1 A0 DQ0 A0 DQ0
CMD19 A8 A8
CLKB1# K8 A9 CLKB1# K8 A9 CMD20 A9 A9
CLKB1 CK VDDQ1 CLKB1 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C C
VDDQ3 C3 VDDQ3 C3 CMD21 A6 A6
CMDB11 K2 C7 CMDB11 K2 C7
21,24 CMDB11 CKE VDDQ4 CKE VDDQ4
VDDQ5 C9 VDDQ5 C9 CMD22 A5
VDDQ6 E9 VDDQ6 E9
G1 +1.8VS G1 +1.8VS CMD23 A7 A7
CMDB8 VDDQ7 CMDB8 VDDQ7
21,24 CMDB8 L8 CS VDDQ8 G3 L8 CS VDDQ8 G3
VDDQ9 G7 VDDQ9 G7 CMD24 A4
CMDB9 K3 G9 CMDB9 K3 G9
21,24 CMDB9 WE VDDQ10 WE VDDQ10
CMD25 CAS# CAS#
CMDB15 K7 A1 VRAM2@ CMDB15 K7 A1 VRAM2@
21,24 CMDB15 RAS VDD1 RAS VDD1
E1 L82 E1 L81 CMD26 A13 A13
CMDB25 VDD2 CMDB25 VDD2
21,24 CMDB25 L7 CAS VDD3 J9 2 1 L7 CAS VDD3 J9 2 1
VDD4 M9 VDD4 M9 CMD27 BA2 BA2
DQMB5 F3 R1 FBMA-L10-160808-300LMT DQMB7 F3 R1 FBMA-L10-160808-300LMT
DQMB4 LDM VDD5 DQMB6 LDM VDD5
B3 UDM B3 UDM CMD28
VDDL J1 VDDL J1
VSSDL J7 1 VRAM2@ VSSDL J7 1 VRAM2@ 1 VRAM2@ CMD29
CMDB12 K9 C1227 1 VRAM2@ CMDB12 K9 C1225 C1226
21,24 CMDB12 ODT ODT
C1228 CMD30
0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_6.3V6K
+1.8VS QSB5 2 4.7U_0805_6.3V6K QSB7 2 2
F7 LDQS F7 LDQS
QSB#5 2 QSB#7
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
VSSQ2 B2 VSSQ2 B2
1

VRAM2@ B8 B8
R1018 VSSQ3 VSSQ3
VSSQ4 D2 VSSQ4 D2
QSB4 B7 D8 QSB6 B7 D8
1K_0402_1% QSB#4 UDQS VSSQ5 QSB#6 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
F2 F2
2

VSSQ7 VSSQ7
VSSQ8 F8 VSSQ8 F8
+MEM_VREFB1 J2 H2 +MEM_VREFB1 J2 H2 CLKB1
VREF VSSQ9 VREF VSSQ9 21 CLKB1
VSSQ10 H8 VSSQ10 H8
1

1
VRAM2@ 1 VRAM2@ A2 A2 VRAM2@
B R1019 C1229 NC#A2 NC#A2 R1020 B
E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3
L1 E3 L1 E3 475_0402_1%
1K_0402_1% 0.1U_0402_16V4Z NC#L1 VSS2 NC#L1 VSS2
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
2
R7 N1 R7 N1
2

2
NC#R7 VSS4 NC#R7 VSS4 CLKB1#
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 21 CLKB1#

HY5PS561621F-25 HY5PS561621F-25 475ohm 1% for NB9M

NB9P-GE, keep 240ohm
Vref= 0.5* 1.8V for NB9M, R1019=1K ohm 1107 Change R1020 to 475 ohm
Vref= 0.5* 1.8V for NB9P-GS/GE2, R1019=1K ohm

DDR2 BGA MEMORY

+1.8VS +1.8VS DDR BGA MEMORY

1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@ 1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@
C1239 C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1230 C1231 C1232 C1233 C1234 C1235 C1236 C1237

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHANNEL B EXT. 256M_2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 25 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS

R333 1 2 8.2K_0402_5% PCI_DEVSEL#

R334 1 2 8.2K_0402_5% PCI_STOP#

R335 1 2 8.2K_0402_5% PCI_TRDY#

R336 1 2 8.2K_0402_5% PCI_FRAME# U58B

D11 F1 PCI_REQ0#
R337 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# C8 AD1 GNT0# G4 PCI_GNT0# Place closely pin B10
D PCI_REQ1# D
R338 1 2 8.2K_0402_5% PCI _IRDY#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7
AD3 GNT1#/GPIO51 PCI_REQ2# CLK_PCI_ICH
E9 AD4 REQ2#/GPIO52 F13
R339 1 2 8.2K_0402_5% PCI_SERR# C9 F12
AD5 GNT2#/GPIO53

1
E10 E6 PCI_REQ3# @
R340 1 PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
2 8.2K_0402_5% B7 AD7 GNT3#/GPIO55 F6 R353
C7 10_0402_5%
+3VS AD8
C5 AD9 C/BE0# D8
G11 B4

2
AD10 C/BE1#
F8 AD11 C/BE2# D6
R341 1 2 8.2K_0402_5% PCI_PIRQA# F11 A5 1
AD12 C/BE3# @
E7 AD13
R342 1 2 8.2K_0402_5% PCI_PIRQB# A3 D3 PCI _IRDY# C537
AD14 IRDY# 8.2P_0402_50V
D2 AD15 PAR E3
R343 1 2
2 8.2K_0402_5% PCI_PIRQC# F10 AD16 PCIRST# R1 PCI_RST#
PCI_RST# 39,40
D5 C6 PCI_DEVSEL#
R344 1 AD17 DEVSEL#
2 8.2K_0402_5% PCI_PIRQD# D10 AD18 PERR# E4 PCI_PERR#
B3 C2 PCI_PLOCK#
R345 1 AD19 PLOCK#
2 8.2K_0402_5% PCI_PIRQE# F7 AD20 SERR# J4 PCI_SERR#
PCI_SERR# 40
C3 A4 PCI_STOP#
R346 1 PCI_PIRQF# AD21 STOP# PCI_TRDY#
2 8.2K_0402_5% F3 AD22 TRDY# F5
F4 D7 PCI_FRAME#
R347 1 PCI_PIRQG# AD23 FRAME#
2 8.2K_0402_5% C1 AD24
G7 C14 PLT_RST#
AD25 PLTRST# PLT_RST# 7,18,31,32,33,35
R348 2 1 8.2K_0402_5% PCI_PIRQH# H7 D4 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH 15
D1 R2 PCI_PME#
AD27 PME# PCI_PME# 40
G5 AD28
H6 AD29 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW
R349 1 2 8.2K_0402_5% PCI_REQ0# G1
H3
AD30 resistance.
R350 1 PCI_REQ1# AD31
2 8.2K_0402_5%
C R351 1 PCI_REQ2# C
2 8.2K_0402_5% Interrupt I/F
PCI_PIRQA# J5 H4 PCI_PIRQE#
R352 1 PIRQA# PIRQE#/GPIO2
2 8.2K_0402_5% PCI_REQ3# PCI_PIRQB# E1 PIRQB# PIRQF#/GPIO3 K6 PCI_PIRQF#
PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2 PCI_PIRQH# 39
ICH9-M ES_FCBGA676

A16 swap override Strap Boot BIOS Strap

B B
Low= A16 swap override Enble
PCI_GNT3# High= Default * PCI_GNT0# SPI_CS#1 Boot BIOS Location

@ R354 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%

1 0 PCI

1 1 LPC *
+3VALW

@ R356
SPI_CS1#_R 1 2
28 SPI_CS1#_R
1K_0402_5%
@ R355
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 26 of 58
5 4 3 2 1
 5 4 3 2 1

ICH9M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
+RTCVCC
+3VS
ICH_INTVRMEN Low = Internal VR Disabled
R359 1 2 1M_0402_5% SM_INTRUDER# 1015 add pull up to meet Intel design
High = Internal VR Enabled(Default) GATEA20 R358 1 2 10K_0402_5%
R357 1 2 330K_0402_5% LAN100_SLP
KB_RST# R362 1 2 10K_0402_5%
R361 2 330K_0402_5% ICH_INTVRMEN +3VS
1 ICH8M LAN100 SLP Strap
R363 1 2 180K_0402_5% ICH_SRTCRST# (Internal VR for VccLAN1.05 and VccCL1.05) R2058 2 1 SATA_LED# +VCCP
10K_0402_5%

1
0_0402_5%

0_0402_5%
D D
1
C538 @ @ ICH_LAN100_SLP Low = Internal VR Disabled H_DPRSTP# @ R365 1 2 56_0402_5%
R364 R360
0.1U_0402_16V4Z High = Internal VR Enabled(Default) H_DPSLP# @ R366 1 2 56_0402_5%
2

2
LPC_AD[0..3] 32,39,40
U58A
ICH_RTCX1 C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
C24 RTCX2 FWH1/LAD1 K4
L6 LPC_AD2
R367 1 FWH2/LAD2
+RTCVCC 2 20K_0402_5% ICH_RTCRST# A25 RTCRST# FWH3/LAD3 K2 LPC_AD3
ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
1 C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 32,39,40
C539 +VCCP

RTC

LPC
1
CLRP2 ICH_INTVRMEN B22 J3
1U_0603_10V4Z SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
2 T50 PAD

2
E25 N7 GATEA20
GLAN_CLK A20GATE GATEA20 40
AJ27 H_A20M# R368
A20M# H_A20M# 4
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R369 1 H_DPRSTP#
DPRSTP# AJ25 2 H_DPRSTP# 5,7,51
F14 AE23 H_DPSLP# 0_0402_5%
H_DPSLP# 5

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R370 1 2 H_FERR#

LAN / GLAN
LAN_RXD2 FERR# H_FERR# 4
56_0402_5%
D13 AD22 H_PW RGOOD
LAN_TXD_0 CPUPWRGD H_PWRGOOD 4,5
D12 LAN_TXD_1
E13 AF25 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# 4
within 2" from R379
B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# 4 +VCCP
AG25 H_INTR

CPU
C INTR H_INTR 4 C
B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# 40
+1.5VS R371 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
AF23 H_NMI
NMI H_NMI 4
HDA_BITCLK AF6 AF24 H_SMI# R374
HDA_BIT_CLK SMI# H_SMI# 4
HDA_SYNC AH4 56_0402_5%
HDA_SYNC H_STPCLK#
STPCLK# AH27 H_STPCLK# 4
HDARST# AE7

2
HDA_RST# THRMTRIP_ICH# R379
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# 4,7,40
HDA_SDIN0 AF4
34 HDA_SDIN0 HDA_SDIN0
HDA_SDIN1 AG4 AG27 placed within 2" from
35 HDA_SDIN1 HDA_SDIN1 TP12
HDA_SDIN2 AH3 ICH9M
19 HDA_SDIN2 HDA_SDIN2
AE5

IHDA
HDA_SDIN3 SATA_RXN4_C
SATA4RXN AH11 SATA_RXN4_C 30
HDA_SDOUT AG5 AJ11 SATA_RXP4_C
HDA_SDOUT SATA4RXP SATA_RXP4_C 30
SATA_TXN4_C C540 2 1 0.01U_0402_50V7K
PAD T51 AG7
SATA4TXN AG12
AF12 SATA_TXP4_C C541 2 1 0.01U_0402_50V7K
SATA_TXN4 30 ODD
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP4 30
PAD T52 AE8 HDA_DOCK_RST#/GPIO34
SATA_LED# AG8
41 SATA_LED# SATALED# SATA_RXN5_C
SATA5RXN AH9 SATA_RXN5_C 38
SATA_RXN0_C AJ16 AJ9 SATA_RXP5_C
30 SATA_RXN0_C
SATA_RXP0_C AH16
SATA0RXN SATA5RXP
AE10 SATA_TXN5_C C542 2 1 0.01U_0402_50V7K
SATA_RXP5_C 38 e-SATA
30 SATA_RXP0_C SATA0RXP SATA5TXN SATA_TXN5 38
C543 2 0.01U_0402_50V7K SATA_TXN0_C SATA_TXP5_C C544 2 1 0.01U_0402_50V7K De-feature disable
P- HDD 30 SATA_TXN0
C545
1
1 2 0.01U_0402_50V7K SATA_TXP0_C
AF17
AG17
SATA0TXN SATA5TXP AF10 SATA_TXP5 38
30 SATA_TXP0 SATA0TXP
AH18 CLK_PCIE_SATA#
SATA_CLKN CLK_PCIE_SATA# 15

SATA
SATA_RXN1_C AH13 AJ18 CLK_PCIE_SATA
30 SATA_RXN1_C SATA1RXN SATA_CLKP CLK_PCIE_SATA 15
SATA_RXP1_C
S- HDD 30 SATA_RXP1_C
C546 1 2 0.01U_0402_50V7K SATA_TXN1_C
AJ13
AG14
SATA1RXP SATARBIAS# AJ7
AH7 R382 1 2
30 SATA_TXN1 SATA1TXN SATARBIAS
C547 1 2 0.01U_0402_50V7K SATA_TXP1_C AF14
30 SATA_TXP1 SATA1TXP 24.9_0402_1%

B
1212 Swap SATA1 and SATA4 ICH9-M ES_FCBGA676 Within 500 mils B

1 0 0 8 a dd the m for Inte l s ugge stion

R439 33_0402_5% HDA_BITCLK
XOR CHAIN ENTRANCE STRAP:RSVD 19 HDA_VGA_BITCLK
R373 33_0402_5%
1
1
2
2
+3VS 35 HDA_BITCLK_MDC
R372 33_0402_5% 1 2 VGA ICH9-M
34 HDA_BITCLK_CODEC
R440 33_0402_5% 1 2 HDA_SYNC
19 HDA_VGA_SYNC
@ R383 R375 33_0402_5% 1 2 @
35 HDA_SYNC_MDC
1 2 HDA_SDOUT_CODEC R376 33_0402_5% 1 2 MDC BATT1
34 HDA_SYNC_CODEC
1K_0402_5%
R442 33_0402_5% 1 2 HDARST#
19 HDA_VGA_RST#
R378 33_0402_5% 1 2
35 HDA_RST#_MDC
@ R384 R377 33_0402_5% 1 2 CODEC
34,40 HDA_RST#_CODEC
1 2 ICH_RSVD
ICH_RSVD 28
1K_0402_5% R444 33_0402_5% 1 2 HDA_SDOUT CR2032 RTC BATTERY
19 HDA_VGA_SDOUT +RTCVCC +3VL BATT1.1
R380 33_0402_5% 1 2
35 HDA_SDOUT_MDC
R381 33_0402_5% 1 2
34 HDA_SDOUT_CODEC
D36
R875 W=20mils 2 CONN@
W=20mils 1 2 1 R876 JBATT1
ICH_RTCX1 HDA_BITCLK 3 W=20mils 1 2 W=20mils 1 1
0_0402_5% 2 2
1

R386 @ 1 DAN202U_SC70 1K_0402_5% 3

ICH_RTCX2 R385 C906 GND
ICH_RSVD HDA_SDOUT_CODEC 1 2 4 GND
10_0402_5%
10M_0402_5% 2.2U_0603_6.3V4Z ACES_85205-02001
2
0 0 1 1
2

C548 C549 Place near ICH9

A A
1
15P_0402_50V8J 15P_0402_50V8J @
0 1 2 2 C550
10P_0402_25V8K
2
1 0
Y3
1 1 1 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
2 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,SATA,LPC
32.768KHZ_12.5P_MC-146 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 27 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SIRQ Place closely pin AF3 Place closely pin H1

R389 10K_0402_5% +3VALW R393 1 2 2.2K_0402_5% 1025 change to follow IBT00 design for G-sensor
1 2 PM_CLKRUN# R392 1 2 2.2K_0402_5%
R390 8.2K_0402_5% U58C CLK_48M_ICH CLK_14M_ICH
1 2 GPIO39 ICH_SMBCLK G16 AH23 GPIO21
15,32,35,39 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
R391 10K_0402_5% ICH_SMBDATA GPIO19
15,32,35,39 ICH_SMBDATA A13 SMBDATA SMB SATA1GP/GPIO19 AF19 GPIO19 41

1
THERM_SCI# LINKALERT# GPIO36 @ @

SATA
GPIO
1 2 E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21
@ R394 8.2K_0402_5% ME_EC_CLK1 C17 AD20 GPIO37 R395 R396
CLKREQ#_C ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
1 2 B18 SMLINK1
R397 10K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
+3VS CLK14 CLK_14M_ICH 15
GPIO18 I CH_RI# CLK_48M_ICH
1 2 F19 clocks AF3 CLK_48M_ICH 15

2
@ R398 8.2K_0402_5% RI# CLK48
1 2 CR_WAKE# PAD T57 SUS_STAT# R4 P1 ICH_SUSCLK T58 PAD 1 @ 1 @
R399 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C552 C553
4 XDP_DBRESET# G19 SYS_RESET#

1
1
1 2 GPIO20 @ @ C16 SLP_S3#
D SLP_S3# SLP_S3# 40 D
R400 8.2K_0402_5% R402 R403 PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
7 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# 40 2 2
1 2 OCP# 10K_0402_5% 10K_0402_5% G17 SLP_S5#

SYS / GPIO
SLP_S5# SLP_S5# 40
R401 10K_0402_5% 40 EC_LID_OUT# EC_LID_OUT# A17
PM_BMBUSY# SMBALERT#/GPIO11 S4_STATE#
1 2 C10

2
2
@ R685 8.2K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
15 H_STP_PCI# A14 STP_PCI#
1 2 CR_CPPE# R404 1 2 0_0402_5% R_STP_CPU# E19 G20 PM_PWROK R406
15 H_STP_CPU# STP_CPU# PWROK PM_PWROK 7,40
R686 8.2K_0402_5% 1 2 10K_0402_5%
1 2 EC_SCI#_SB PM_CLKRUN# L4 M2 R407 1 2 0_0402_5%

Power MGT
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR 7,51
@ R687 8.2K_0402_5%
ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
31,32 ICH_PCIE_WAKE# WAKE# BATLOW#
SIRQ M5
40 SIRQ SERIRQ
1 2 GPIO37 0718 INSTALL R179 THERM_SCI# AJ23 R3 PWRBTN_OUT#
20,40 THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# 40
R689 8.2K_0402_5% R_EC_RSMRST#
R_EC_RSMRST# 47
1 2 GPIO57 VGATE D21 D20
15,51 VGATE VRMPWRGD LAN_RST#
R690 8.2K_0402_5%
1 2 GPIO48 R412 1 2 PAD T59 A20 D22 R_EC_RSMRST# R413 1 2 100_0402_5%
TP11 RSMRST# EC_RSMRST# 40
R691 8.2K_0402_5% 100K_0402_5% R795 1 2 10K_0402_5%
1 2 GPIO21 4 OCP# OCP# AG19 R5 CK_PW RGD
GPIO1 CK_PWRGD CK_PWRGD 15
R692 8.2K_0402_5% 33 CR_CPPE# CR_CPPE# AH21
GPIO19 EC_SCI# GPIO6
1 2 40 EC_SCI# 1 2 EC_SCI#_SB AG21 GPIO7 CLPWROK R6 M_PWROK
M_PWROK 7,40
R693 8.2K_0402_5% 40 EC_SMI# EC_SMI# R2094 0_0402_5% A21
GPIO36 GPIO8 +3VS
1 2 1 2 EC_SCI#_GPIO12 C12 GPIO12 SLP_M# B16
R694 8.2K_0402_5% 31 LAN_DSM#_SB LAN_DSM#_SB @ R2095 0_0402_5% C21
17/14 GPIO13 CL_CLK0 R420
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 7
1 2 GPIO49 1 2 GPIO18 K1 B19 0.1U_0402_16V4Z 1 2

GPIO
Controller Link
@ R870 10K_0402_5% 31,40 ISOLATEB R2085 1K_0402_1% GPIO20 GPIO18 CL_CLK1 3.24K_0402_1%
17 GPIO20 AF8 GPIO20

1
33 CR_WAKE# CR_WAKE# AJ22 F22 CL_DATA0 1
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 7
DIS/UMA A9 C19 C554 R421
GPIO27 CL_DATA1
D19 GPIO28
CLKREQ#_C L1 C25 CL_VREF0_ICH 453_0402_1%
15 CLKREQ#_C SATACLKREQ#/GPIO35 CL_VREF0 2
+3VS R423 1 2 GPIO38 AE19 A19 CL_VREF1_ICH

2
1102 Add test point 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C 1212 Add R2095 for EC_SCI# R438 1 2 GPIO48 AF21 F21 CL_RST# +3VALW C
32 EXP_CPPE# SDATAOUT1/GPIO48 CL_RST0# CL_RST# 7
0_0402_5% GPIO49 AH24 D18
GPIO57 GPIO49 CL_RST1# R425
1108 For LAN DSM A8 GPIO57/CLGPIO5
1109 Add GPIO22 for card reader wake up event +3VS 1 2 A16 XMIT_OFF 1 2
MEM_LED/GPIO24 XMIT_OFF 32
@R424 1K_0402_5% SB_SPKR M7 C18 GPIO10 3.24K_0402_1%
34 SB_SPKR SPKR GPIO10/SUS_PWR_ACK

1
MCH_ICH_SYNC#AJ24 C11 GPIO14 1

MISC
7 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_RSVD B21 C20 C555 R426
27 ICH_RSVD TP3 WOL_EN/GPIO9
AH20 1108 For LAN DSM
TP8 453_0402_1%
AJ20 TP9
SB_SPKR LAN_WOL_EN R796 2 2
+3VALW AJ21 1 +3VALW

2
LINKALERT# TP10
1 2
R405 10K_0402_5% low -->default ICH9-M ES_FCBGA676 100K_0402_5% 0.1U_0402_16V4Z
1 2 ICH_LOW_BAT# High -->No boot
R408 8.2K_0402_5% U58D
1 2 ICH_PCIE_WAKE# PCIE_RXN1 N29 V27 DMI_RXN0 DMI_RXN0 7
32 PCIE_RXN1 PERN1 DMI0RXN
R409 1K_0402_5% PCIE_RXP1 N28 V26 DMI_RXP0 DMI_RXP0 7
32 PCIE_RXP1 PERP1 DMI0RXP
1 2 I CH_RI# WLAN C556 1 2 0.1U_0402_16V4Z PCIE_C_TXN1 P27 U29 DMI_TXN0

Direct Media Interface

32 PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 7
R410 10K_0402_5% 32 PCIE_TXP1 C557 1 2 0.1U_0402_16V4Z PCIE_C_TXP1 P26 U28 DMI_TXP0 DMI_TXP0 7
XDP_DBRESET# PETP1 DMI0TXP
1 2
R411 10K_0402_5% PCIE_RXN2 L29 Y27 DMI_RXN1 DMI_RXN1 7
35 PCIE_RXN2 PERN2 DMI1RXN
1 2 S4_STATE# PCIE_RXP2 L28 Y26 DMI_RXP1 DMI_RXP1 7
35 PCIE_RXP2 PERP2 DMI1RXP
R414 10K_0402_5% Robson 35 PCIE_TXN2 C558 1 2 0.1U_0402_16V4Z PCIE_C_TXN2 M27 W29 DMI_TXN1 DMI_TXN1 7
ME_EC_CLK1 C559 1 PETN2 DMI1TXN
1 2 35 PCIE_TXP2 2 0.1U_0402_16V4Z PCIE_C_TXP2 M26 PETP2 DMI1TXP W28 DMI_TXP1 DMI_TXP1 7
R416 10K_0402_5%

PCI - Express
1 2 ME_EC_DATA1 PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 7
32 PCIE_RXN3 PERN3 DMI2RXN
R417 10K_0402_5% PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 7
32 PCIE_RXP3 PERP3 DMI2RXP
1 2 GPIO10 TV Tuner 32 PCIE_TXN3 C560 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 7
R418 10K_0402_5% C561 1 PETN3 DMI2TXN
32 PCIE_TXP3 2 0.1U_0402_16V4Z PCIE_C_TXP3 K26 PETP3 DMI2TXP AA28 DMI_TXP2 DMI_TXP2 7
1 2 EC_LID_OUT# 1008 no stuff
@ R419 10K_0402_5% GLAN_RXN G29 AD27 DMI_RXN3 DMI_RXN3 7
31 GLAN_RXN PERN4 DMI3RXN
1 2 EC_SMI# GLAN_RXP G28 AD26 DMI_RXP3 DMI_RXP3 7
31 GLAN_RXP PERP4 DMI3RXP
@ R695 8.2K_0402_5% GLAN 31 GLAN_TXN C564 1 2 0.1U_0402_16V4Z GLAN_TXN_C H27 AC29 DMI_TXN3 DMI_TXN3 7
B GPIO14 C565 1 0.1U_0402_16V4Z GLAN_TXP_C PETN4 DMI3TXN DMI_TXP3 B
1 2 31 GLAN_TXP 2 H26 PETP4 DMI3TXP AC28 DMI_TXP3 7
R696 8.2K_0402_5%
1 2 EC_SCI#_GPIO12 PCIE_RXN5 E29 T26 CLK_PCIE_ICH#
33 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 15
@R2096 10K_0402_5% PCIE_RXP5 E28 T25 CLK_PCIE_ICH
33 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 15
1 2 XMIT_OFF 1394_CR1 33 PCIE_TXN5 C608 1 2 0.1U_0402_16V4Z PCIE_C_TXN5 F27
R2101 10K_0402_5% C577 1 PETN5
33 PCIE_TXP5 2 0.1U_0402_16V4Z PCIE_C_TXP5 F26 PETP5 DMI_ZCOMP AF29 R428 24.9_0402_1% Within 500 mils
1212 For WLAN issue AF28 DMI_IRCOMP 1 2 +1.5VS
PCIE_RXN4 DMI_IRCOMP
32 PCIE_RXN4 C29 PERN6/GLAN_RXN
PCIE_RXP4 C28 AC5 USB20_N0
32 PCIE_RXP4 PERP6/GLAN_RXP USBP0N USB20_N0 38
New Card 32 PCIE_TXN4 C562 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 D27 AC4 USB20_P0 USB-0 Right side
PETN6/GLAN_TXN USBP0P USB20_P0 38
C563 1 2 0.1U_0402_16V4Z PCIE_C_TXP4 D26 AD3 USB20_N1
Board ID 32 PCIE_TXP4 PETP6/GLAN_TXP USBP1N
USBP1P AD2 USB20_P1
USB20_N1 38
USB20_P1 38 USB-1 Right side
1212 Swap PCIE GLAN and New Card PAD T61 D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 38
PAD T62 D24 AC2 USB20_P2 USB-2 E-SATA & USB Combo
+3VS +3VS SPI_CS0# USBP2P USB20_P2 38
26 SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3
SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 42
AA4 USB20_P3 USB-3 Dock
USBP3P USB20_P3 42
USB20_N4
PAD T63 D25 SPI_MOSI SPI USBP4N AB2 USB20_N4 17
2

PAD T64 E23 AB3 USB20_P4 USB-4 USB Camera

SPI_MISO USBP4P USB20_P4 17
R776 R774 AA1 USB20_N5
USBP5N USB20_N5 32
USB_OC#0 N4 AA2 USB20_P5 USB-5 WLAN
OC0#/GPIO59 USBP5P USB20_P5 32
10K_0402_5% 10K_0402_5% R429 1 2 0_0402_5% USB_OC#1 N5 W5 USB20_N6
38 BT_OFF OC1#/GPIO40 USBP6N USB20_N6 38
USB_OC#2 USB20_P6
N6 USB W4 USB20_P6 38 USB-6 Bluetooth
1

DIS/UMA 17/14 WXMIT_OFF# OC2#/GPIO41 USBP6P USB20_N7

P6 OC3#/GPIO42 USBP7N Y3 USB20_N7 38
RP31 USB_OC#4 M1 Y2 USB20_P7 USB-7 Fingerprint
OC4#/GPIO43 USBP7P USB20_P7 38
2

USB_OC#6 4 5 USB_OC#5 N2 W1 USB20_N8

+3VALW OC5#/GPIO29 USBP8N USB20_N8 32
@ @ USB_OC#1 3 6 USB_OC#6 M4 W2 USB20_P8 USB-8 MiniCard(TV)
OC6#/GPIO30 USBP8P USB20_P8 32
R777 R775 USB_OC#2 2 7 USB_OC#7 M3 V2 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 32
10K_0402_5% 10K_0402_5% USB_OC#4 1 8 USB_OC#8 N3 V3 USB20_P9 USB-9 New Card
OC8#/GPIO44 USBP9P USB20_P9 32
USB_OC#9 N1 U5 USB20_N10
USB20_N10 38
1

10K_1206_8P4R_5% USB_OC#10 OC9#/GPIO45 USBP10N USB20_P10

USB_OC#11
P5 OC10#/GPIO46 USBP10P U4
USB20_N11
USB20_P10 38 USB-10 Left Side
P3 OC11#/GPIO47 USBP11N U1 USB20_N11 38
RP32 U2 USB20_P11 USB-11 Touch Screen
A USBP11P USB20_P11 38 A
Discrete-->H 17" USB_OC#7 4 5 USBRBIAS AG2
USB_OC#8 USBRBIAS
3 6 AG1 USBRBIAS#
1

UMA-->L platform-->H USB_OC#9 2 7

USB_OC#0 1 8 R430 ICH9-M ES_FCBGA676
14" 10K_1206_8P4R_5% 22.6_0402_1%
platform-->L
2

RP33
1008 add board ID detection WXMIT_OFF#
USB_OC#5
4 5 Within 500 mils
Security Classification Compal Secret Data Compal Electronics, Inc.
3 6 Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
USB_OC#10 2 7
USB_OC#11 1 8 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
10K_1206_8P4R_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 28 of 58
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U58E

20 mils U58F AA26 H5
VSS[001] VSS[107]
A23 VCCRTC
G3: 6uA A15 AA27 J23
1634mA VCC1_05[01] VSS[002] VSS[108]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
B15 0.1U_0402_16V4Z AA3 J26
ICH_V5REF_RUN VCC1_05[02] VSS[003] VSS[109]
A6 2mA C15 AA6 J27
V5REF VCC1_05[03] VSS[004] VSS[110]
1 1 VCC1_05[04] D15 1 1 AB1 VSS[005] VSS[111] AC22
C566 C567 E15 C568 C569 AA23 K28
ICH_V5REF_SUS 2mA VCC1_05[05] VSS[006] VSS[112]
AE1 V5REF_SUS VCC1_05[06] F15 AB28 VSS[007] VSS[113] K29
L11 0.1U_0402_16V4Z AB29 L13
2 2 VCC1_05[07] 2 2 VSS[008] VSS[114]
AA24 646mA L12 AB4 L15
VCC1_5_B[01] VCC1_05[08] VSS[009] VSS[115]
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB5 VSS[010] VSS[116] L2
AB24 VCC1_5_B[03] VCC1_05[10] L16 AC17 VSS[011] VSS[117] L26
AB25 L17 +1.5VS AC26 L27
VCC1_5_B[04] VCC1_05[11] VSS[012] VSS[118]
AC24 VCC1_5_B[05] VCC1_05[12] L18 AC27 VSS[013] VSS[119] L5
AC25 M11 R432 AC3 L7
D R431 VCC1_5_B[06] VCC1_05[13] 0.01U_0402_16V7K VSS[014] VSS[120] D
40 mils AD24 VCC1_5_B[07] VCC1_05[14] M18 1 2 AD1 VSS[015] VSS[121] M12
10U_0805_10V4Z CHB1608U301_0603

CORE
+1.5VS 1 2 AD25 VCC1_5_B[08] VCC1_05[15] P11 AD10 VSS[016] VSS[122] M13
CHB1608U301_0603 1 AE25 P18 1 1 AD12 M14
VCC1_5_B[09] VCC1_05[16] C574 C575 VSS[017] VSS[123]
1 1 1 AE26 VCC1_5_B[10] VCC1_05[17] T11 AD13 VSS[018] VSS[124] M15

220U_D2_4VM
+ C570 C571 C572 C573 AE27 T18 AD14 M16
VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
AE28 VCC1_5_B[12] VCC1_05[19] U11 AD17 VSS[020] VSS[126] M17
2 2
AE29 VCC1_5_B[13] VCC1_05[20] U18 AD18 VSS[021] VSS[127] M23
2 2 2 2
F25 VCC1_5_B[14] VCC1_05[21] V11 AD21 VSS[022] VSS[128] M28
G25 VCC1_5_B[15] VCC1_05[22] V12 AD28 VSS[023] VSS[129] M29
+5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z H24 V14 AD29 N11
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
H25 VCC1_5_B[17] VCC1_05[24] V16 AD4 VSS[025] VSS[131] N12
J24 VCC1_5_B[18] VCC1_05[25] V17 +VCCP AD5 VSS[026] VSS[132] N13
1

VCCA3GP
J25 VCC1_5_B[19] VCC1_05[26] V18 AD6 VSS[027] VSS[133] N14
R433 D13 K24 1 AD7 N15
VCC1_5_B[20] C576 VSS[028] VSS[134]
K25 VCC1_5_B[21] AD9 VSS[029] VSS[135] N16
100_0402_5% CH751H-40_SC76 L23 AE12 N17
VCC1_5_B[22] 22U_0805_6.3VAM VSS[030] VSS[136]
L24 R29 AE13 N18
2

VCC1_5_B[23] VCCDMIPLL 2 VSS[031] VSS[137]

L25 VCC1_5_B[24] AE14 VSS[032] VSS[138] N26
ICH_V5REF_RUN M24 W23 0317 change value +VCCP AE16 N27
VCC1_5_B[25] 23mA VCC_DMI[1] VSS[033] VSS[139]
1 20 mils M25 VCC1_5_B[26] VCC_DMI[2] Y23 AE17 VSS[034] VSS[140] P12
C849 N23 AE2 P13
VCC1_5_B[27] VSS[035] VSS[141]
N24 VCC1_5_B[28] AB23 AE20 P14
0.1U_0402_10V6K N25 VCC1_5_B[29]
48mA V_CPU_IO[1]
V_CPU_IO[2] AC23 AE24
VSS[036]
VSS[037]
VSS[142]
VSS[143] P15
2

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P24 VCC1_5_B[30] AE3 VSS[038] VSS[144] P16
P25 AG29 +3VS AE4 P17
VCC1_5_B[31] VCC3_3[01] 1 1 1 VSS[039] VSS[145]
R24 2mA AJ6 C578 C579 C580 AE6 P2
VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE9 VSS[041] VSS[147] P23
+5VALW +3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R26 VCC1_5_B[34] AF13 VSS[042] VSS[148] P28
2 2 2
R27 VCC1_5_B[35] VCC3_3[03] AD19 1 1 1 AF16 VSS[043] VSS[149] P29
C581 C582 C583

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 AF18 VSS[044] VSS[150] P4
1

T27 VCC1_5_B[37] VCC3_3[05] AG24 AF22 VSS[045] VSS[151] P7

R434 D14 T28 AC20 AH26 R11
C VCC1_5_B[38] VCC3_3[06] +3VS 2 2 2 (DMI) VSS[046] VSS[152] C
T29 VCC1_5_B[39] AF26 VSS[047] VSS[153] R12
10_0402_5% CH751H-40_SC76 U24 308mA AF27 R13
VCC1_5_B[40] 0.1U_0402_16V4Z VSS[048] VSS[154]
U25 B9 AF5 R14
2

ICH_V5REF_SUS VCC1_5_B[41] VCC3_3[08] VSS[049] VSS[155]

V24 VCC1_5_B[42] VCC3_3[09] F9 1 AF7 VSS[050] VSS[156] R15
20 mils V25 G3 C585 AF9 R16
VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[157]
1 U23 VCC1_5_B[44] VCC3_3[11] G6 AG13 VSS[052] VSS[158] R17

PCI
C850 W24 J2 AG16 R18
VCC1_5_B[45] VCC3_3[12] 2 VSS[053] VSS[159]
W25 VCC1_5_B[46] VCC3_3[13] J7 1008 Change power rail for Discrete platform AG18 VSS[054] VSS[160] R28
0.1U_0402_10V6K K23 K7 AG20 T12
2 VCC1_5_B[47] VCC3_3[14] VSS[055] VSS[161]
Y24 VCC1_5_B[48] AG23 VSS[056] VSS[162] T13
Y25 VCC1_5_B[49] AG3 VSS[057] VSS[163] T14
47mA 11mA AJ4 R778 1 2 0_0603_5% +3VS AG6 T15
VCCHDA VSS[058] VSS[164]
AG9 VSS[059] VSS[165] T16
R435 11mA VCCSUSHDA AJ3 R1038 1 2 +3VALW 1 AH12 T17
0_0603_5% C586 VSS[060] VSS[166]
+1.5VS 1 2 AJ19 VCCSATAPLL 1 AH14 VSS[061] VSS[167] T23
CHB1608U301_0603 C587 AH17 B26
0.1U_0402_16V4Z VSS[062] VSS[168]
VCCSUS1_05[1] AC8 AH19 VSS[063] VSS[169] U12
T65 2
1U_0603_10V4Z

10U_0805_10V4Z

0316 change design 1 1 AC16 F17 0.1U_0402_16V4Z AH2 U13

+1.5VS VCC1_5_A[01] VCCSUS1_05[2] T66 2 VSS[064] VSS[170]
C588 C589 AD15 AH22 U14
VCC1_5_A[02] VSS[065] VSS[171]
1 AD16 VCC1_5_A[03] AH25 VSS[066] VSS[172] U15
C590 AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 VCCSUS1_5_ICH_1 AH28 VSS[067] VSS[173] U16
2 2 T75
ARX

AF15 VCC1_5_A[05] AH5 VSS[068] VSS[174] U17

1U_0603_10V4Z AG15 F18 VCCSUS1_5_ICH_2 AH8 AD23
2 VCC1_5_A[06] VCCSUS1_5[2] T76 +3VALW VSS[069] VSS[175]
AH15 VCC1_5_A[07] AJ12 VSS[070] VSS[176] U26
AJ15 VCC1_5_A[08] AJ14 VSS[071] VSS[177] U27
VCCSUS3_3[01] A18 AJ17 VSS[072] VSS[178] U3
AC11 212mA D16 AJ8 V1
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] 1 1 VSS[073] VSS[179]

AD11 D17 C591 C592 B11 V13
VCC1_5_A[10] VCCSUS3_3[03] VSS[074] VSS[180]
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 B14 VSS[075] VSS[181] V15
AF11 0.1U_0402_16V4Z 0.1U_0402_16V4Z B17 V23
VCC1_5_A[12] 2 2 VSS[076] VSS[182]
ATX

AG10 VCC1_5_A[13] B2 VSS[077] VSS[183] V28

+1.5VS AG11 VCC1_5_A[14] B20 VSS[078] VSS[184] V29
B B
AH10 VCC1_5_A[15] B23 VSS[079] VSS[185] V4
1 AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 B5 VSS[080] VSS[186] V5
C593 B8 W26
VSS[081] VSS[187]
AC9 1342mA
VCC1_5_A[17] C26 VSS[082] VSS[188] W27
1U_0603_10V4Z C27 W3
2 VSS[083] VSS[189]
AC18 VCC1_5_A[18] E11 VSS[084] VSS[190] Y1
AC19 VCC1_5_A[19] E14 VSS[085] VSS[191] Y28
VCCSUS3_3[06] T1 E18 VSS[086] VSS[192] Y29
AC21 VCC1_5_A[20] VCCSUS3_3[07] T2 E2 VSS[087] VSS[193] Y4
VCCSUS3_3[08] T3 E21 VSS[088] VSS[194] Y5
G10 T4 +3VALW E24 AG28
+1.5VS VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E5 VSS[090] VSS[196] AH6
1 11mA 11mA T6 E8 AF2
C595 VCCSUS3_3[11] VSS[091] VSS[197]
VCCPUSB

+1.5VS AC12 VCC1_5_A[23] VCCSUS3_3[12] U6 1 F16 VSS[092] VSS[198] B25

AC13 U7 C594 F28
0.1U_0402_16V4Z VCC1_5_A[24] VCCSUS3_3[13] VSS[093]
AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F29 VSS[094]
2 4.7U_0603_6.3V6M
1 VCCSUS3_3[15] V7 G12 VSS[095]
C596 2
AJ5 VCCUSBPLL VCCSUS3_3[16] W6 G14 VSS[096] VSS_NCTF[01] A1
VCCSUS3_3[17] W7 G18 VSS[097] VSS_NCTF[02] A2
USB CORE

0.1U_0402_16V4Z AA7 Y6 G21 A28

2 VCC1_5_A[26] VCCSUS3_3[18] VSS[098] VSS_NCTF[03]
AB6 VCC1_5_A[27] VCCSUS3_3[19] Y7 G24 VSS[099] VSS_NCTF[04] A29
AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G26 VSS[100] VSS_NCTF[05] AH1
AC6 VCC1_5_A[29] G27 VSS[101] VSS_NCTF[06] AH29
AC7 VCC1_5_A[30] G8 VSS[102] VSS_NCTF[07] AJ1
H2 VSS[103] VSS_NCTF[08] AJ2
+3VS T69 VCC_LAN1_05_INT_ICH_1 A10 H23 AJ28
T70 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCCL1_05_ICH VSS[104] VSS_NCTF[09]
A11 VCCLAN1_05[2] VCCCL1_05 G22 H28 VSS[105] VSS_NCTF[10] AJ29
T71
VCCCL1_5 G23 H29 VSS[106] VSS_NCTF[11] B1
A12 VCCLAN3_3[1] VSS_NCTF[12] B29
B12 19/78/78mA 19/73/73mA
VCCLAN3_3[2]
0.1U_0402_16V4Z

1 23mA
VCCCL3_3[1] A24 1 @
C597 R436 CHB1608U301_0603 B24 +3VS C598 ICH9-M ES_FCBGA676
VCCCL3_3[2]
GLAN POWER

A 1U_0603_10V4Z A
1 2 A27 VCCGLANPLL
+1.5VS R437 80mA
2 2
10U_0805_10V4Z

2.2U_0603_6.3V4Z

+1.5VS 1 2 D28 VCCGLAN1_5[1]

D29 VCCGLAN1_5[2]
1 1 CHB1608U301_0603 E26
C599 C600 VCCGLAN1_5[3]
1 E27 VCCGLAN1_5[4]
C601 +3VS 1mA
A26
2 2 4.7U_0805_10V4Z
2
VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

HDD Connector
CONN@
0903 change Qty JHDD1
+5VS
GND 1
0.1U_0402_16V4Z 2 SATA_TXP0
A+ SATA_TXP0 27
3 SATA_TXN0
A- SATA_TXN0 27
1 1 1 GND 4
C603 C604 C605 5 SATA_RXN0 C602 2 1 0.01U_0402_16V7K
B- SATA_RXN0_C 27
6 SATA_RXP0 C607 2 1 0.01U_0402_16V7K
B+ SATA_RXP0_C 27
GND 7
2 2 2
D 10U_0805_10V4Z 0.1U_0402_16V4Z Near CONN side. D

V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10
GND 11 0903 change
GND 12
GND 13

+3VS
0903 change V5 14
+5VS
23 GND V5 15
24 GND V5 16
GND 17
0.1U_0402_16V4Z 18
Reserved
GND 19
1 @ 1 @ V12 20
C609 C610 21
V12
V12 22
2 2
share HDD2
1000P_0402_50V7K SUYIN_127072FR022G210ZR_RV

DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA

SUYIN_127043FR022G204ZL_22P_NR
Pleace near HD CONN

2nd HDD Connector-option

CONN@
0903 change Qty JHDD2
+5VS
C C
GND 1
0.1U_0402_16V4Z 2 SATA_TXP1
A+ SATA_TXP1 27
3 SATA_TXN1
A- SATA_TXN1 27
1 1 1 GND 4
C613 C614 C615 5 SATA_RXN1 C612 2 1 0.01U_0402_16V7K
B- SATA_RXN1_C 27
6 SATA_RXP1 C617 2 1 0.01U_0402_16V7K
B+ SATA_RXP1_C 27
GND 7
2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z Near CONN side.
V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10 0903 change
GND 11
GND 12
GND 13
V5 14
+3VS 23 15 +5VS
GND V5
24 GND V5 16
GND 17
0.1U_0402_16V4Z 10U_0603_6.3V6M 18
Reserved
GND 19
1 @ 1 @ 1 @ 1 @ V12 20
C619 C620 C621 C618 21
V12
V12 22
2 2 2 2
1000P_0402_50V7K 1U_0603_10V4Z SUYIN_127072FR022G210ZR_RV

DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA

Pleace near HD CONN SUYIN_127043FR022G204ZL_22P_NR

B B

CD-ROM Connector
+5VS JODD
Placea caps. near ODD CONN.
GND 1
2 SATA_TXP4
A+ SATA_TXP4 27
3 SATA_TXN4
A- SATA_TXN4 27
GND 4
5 SATA_RXN4 C622 2 1 0.01U_0402_16V7K
B- SATA_RXN4_C 27
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1 1 1 1 6 SATA_RXP4 C623 2 1 0.01U_0402_16V7K

B+ SATA_RXP4_C 27
C624 C625 C626 C627 7
GND

2 2 2 2
Near CONN side.
DP 8
V5 9
V5 10 +5VS
14 GND MD 11
15 GND GND 12
GND 13

SUYIN_127382FR013G509ZR ZZZ1

A A
1009 Update to correct CIS
LA-4082P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

+3V_LAN
1025 add to meet HP request Close to Pin16,37,46,53 +3V_LAN
+AVDD33 L74
2 2 0_0603_5% 0.1U_0402_16V4Z
+3V_LAN +3VALW C650 C651 2 2 2 2
C631 C649 C642 C643
0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 1 1 0.1U_0402_16V4Z
R1106 1 1 1 1
1 2
0_1206_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Close to Pin2 & pin59
D D

S
1 3

4
.
7
uo
Hk
Q106 +LAN_VDD12

c
h
e
AP2305GN

G
2
+LAN_VDD12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
40 LANPWR#
L83 2 2 2 2 2 2
+CTRL_18 1 2 C636 C637 C638 C639 C640 C641
4.7UH_1008HC-472EJFS-A_5%_1008
Close to Pin1 2 2 1 1 1 1 1 1
C630 C629

22U_0805_6.3VAM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1
Place Close to Chip
U18
0.1U_0402_16V4Z
28 GLAN_RXP C653 1 2 PCIE_RXP2_LAN 29 45 LAN_DO
HSOP EEDO LAN_DI 0.1U_0402_16V4Z 0.1U_0402_16V4Z
EEDI/AUX 47
28 GLAN_RXN C654 1 2 PCIE_RXN2_LAN 30 48 LAN_SK
HSON EESK LAN_CS
EECS 44 2 2 2 2 2
0.1U_0402_16V4Z 23 R453 1 2 +3V_LAN C644 C645 C646 C647 C648
28 GLAN_TXP HSIP 3.6K_0402_5%
28 GLAN_TXN 24 HSIN 1 1 1 1 1
LED3 54
55 U17
GLAN_REQ# LED2 LAN_LINK# LAN_DO 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
15 CLKREQ#_9 1 2 33 CLKREQB LED1 56 4 DO GND 5 2
R456 0_0402_5% 57 LAN_ACTIVITY# LAN_DI 3 6 C652
LED0 LAN_SK DI NC
15 CLK_PCIE_LAN 26 REFCLK_P 2 SK NC 7
LAN_CS 1 8 +3VALW
LAN_MDI0+ CS VCC 1
0.1U_0402_16V4Z
15 CLK_PCIE_LAN# 27 3

B3
e0
a0
dm
f
o
r
8
1
1
1
C
C REFCLK_N MDIP0 LAN_MDI0- AT93C46-10SI-2.7_SO8 C
MDIN0 4

A
20 6 LAN_MDI1+
7,18,26,32,33,35 PLT_RST# PERSTB MDIP1 +LAN_EVDD12
7 LAN_MDI1-
MDIN1 LAN_MDI2+
MDIP2 9
+CTRL_18 1 10 LAN_MDI2-
SROUT12 MDIN2 LAN_MDI3+ L84
MDIP3 12 +LAN_VDD12
+LAN_VDD12 5 13 LAN_MDI3- 0_0603_5%
FB12 MDIN3 Y2 2 2
+3V_LAN R2048 62 LAN_X1 2 1LAN_X2 C632 C633
0_0603_5% ENSR 0.1U_0402_16V4Z
DVDD12 21 +LAN_VDD12
R446 1 2 64 32 25MHZ_20P
2.49K_0402_1% RSET DVDD12 1 1
DVDD12 38 1 1
43 C257 C256
R454 DVDD12 0.1U_0402_16V4Z
DVDD12 49
28,32 ICH_PCIE_WAKE# 1 2 GLAN_WAKE# 19 52 27P_0402_50V8J 27P_0402_50V8J
0_0402_5% LANWAKEB DVDD12 2 2
28,40 ISOLATEB ISOLATEB 36 ISOLATEB
EVDD12 22 +LAN_EVDD12
EVDD12 28
LAN_X1 60
+3VS CKTAL1
LAN_X2 61 16
CKTAL2 VDD33
VDD33 37
1

@ 46 +3V_LAN
R445 VDD33
VDD33 53
65 EXPOSE_PAD
1K_0402_1%
63 L85 +3V_LAN
LAN Conn.
2

ISOLATEB VDDSR 0_0603_5%

25 EGND
2 +AVDD33 CONN@
AVDD33 JRJ45
31 EGND AVDD33 59 1 1
R443 C634 C635 13
B +3V_LAN Yellow LED+ B
AVDD12 8
15K_0402_5% 15 11 22U_0805_6.3VAM 0.1U_0402_16V4Z LAN_ACTIVITY# R452 2 1 300_0402_5% 14
NC AVDD12 2 2 Yellow LED-
17 NC AVDD12 14 1 SHLD1 16
18 NC AVDD12 58 +LAN_VDD12 42 RJ45_MIDI3- 8 PR4-
34 @ 9
NC C656 DETECT PIN1
35 NC 1 2 +3VALW 42 RJ45_MIDI3+ 7 PR4+
39 50 @ R2074 10K_0402_5% 68P_0402_50V8K 2
NC IGPIO LAN_DSM#
40 NC OGPIO 51 1 2 LAN_DSM#_KBC 40 42 RJ45_MIDI1- 6 PR2-
41 @ R2075 0_0402_5%
NC
42 NC 1 2 LAN_DSM#_SB 28 42 RJ45_MIDI2- 5 PR3-
R2086 0_0402_5%
RTL8111C-GR_QFN64_9X9 42 RJ45_MIDI2+ 4 PR3+
1108 Add LAN DSM function
42 RJ45_MIDI1+ 3 PR2+
U19 R450
1 24 C1121 1 2 1 2 42 RJ45_MIDI0- 2
LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- 0.01U_0402_16V7K 75_0402_1% PR1-
2 TD1+ MX1+ 23 DETCET PIN2 10
LAN_MDI3+ 3 22 RJ45_MIDI3+ R447 @ 2 42 RJ45_MIDI0+ 1
TD1- MX1- C2105 C657 PR1+
4 TCT2 MCT2 21 1 2 1 2 SHLD1 15
LAN_MDI2- 5 20 RJ45_MIDI2- 0.01U_0402_16V7K 75_0402_1% 68P_0402_50V8K 11
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+ R448 +3V_LAN Green LED+
6 TD2- MX2- 19
C2106 LAN_LINK# 1 R451 2
7 TCT3 MCT3 18 1 2 1 2 1 300_0402_5% 12 Green LED-
LAN_MDI1- 8 17 RJ45_MIDI1- 0.01U_0402_16V7K 75_0402_1%
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ R449 FOX_JM36113-P1122-7F
9 TD3- MX3- 16
10 15 C2107 1 2 1 2
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- 0.01U_0402_16V7K 75_0402_1%
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+ LANGND
TD4- MX4-
NS692405 1 1
C661 C662
HP PoE solution C658 0.1U_0402_16V4Z 4.7U_0805_10V4Z
A RJ45_GND 1 2 2 A
2

1 1 1 1 1000P_1808_3KV7K
C659 C660 C663 C664

0.01U_0402_16V7K 0.01U_0402_16V7K
0.01U_0402_16V7K 2 2 2 2 0.01U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
Place these components 8111C GLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
colsed to LAN chip AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 31 of 58
5 4 3 2 1
 A B C D E

Mini Card 0--WLAN 1022 change to follow HP design Mini Card 2---TV tuner
1022 change to follow HP design
+1.5VS_WLAN +3VS_WLAN +3VALW
+1.5VS_TV +3VS_TV +3VALW
0.01U_0402_16V7K 4.7U_0805_10V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z
0.01U_0402_16V7K 4.7U_0805_10V4Z 0.1U_0402_16V4Z +1.5VS R476 1 2 0_0805_5% +1.5VS_TV
1 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C1343 C1344 C1345 1 1 1 1 1 1 1 1 1 1
C676 C677 C678 C1350 C672 C673 C674 C679 C680 C671
+3VS R477 1 2 0_0805_5% +3VS_TV
2 2 2
1 2 2 2 2 2 2 2 2 2 2 1
0906 add +3VALW 1 2
0.1U_0402_16V4Z 4.7U_0805_10V4Z @ R2119 0_0805_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1226 Add R to +3VALW
1226 Add R to +3VALW
+3VALW +3VS
0906 add debug channel
follow Mini-CARD SPEC 0903 update CIS to H5.2mm
CONN@ DEBUG@ 0_0402_5%
+3VS_WLAN JP14 DEBUG@ 0_0402_5%
CONN@ 1 2 ICH_PCIE_WAKE# 1 2 +3VS_TV DEBUG@ 0_0402_5%
JP13 @ R2118 0_0805_5% CH_DATA 1 2 DEBUG@ 0_0402_5%
3 3 4 4
ICH_PCIE_WAKE# 1 2 1 2 CH_CLK 5 6 +1.5VS_TV DEBUG@ 0_0402_5%
CH_DATA 1 2 R458 0_0805_5% CLKREQ#_6 5 6 R1577
38 CH_DATA 3 3 4 4 15 CLKREQ#_6 7 7 8 8 1 2 LPC_FRAME# 27,39,40
CH_CLK 5 6 1 2 +1.5VS 9 10 R1578 1 2 LPC_AD3
38 CH_CLK 5 6 9 10 LPC_AD3 27,39,40
15 CLKREQ#_10 CLKREQ#_10 7 8 R1564 0_0805_5% 11 12 R1579 1 2 LPC_AD2
7 8 15 CLK_PCIE_MCARD2# 11 12 LPC_AD2 27,39,40
9 10 1008 add them for debug card 13 14 R1580 1 2 LPC_AD1
9 10 15 CLK_PCIE_MCARD2 13 14 LPC_AD1 27,39,40
11 12 +1.5VS_WLAN 15 16 R1581 1 2 LPC_AD0
15 CLK_PCIE_MCARD0# 11 12 15 16 LPC_AD0 27,39,40
13 14 PLT_RST# 17 18
15 CLK_PCIE_MCARD0 13 14 17 18
15 15 16 16 15 CLK_DEBUG_PORT0 19 19 20 20
17 18 0_0402_5% 21 22 PLT_RST#
17 18 XMIT_OFF# R465 1 PCIE_C_RXN3 21 22 @ R466 1
19 19 20 20 28 PCIE_RXN3 2 23 23 24 24 2 0_0402_5% +3VALW
R461 0_0402_5% 21 22 PLT_RST# 28 PCIE_RXP3 R467 1 2 PCIE_C_RXP3 25 26 R468 1 2 0_0402_5% +3VS
21 22 25 26
28 PCIE_RXN1 1 2 PCIE_C_RXN1 23 23 24 24 R464 1 2 0_0402_5% +3VS 0_0402_5% 27 27 28 28 +1.5VS_TV
28 PCIE_RXP1 1 2 PCIE_C_RXP1 25 25 26 26 @ R1582 1 2 0_0402_5% +3VALW 29 29 30 30 ICH_SMBCLK
R463 0_0402_5% 27 28 +1.5VS_WLAN PCIE_TXN3 31 32 ICH_SMBDATA
27 28 28 PCIE_TXN3 31 32
29 30 ICH_SMBCLK PCIE_TXP3 33 34
PCIE_TXN1 29 30 ICH_SMBDATA 28 PCIE_TXP3 33 34
28 PCIE_TXN1
PCIE_TXP1
31 31 32 32 1023 change to follow 14" 35 35 36 36 USB20_N8 28
28 PCIE_TXP1 33 33 34 34 37 37 38 38 USB20_P8 28
35 35 36 36 USB20_N5 28 +3VS_TV 39 39 40 40
37 37 38 38 USB20_P5 28 41 41 42 42 1023 change to follow 14"
+3VS_WLAN 1 2 39 39 40 40 43 43 44 44
+3VALW 0_0603_5% 41 41 42 42 45 45 46 46
R2115 43 44 47 48 +1.5VS_TV
2 43 44 WL_LED# 41 47 48 2
45 45 46 46 49 49 50 50
47 47 48 48 +1.5VS_WLAN 51 51 52 52 +3VS_TV
1

49 49 50 50 53 G1 G2 54
@ @ 51 52 +3VS_WLAN 55 56
R478 R479 51 52 G3 G4
53 G1 G2 54
10K_0402_5% 100K_0402_5% 55 56 FOX_AS0B226-S99N-7F_52P
G3 G4
2

XMIT_OFF# FOX_AS0B226-S99N-7F_52P
0903 update CIS to H5.2mm
1

D88 D @
1 2 2 Q13
28 XMIT_OFF
G 2N7002_SOT23 1027 add them for meet Minicard Rev1.1 spec
CH751H-40PT_SOD323-2 S 1224 Delete R470,R471
3

1 2 1212 Move to WLAN

R481 0_0402_5%

New Card Near to Express Card slot.

+1.5VS +3VS_PEC
U25 CONN@
C685 2 1 0.1U_0402_16V4Z 12 11 +1.5VS_PEC JEXP 4.7U_0805_10V4Z
3 1.5Vin 1.5Vout 3
14 1.5Vin 1.5Vout 13
+3VS 1 GND 1 1
USB20_N9 2 C683 C684
28 USB20_N9 USB_D-
C686 2 1 0.1U_0402_16V4Z 2 3 +3VS_PEC USB20_P9 3
3.3Vin 3.3Vout 28 USB20_P9 USB_D+
4 5 EXP_CPPE# 4
C687 2 3.3Vin 3.3Vout CPUSB# 2 2
1 0.1U_0402_16V4Z 1023 change to follow 14" 5 RSV
+3VALW 17 15 +3V_PEC 6 0.1U_0402_16V4Z
AUX_IN AUX_OUT ICH_SMBCLK RSV
15,28,35,39 ICH_SMBCLK 7 SMB_CLK
PLT_RST# 6 19 ICH_SMBDATA 8
7,18,26,31,33,35 PLT_RST# SYSRST# OC# 15,28,35,39 ICH_SMBDATA SMB_DATA +1.5VS_PEC
+1.5VS_PEC 9 +1.5V
SYSON 20 8 PERST# 10
40,41,43,49 SYSON SHDN# PERST# +1.5VS_PEC +1.5V
28,31 ICH_PCIE_WAKE# 11 4.7U_0805_10V4Z
SUSP# WAKE#
34,40,43,46,48,49,50,52 SUSP# 1 STBY# NC 16 +3V_PEC 12 +3.3VAUX
PERST# 13 1 1
@ R485 PERST#
+3VALW 2 1 100K_0402_5% 10 CPPE# GND 7 +3VS_PEC 14 +3.3V
C688 C689
15 +3.3V
EXP_CPPE# 9 CLKREQ#_4 16
28 EXP_CPPE# CPUSB# 15 CLKREQ#_4 CLKREQ# 2 2
EXP_CPPE# 17 CPPE# 0.1U_0402_16V4Z
18 RCLKEN 15 CLK_PCIE_NCARD# 18 REFCLK-
15 CLK_PCIE_NCARD 19 REFCLK+
R5538D001-TR-F_QFN20_4X4~D 20 GND
21
internal pull high to 3.3Vaux-in 28 PCIE_RXN4
28 PCIE_RXP4 22
PERn0
PERp0
23 +3V_PEC
EC need setting at Hi-Z & output Low 28 PCIE_TXN4 24
GND
PETn0
28 PCIE_TXP4 25 4.7U_0805_10V4Z
PETp0
26 GND
1 1
27 C690 C691
GND
28 GND
SANTA_130801-1_26P 2 2
4 0.1U_0402_16V4Z 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 32 of 58
A B C D E
 A B C D E

Card Reader Connector

CONN@
JREAD
need change to low active switch 3 21
+VCC_4IN1 XD-VCC SD-VCC +VCC_4IN1
MS-VCC 28
+VCC_OUT +VCC_4IN1 XD_SD_MS_D0 32
XD_SD_MS_D1 XD-D0 SDCLK
Use 0603 type and over 20 mils 10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_SD_MS_D2 XD_SD_MS_D0
trace width on both side @ 40mil XD_SD_MS_D3
9
8
XD-D2 SD-DAT0 14
12 XD_SD_MS_D1
+3VS U74 XD_D4 XD-D3 SD-DAT1 XD_SD_MS_D2
7 XD-D4 SD-DAT2 30
XD_D5 6 29 XD_SD_MS_D3
+VCC_OUT +VCC_4IN1 XD_D6 XD-D5 SD-DAT3 XD_D4
3 IN OUT 1 5 XD-D6 SD-DAT4 27
4 5 XD_D7 4 23 XD_D5
1 R1553 EN OUT XD-D7 SD-DAT5 XD_D6 1
1 SD-DAT6 18

1
1 2 @ C1333 2 1 @ SDCMD_MSBS_XDWE# 34 16 XD_D7
0_0805_5% GND @ C1334 R1562 XDWP#_SDWP# XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
33 XD-WP SD-CMD 25
1102 Install R1553 1 0.1U_0402_16V4Z G5250C2T1U_SOT23-5 150K_0402_5% XD_ALE 35 1 XDCD0#_SDCD#
XD-ALE SD-CD-SW

1
C1331 C694 2 XD_CD# 40 XD-CD
@ @ 2 XD_RB# XDWP#_SDWP#
39 2

2
C901 R1543 10U_0805_10V4Z 0.1U_0805_50V7M 1U_0603_10V4Z XD_RE# XD-R/B SD-WP-SW
38

2
XDCE# 2 XDCE# XD-RE
2 1 2 1 37 XD-CE
XD_CLE 36 26 MSCLK
100P_0402_25V8K 100_0402_5% XD-CLE MS-SCLK XD_SD_MS_D0
MS-DATA0 17
reserved power circuit 11 15 XD_SD_MS_D1
7IN1 GND MS-DATA1 XD_SD_MS_D2
31 7IN1 GND MS-DATA2 19
24 XD_SD_MS_D3
MS-DATA3 XDCD1#_MSCD#
MS-INS 22
+VCC_4IN1 13 SDCMD_MSBS_XDWE#
MS-BS
41 7IN1 GND
42 7IN1 GND
R1544 1 2 XDWP#_SDWP#
10K_0402_5% TAITW_R015-B10-LM
R1545 1 2 XD_RB#
10K_0402_5% 1109 Do not install R2030
+1.8VS_CR
@ R2030
0.1U_0402_16V4Z 1 2 +1.8VS
1 1 1 1
C892 C1326 C1327 C893 0_0805_5%
Strap pin for JMicro
2 2 2 2
+3VS 1023 JMicro suggest to change 10U_0805_10V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
Power Circuit
R1546 2 1 XD_CLE
2 10K_0402_5% U73 0.1U_0402_16V4Z D46 2
+3VS
R1548 2 1 XD_ALE XDCD1#_MSCD# 2
10K_0402_5% 3 5 1 1 1 XD_CD#
15 CLK_PCIE_CR# APCLKN APVDD
1212 Change XD_ALE to +3VS 4 10 C1328 C692 XDCD0#_SDCD# 3
15 CLK_PCIE_CR APCLKP APV18
1
9 DAN202U_SC70
28 PCIE_TXN5 APRXN 2 2
8 19 C696
28 PCIE_TXP5 APRXP DV33 0.1U_0402_16V4Z 270P_0402_50V7K
DV33 20
XD_RE# 2
R1547 2 1 28 PCIE_RXN5 C693 1 2 0.1U_0402_16V7K PCIE_RXN5_C 11 APTXN DV33 44
200K_0402_5% 28 PCIE_RXP5 C697 1 2 0.1U_0402_16V7K PCIE_RXP5_C 12 18 0.1U_0402_16V4Z +1.8VS_CR
APTXP DV18
DV18 37
R114 2 1 8.2K_0402_5% 7 1 1
+3VS APREXT XD_SD_MS_D0 C1329 C1330
MDIO0 48
1023 JMicro suggest to change 47 XD_SD_MS_D1
4.7K_0402_5% R1555 XIN MDIO1 XD_SD_MS_D2
38 TXIN MDIO2 46
2 2
1 2XDCD0#_SDCD# XOUT 39 45 XD_SD_MS_D3
+3VS TXOUT JMB380 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE#
4.7K_0402_5% R1556 C695 42 SDCLK_MSCLK_XDCE# 0.1U_0402_16V4Z
MDIO5
1 2 XDCD1#_MSCD# 1 2 30 TAV33 MDIO6 41 XDWP#_SDWP#
0.1U_0402_16V4Z 40 XD_CLE
MDIO7 XD_D4
MDIO8 29
1 28 XD_D5
7,18,26,31,32,35 PLT_RST# XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7
R2087 0_0402_5% MDIO11 XD_RE# SDCLK_MSCLK_XDCE# R1550
MDIO12 25 1 2 22_0402_5% SDCLK
@ @ 28 CR_CPPE# 1 2 13 23 XD_RB# R1551 1 2 22_0402_5% MSCLK
R1541 C1325 SEEDAT MDIO13 XD_ALE R1552
14 SEECLK MDIO14 22 1 2 22_0402_5% XDCE#
SDCLK 1 2 1 2
34 TPA1+
100_0402_5% 100P_0402_25V8K D86 XDCD1#_MSCD# TPA1P TPBIAS1 R1554
15 CR1_CD1N TPBIAS_1 35
1 2 XDCD0#_SDCD# 16 36 TREXT 1 2
28 CR_WAKE# CR1_CD0N TREXT 12K_0402_1%
3 CH751H-40PT_SOD323-2 3
APGND 6
1109 Add D86 for card reader wake up +VCC_OUT 17 CR1_PCTLN
use for PWR_EN# TCPS 24
31 TPB1-
@ @ CR_LED# TPB1N TPB1+
21 CR1_LEDN TPB1P 32
R1542 C900 TPA1-
MSCLK 1 2 1 2
8mA sink current TPA1N 33

GND 49
100_0402_5% 100P_0402_25V8K
JMB380-QGAZ0A_QFN48_7X7

White LED: VF=3V, IF = 5mA, Res = 56ohm

CONN@
1009 lower LED power consumption J1394A
+5VS C899 1 2 220P_0402_50V8K R1560 1 2 56_0402_5% TPB1- 1
R1559 TPB-
1 2 56_0402_5% TPB1+ 2 TPB+ GND 5
TPA1- 3 6
TPA- GND
1

R1558 1 2 TPA1+ 4
R1557 4.99K_0402_1% TPA+
470_0402_5% SUYIN_020115FB004SX00ZL
24.576MHz_16P_3XG-24576-43E1 R1561 1 2 56_0402_5%
TPBIAS1 R290 1 2 56_0402_5%
2

C897 1
2 1 XIN C1332
2

22P_0402_50V8J D47 0.33U_0603_16V4Z

1

2
HT-F196BP5_WHITE
1

R134
X2 1M_0402_5%
1 1

4 4
2

C898 Q53 D
2 1 XOUT 2N7002_SOT23-3 2 CR_LED#
G
2

22P_0402_50V8J S
3

R2097
For JM380 4.7K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
JMB380/385 card reader/1394
1212 Change to high active control AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 33 of 58
A B C D E
 A B C D E

1008 Change to +3V

1019 Change Size to 1206 for IDT request CODEC POWER (4.75V)
+3VS_HDA +3VS 0212_Change to +5VALW.
+3VDD_CODEC +3VAMP_CODEC 300mA
R867 R885 R886
+5VALW +VDDA_CODEC
1 2 +3VS 1 2 1 2 +VDDA_CODEC W=40Mil

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z
BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 U28

0.1U_0402_16V4Z

1U_0603_10V4Z
1 1 1 1 0_1206_5% C722 1 2 1
C725 C727 C730 C731 0.1U_0402_16V4Z IN
1 OUT 5
C904 2 1
GND C723
2 2 2 2
32,40,43,46,48,49,50,52 SUSP# 3 SHDN BYP 4
2 2.2U_0805_16V4Z
1 G9191-475T1U_SOT23-5 2 1
1
C732
0208_Change SLP_S3# to SUSP#.
0.1U_0402_16V4Z
2

U56
R2060
+3VDD_CODEC 9 DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 47 1 2 EAPD_CODEC 40
0_0402_5%
1 DVDD_CORE VOL_UP/DMIC_0/GPIO 1 2 DMIC_DAT 17

VOL_DN/DMIC_1/GPIO 2 4
+3VAMP_CODEC 25 AVDD1*
GPIO 3 30
38 AVDD2**
VREFOUT-E / GPIO 4 31

+3VS_HDA 3 43 EAPD_CODEC_R
DVDD_IO GPIO 5 EAPD_CODEC_R 37
32 MONO_OUT GPIO 6 44

45 SPDIF_OUT_DOCK
SPDIF OUT1 / GPIO 7 SPDIF_OUT_DOCK 42
HDA_BITCLK_CODEC 6
27 HDA_BITCLK_CODEC BITCLK
48 SPDIF_OUT
SPDIF OUT0 SPDIF_OUT 19
HDA_SDOUT_CODEC 5
27 HDA_SDOUT_CODEC SDO
R517 1 2 33_0402_5% 8
27 HDA_SDIN0 SDI_CODEC
1106 Add EC_BEEP 28 VREFOUT_B
VREFOUT-B VREFOUT_B 36
HDA_SYNC_CODEC 10
2 27 HDA_SYNC_CODEC SYNC 2
29 +3VAMP_CODEC
HDA_RST#_CODEC VREFOUT-C
27,40 HDA_RST#_CODEC 11 RESET# R523 1 2 5.1K_0402_1%
R2076 47K_0402_5% R526 1 2 20K_0402_1% EXTMIC_DET# 36
1 2 13 SENSE R524 1 2 39.2K_0402_1% JACK_DET# 36,42 1107 Delete R515,R516,C916
40 EC_BEEP SENSE_A
R1528 1 2 22_0402_5% 46 C951 1 2 0.1U_0402_16V4Z
17 DMIC_CLK DMIC_CLK
R520 @ R1599 1 2 10K_0402_1% INTMIC_DET# 36
28 SB_SPKR 1 2 47K_0402_5% C913 2 1 1U_0603_10V4Z 33 CAP2 PORTA_R 41 HP_OUTR
HP_OUTR 36
R521 1
HP Jack & Dock
2 10K_0402_5% C955 1 2 MONO_INR 12 PCBEEP PORTA_L 39 HP_OUTL
HP_OUTL 36 1023 change detection circuit to solve Speaker
0.1U_0402_16V4Z
C956 1 2 0.1U_0402_16V4Z
can not work.
22 MIC_EXT_R
PORTB_R MIC_EXT_R 36
R531 1
40 NC / OTP Jack MIC
+3VAMP_CODEC 2 5.1K_0402_1% PORTB_L 21 MIC_EXT_L
MIC_EXT_L 36
42 SENSE_B# R916 1 2 39.2K_0402_1% SENSEB# 34 SENSE_B / NC
1
C979 37 24 MIC_IN_R
NC PORTC_R MIC_IN_R 36
0.1U_0402_16V4Z MIC_IN_L
Internal MIC
18 NC PORTC_L 23 MIC_IN_L 36
2
19 NC
36 LINE_OUT_R
PORTD_R LINE_OUT_R 36,37
20 NC LINE_OUT_L
Internal SPKR.
PORTD_L 35 LINE_OUT_L 36,37

C744 1 2 VC_REFA 27 15 DOCK_MIC_R_CODEC C2108 2 1 1U_0603_10V4Z R2080 1 2 10K_0402_5%

VREFFILT PORTE_R DOCK_MIC_R 42
10U_0805_10V4Z DOCK MIC
26 14 DOCK_MIC_L_CODEC C2109 2 1 1U_0603_10V4Z R2081 1 2 10K_0402_5%
AVSS1* PORTE_L DOCK_MIC_L 42
42 AVSS2**

2
3 3
PORTF_R 17
7 R1573 R1574
DVSS** 1.21K_0402_1% 1.21K_0402_1%
PORTF_L 16

1
92HD71B7X5NLGXA1X8_QFN48_7X7 1/Av circuit

1106 Change C746,C747,C748,C749 to 1000PF

1107 HP request
@
C746
1 2
1000P_0402_50V7K
@
C747
1 2
1000P_0402_50V7K
@ HDA_BITCLK_CODEC
SENSE A SENSE B C748
1 2
1

1000P_0402_50V7K @
Port Resistor Port Resistor @ R525
C749
1 2 47_0402_5%
1000P_0402_50V7K
2

A 39.2K E 39.2K 1 @
@ R2068 C745
1 2
0_0402_5% 33P_0402_50V8K
2
B 20K F 20K R527
4 4
1 2
0_1206_5%
C 10K G 10K R528
1 2 GNDA 36,37,42
0_1206_5%
D 5.11K H 5.11K
GND GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec_IDT9271B7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 34 of 58
A B C D E
 5 4 3 2 1

MDC 1.5 Conn.

Change type 4/25

CONN@
JP18

1 2 R803 1 2 0_0603_5% +3VS

HDA_SDOUT_MDC GND1 RES0
27 HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
D D
5 GND2 3.3V 6 +3VS
27 HDA_SYNC_MDC HDA_SYNC_MDC 7 8
IAC_SYNC GND3
27 HDA_SDIN1 R529 1 2 HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10
27 HDA_RST#_MDC 33_0402_5% 11 12 HDA_BITCLK_MDC 27
IAC_RESET# IAC_BITCLK

@ R530 @ C751

GND
GND
GND
GND
GND
GND
+3VS 2 1 1 2

ACES_88018-124G 10_0402_5% 10P_0402_25V8K

13
14
15
16
17
18
1000P_0402_50V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 1 1 @ Connector for MDC Rev1.5
C752 C753 C754

2 2 2

Mini Card 1---Robson +3VS_MINI +1.5VS_MINI +3VALW

C C
0.01U_0402_16V7K 4.7U_0805_10V4Z 0.01U_0402_16V7K4.7U_0805_10V4Z

1 1 1 1 1 1 1 @
C759 C760 C761 C755 C756 C757 C758

0.1U_0402_16V7K
2 2 2 2 2 2 2
1226 Add R to +3VALW
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VALW +3VS
@ R2120
1 2
+1.5VS_MINI +3VS_MINI 0_0805_5%
CONN@
JP19 R1565
1 1 2 2 1 2
3 4 0_0805_5%
3 4
5 5 6 6
CLKREQ#_11 7 8 +1.5VS
15 CLKREQ#_11 7 8
9 10 R1566
9 10
15 CLK_PCIE_MCARD1# 11 11 12 12 1 2
13 14 0_0805_5%
15 CLK_PCIE_MCARD1 13 14
15 15 16 16 0903 change from L to R
17 17 18 18
19 19 20 20 0906 Add
R533 0_0402_5% 21 22 PLT_RST#
21 22 PLT_RST# 7,18,26,31,32,33
28 PCIE_RXN2 1 2 PCIE_RX2N_R 23 23 24 24 R469 1 2 0_0402_5% +3VS_MINI
28 PCIE_RXP2 1 2 PCIE_RX2P_R 25 25 26 26 @ R1583 1 2 0_0402_5% +3VALW
R534 0_0402_5% 27 28
27 28
29 29 30 30 ICH_SMBCLK 15,28,32,39
28 PCIE_TXN2 31 31 32 32 ICH_SMBDATA 15,28,32,39
B B
28 PCIE_TXP2 33 33 34 34
35 35 36 36
37 37 38 38
+3VS_MINI 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
49 49 50 50
51 51 52 52

53 GND1 GND2 54
55 GND1 GND1 56 0903 update CIS to H5.2mm
FOX_AS0B226-S99N-7F~D

SP01000P700 S H-CONN ACES 88914-5204 52P P0.8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC 1.5 & Robson
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 35 of 58
5 4 3 2 1
 A B C D E

+5VAMP +5VS
@ R906 0_0402_5%
0906 Change R535 +VDDA_CODEC 1 2 @ C972 1 2
1 2
3/28 from 0_1206_5% 1U_0603_10V4Z

1
1 1
NC7SZ04P5X_SC70-5 C2102 C2101 @ @
R904 R905
change to 2N7002 10U_0805_10V4Z 10U_0805_10V4Z 4.7K_0402_5% 4.7K_0402_5%
U30 2 2 MIC INT In-L

2
14 RS/D RVDD 19
CONN@
R542 1 2 0_0402_5% 9 7 @ JP21
37,40 EC_MUTE# LS/D LVDD C970
INT_MIC_DET# 1
1 MICIN_L 1 1
34 MIC_IN_L 1 2 2 2
C770 1 2 0.1U_0402_16V7K R1530 1 2 16 1 SPKR+ MICIN_R 3
RIN+ ROUT+ 3

1
7.5K_0402_1% @ 22U_0805_6.3VAM 4
C772 1 4
34,37 LINE_OUT_R 2 0.1U_0402_16V7K R946 1 2 17 RIN- ROUT- 3 SPKR- R900
7.5K_0402_1% 0_0603_5% 5
@ GND1
C971 6 GND2
C773 1 2 0.1U_0402_16V7K R1531 1 2 12 4 SPKL+

2
7.5K_0402_1% LIN+ LOUT+ ACES_88231-04001
34 MIC_IN_R 1 2
C1324 1 2 0.1U_0402_16V7K R947 1 2 13 6 SPKL-
34,37 LINE_OUT_L 7.5K_0402_1% LIN- LOUT- 22U_0805_6.3VAM

1224 Change value 15 RBYPASS

NC 20 1108 Change C970,C971 to 22uF
11 LBYPASS
NC 18

1 1 2 GND NC 10
1212 Change to 1uF C775 C765
5 GND NC 8
1U_0805_25V6K +VDDA_CODEC
2 2
0906 Change pin define @

2
TPA6020A2RGWR_QFN20_5x5 Audio & USB board conn +3VS R1597 1 2 @
10K_0402_5% R1596
1U_0805_25V6K 10K_0402_5%
Keep 10 mil CONN@
JP48
width 40 ANA_MIC_DET

1
EXT_MIC_R
1 1

6
EXT_MIC_L
2 2
3 3 HP_OUT_R
34 INTMIC_DET#
4 4

3
HP_OUT_L INT_MIC_DET#
2 5 5 @ Q108B @
2
2
6 6 EXTMIC_DET# Q108A
7 7 EXTMIC_DET# 34

1
HP_DET# 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
8 8 5
9 9
10 10

4
CIR_ IN
11 11 CIR_IN 40,42
12 12 +5VL
13 13
14 14 1023 change to n channel FET to solve Speaker can
ACES_87213-1400G not work.

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

SPEAKER
JP20
SPKL+ 1
B+ SPKL- 1
1023 add R1012 to solve Speaker can 2 2
SPKR+ 3
not work SPKR- 4
3
4
1

34,42 JACK_DET# 1 1 1 1 5 GND1

R1011 @C957 @ C958 @ C959 @ C960 6
330K_0402_5% GND2
3 +3VALW 47P_0402_50V8J ACES_88231-04001 3
2 2 2 2 CONN@
2

1108 Add 0.01uF

1

D Q202
2 47P_0402_50V8J 47P_0402_50V8J
2

G 47P_0402_50V8J
R1007 S 2N7002_SOT23-3
3
2

10K_0402_5% 1
R1012 Q145B C2112
10K_0402_5% 0.01U_0402_16V7K
6 1

5
2N7002DW-7-F_SOT363-6 2
1

C1358
HP_DET# 2N7002DW-7-F_SOT363-6 R1587
2 34 VREFOUT_B 1 2 1 2
Q145A 1107 Add R2082,R2083 0_0402_5%
1U_0603_10V4Z
1

Q147A

1
2N7002DW-7-F_SOT363-6 R2082 40.2_0603_1%
C2103 1 R1588 R1589
+

34 HP_OUTR 6 1 2 1 2 DOCK_LOUT_R 42
100U_6.3V_M 4.7K_0402_5% 4.7K_0402_5%
5

Q147B
2N7002DW-7-F_SOT363-6 R2083 40.2_0603_1% HP OUT For Docking

2
C2104 1
+

34 HP_OUTL 3 4 2 1 2 DOCK_LOUT_L 42
100U_6.3V_M
1U_0603_10V6K
34 MIC_EXT_R
C1359 1 2 EXT_MIC_R
C1346 1 HP_OUT_R C1360 2 EXT_MIC_L
+

2 34 MIC_EXT_L 1
100U_6.3V_M
HP OUT For M/B 1U_0603_10V6K
C1347 1 HP_OUT_L
+

2
100U_6.3V_M
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 36 of 58
A B C D E
 A B C D E

@
R917 1 2 0_0603_5%

1107 Change C980,C984 from 5900p to 0.039u

1107 Change C983,C992 from 1000p to 100p C980 0.027uF_0603_16V
1 2
1107 Change C982 from 5900p to 0.039u +VDDA_CODEC C981
+VREF 1 2

5600P_0402_25V7K
C982 0.039uF_0603_25V C983 1

4
1 2 100P_0402_50V8J U35B R918
5 R919 1 2

P
R920 C984 0.027uF_0603_16V +
OUT 7 1 2
1 R921 2 +VREF 10K_0402_1% 1
1 2 1 2 6 -

G
1 2 30.1K_0402_1% 10K_0402_1%
TLV2464_TSSOP14 +VDDA_CODEC

11
1
+VDDA_CODEC

100P_0402_50V8J
10K_0402_1%
R922 1
10K_0402_1% C985 +VREF
C986 R923 R924

4
1 2 1 2 1 2 U35D

2
34,36 LINE_OUT_R

4
1U_0603_10V4Z 20K_0402_1% U35A 60.4K_0402_1% 2
12

P
C987 C988 + BASS_OUT
3 14

P
C989 R925 + C990 OUT
OUT 1 1 2 1 2 13 -

G
34,36 LINE_OUT_L 1 2 1 2 2 - 1 2

G
1U_0603_10V4Z 20K_0402_1% 0.056uF_0603_16V +VDDA_CODEC 1U_0603_10V4Z TLV2464_TSSOP14

11
+VREF

100P_0402_50V8J
TLV2464_TSSOP14 0.027uF_0603_16V

11
1
C991
1

4
+VREF C992 U35C
2 100P_0402_50V8J R926
10

P
R927 C993 +
OUT 8 1 2
2
1 2 1 2 9 -

G
30.1K_0402_1% 10K_0402_1%
0.027uF_0603_16V TLV2464_TSSOP14

11
1
1224 C987 change from 0.47u to 0.056uF
R928
Change C984, C980, C993, C990 to 0.027uF 10K_0402_1%
R929 @ C994 1 2 0.1U_0402_10V6K
1 2

2
60.4K_0402_1% @ C997 1 2 0.1U_0402_10V6K

@ C998 1 2 0.1U_0402_10V6K
+VDDA_CODEC +VREF R931 1 2 0_0805_5%
2 @ C999 1 2
2 0.1U_0402_10V6K
R930
1 2 @ C1000 1 2 0.1U_0402_10V6K
4.7U_0603_6.3V4Z~D

10K_0603_5%
0.1U_0402_10V6K
1

1 1
R932 C995 C996
10K_0603_5%
2 2 1009 change Subwoofer power circuit
2

C1001 1 2
4.7U_0805_25V6-K

D81 D82
B+ 2 1 2 1 +V_WOOFER
+VDDA_CODEC RLS4148_LL34-2 RLS4148_LL34-2 2 2
C1006 C1007
1107 Change C1008,C1009 to 1UF and no install R936
1U_0805_25V4Z 1U_0805_25V4Z
1

@ 1 1 B+
R934 R935
1107 Add pull down for Sub-Woofer 1K_0402_5% 0_0402_5%

1
+V_WOOFER @
shutdown and EC_MUTE# R936
2

U60 +V_WOOFER 0_0603_5%

3 1U_0603_10V4Z 3
24

2
BASS_OUT VCC C1003 4.7U_0805_25V6K
1 2 1 INN VREF 23 1 2
C1002 0.47U_0402_10V4Z~D 22
BYPASS C1004
1 2 2 INP 1 2 1 1
C1005 0.47U_0402_10V4Z~D 2 2 C1017 C1016
2.2U_0603_106K C1008 C1009 4.7U_0805_25V6K
R937 1 2 3
0_0402_5% GAIN0 220P_0402_50V7K 2 2
@ R938 1 C1010 1 1 1
2 4 GAIN1 COSC 21 2
0_0402_5% 20 1U_0805_25V4Z 1U_0805_25V4Z
ROSC R939 1 2
@ R2084 1 2 0_0402_5% 120K_0402_5%
36,40 EC_MUTE# R2061
34 EAPD_CODEC_R 1 2 0_0402_5% 5 SHUTDOWN
R2063 1 2 8.2K_0402_5% 16
7 VCLAMP
PVCC
PVCC 9 1113 Remove L58,L60 for layout spacing Sub-woofer Connector
1
C1011 14 CONN@
OUTP L57 JP49
OUTP 15 1 2
1U_0603_16V4Z BLM31AJ260SN1L_1206~D 1
2 L59 1
OUTN 10 1 2 2 2
R941 1 2 8 11 BLM31AJ260SN1L_1206~D
51_0402_5% BSN OUTN
1 1 3 GND
2

R942 1 2 17 C1012 C1013 4

51_0402_5% BSP BAT54AW_SOT323-3~D GND
ACES_88231-02001
1 1 6 4700P_0402_25V 2 2 4700P_0402_25V
C1014 C1015 PGND D38
18 AGND PGND 12
19 13
1

0.22U_0402_10V4Z 0.22U_0402_10V4Z AGND PGND

2 2

HPA00304PWR_TSSOP24
4
1108 Change to dual package
Need check 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EQ & Sub Woofer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 37 of 58
A B C D E
 5 4 3 2 1

Left side USB Connector Left side ESATA/USB combination Connector

+5VALW USB_VCCC
CONN@
USB_VCCC JP25
1023 change to follow 14" USB
U32 CONN@ 1
JP27 B_VCC
1 GND OUT 8 W=60mils 28 USB20_N2 2 B_D-
2 IN OUT 7 1 VCC 28 USB20_P2 3 B_D+
3 IN OUT 6 1 28 USB20_N10 2 D- 4 B_GND

150U_D_6.3VM

0.1U_0402_16V4Z

1000P_0402_50V7K
1 4 EN# OC# 5 1 1 28 USB20_P10 3 D+
C787 + C786 C788 C789 4 5
D TPS2061IDGNR_MSOP8 GND SATA_TXP5 GND D
27 SATA_TXP5 6 A+
4.7U_0805_10V4Z 5 SATA_TXN5 7 ESATA
2 2 2 2 GND 27 SATA_TXN5 A-
1023 change to follow 14" 6 GND 8 GND SHIELD 12
7 C784 2 1 0.01U_0402_16V7KSATA_RXN5 9 13
GND 27 SATA_RXN5_C B- SHIELD
8 C785 2 1 0.01U_0402_16V7KSATA_RXP5 10 14
GND 27 SATA_RXP5_C B+ SHIELD
11 GND SHIELD 15
USB_EN# SUYIN_020173MR004M598ZL
TYCO_1759576-1
@
R561 1 2 10K_0402_5% +5VALW D22 @ D15
+5VALW 4 2 USB20_P10 +5VALW 4 VIN 2 SATA_TXP5
VIN IO1 IO1
USB20_N10 3 1 SATA_TXN5 3 1
IO2 GND IO2 GND
PRTR5V0U2X_SOT143-4 PRTR5V0U2X_SOT143-4

@ D84 @ D85
1023 change to follow 14" +5VALW 4 VIN 2 SATA_RXP5 +5VALW 4 VIN 2 USB20_P2
IO1 IO1
SATA_RXN5 3 1 USB20_N2 3 1
IO2 GND IO2 GND
PRTR5V0U2X_SOT143-4 PRTR5V0U2X_SOT143-4

USB cable connector for Right side Touch screen connector 1020 change to meet correct power rail
+5VS CONN@
JP26
C CONN@ C
1 1
JP43 2
28 USB20_N11 2
+5VALW 1 1 28 USB20_P11 3 3
2 4
3
2
3 5
4
5
5P connector
USB_EN# 4 1023 change to follow 14" 6
4 GND1
28 USB20_N0 5 5 7 GND2
28 USB20_P0 6 6
7 ACES_88266-05001
7
28 USB20_N1 8 8
9 11 1023 change to follow 14" @ D18
28 USB20_P1 9 G11 USB20_P11
10 10 G12 12 +5VS 4 VIN IO1 2

1023 change to follow 14" ACES_87213-1000G USB20_N11 3 1

IO2 GND
PRTR5V0U2X_SOT143-4

Finger printer BT Connector

CONN@
JP30
1212 Add soft start circuit 1 1 +3VAUX_BT
B
20070209 Add for FPR 2 2 B
USB20_P6_R R567 1 0_0402_5%
@ R698 3 3 USB20_N6_R
2 USB20_P6 28
1 2 0_0603_5% 4 4
R568 2 1 0_0402_5% USB20_N6 28
@ Q34 +3VS 5 5 @ R569 1 1K_0402_5%
BT_LED 41
R653 6 6 @ R570 1
2
1K_0402_5% CH_DATA 32
7 7 2 CH_CLK 32
S

+3VALW 3 1 1 2 8 8
0_0603_5% 0612 no install
GND1 9
@ C2121
2
SI2301BDS_SOT23
1
C835 GND2 10 @ D25
G
2

0.1U_0402_16V4Z ACES_88231-08001 +5VALW 4 VIN 2 USB20_P6_R

@ R2113 0.1U_0402_16V4Z IO1
47K_0402_5% 1 2 USB20_N6_R 3 IO2 GND 1
1 2 CONN@ 1212 BT issue, change circuit
40 USB_EN#
JP41 PRTR5V0U2X_SOT143-4
1 1
R654 1 2 0_0402_5% USB20_N7_R 2 +3VALW +3VS
28 USB20_N7 2
R655 1 2 0_0402_5% USB20_P7_R 3
28 USB20_P7 3 +3VAUX_BT
4 R2112 0_0603_5%
4
3

5 1 2 Q24 SI2301BDS_SOT23
5
1023 change to follow 14" 1 2 6 6

S
@ @ R582

D
7 GND 1 2 3 1
D33 0_0603_5% 8 @ R572 0_0603_5%
PACDN042_SOT23-3~D GND
ACES_85201-06051

G
1 1 1
1

2
1
1 2 C791 C792 C793
C790 R2114
1107 Change FPR pin assignment 1U_0603_10V4Z 100K_0402_5% 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
C794 2 2 2
2 1

2
0.1U_0402_16V4Z

A A
28 BT_OFF 1 2
R574 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 38 of 58
5 4 3 2 1
 5 4 3 2 1

1113 EC request
LPC Debug
+3VL +3VALW
1008 Change power rail
SPI ROM Port Change from +3VL to +3VS. 6/9
+3VL

2
@ R2091 R2092 U33
Removed +3VS. 6/13
0_0402_5% 0_0402_5% 20mils 8 4
VCC VSS
1
C796 3 B+

1
0.1U_0402_16V4Z W
7 CONN@
D 2 HOLD JP32 D
R576 1 2 SPI_FSEL# 1 1
40 FSEL# S Ground

1
1 0_0402_5% 2
15 CLK_DEBUG_PORT1 LPC_PCI_CLK
C795 R575 R577 1 2 SPI_CLK_R 6 3
40 SPI_CLK C Ground
100K_0402_5% 0_0402_5% 4
27,32,40 LPC_FRAME# LPC_FRAME#
0.1U_0402_16V4Z 40 FWR# R578 1 2 SPI_FWR# 5 2 SPI_SO 1 2 FR D# FRD# 40 5
2 U34 0_0402_5% D Q R579 0_0402_5% +V3S
26,40 PCI_RST# 6

2
WIESON G6179 8P SPI LPC_RESET#
8 VCC A0 1 7 +V3S
7 WP A1 2 SP07000F500 S SOCKET WIESON G6179-100000 8P 27,32,40 LPC_AD0 8 LPC_AD0
6 3 SPI_CLK_R 9
40,41,45 SMB_EC_CK1 SCL A2 SPIFLASH 27,32,40 LPC_AD1 LPC_AD1
40,41,45 SMB_EC_DA1 5 SDA GND 4 1 27,32,40 LPC_AD2 10 LPC_AD2
C798 WIESO_G6179-100000_8P 11
27,32,40 LPC_AD3 LPC_AD3
AT24C16AN-10SI-2.7_SO8 12
10P_0402_25V8K ON/OFFBTNLED# VCC_3VA
13 PWR_LED#
2
14 CAPS_LED#
15 NUM_LED#
1
VCC1PWRGD 16
R580 SPI_CLK_JP52 VCC1_PWRGD
100K_0402_5%
Connect pin3 & 23 SPI_CS#_JP52
17 SPI_CLK
18 SPI_CS#
together and pin 24 SPI_SI_JP52 19
SPI_SO_JP52 SPI_SI
to GND in 6/29. 20
2

SPI_HOLD#_0 SPI_SO
21 SPI_HOLD#
22 Reserved
23 Reserved
24 Reserved

ACES_87216-2404_24P

C C

SPI_CLK 1 2 SPI_CLK_JP52
@ R584 0_0402_5%

FSEL# 1 2 SPI_CS#_JP52
@ R586 0_0402_5%

Acceleromter-1 +3VALW FWR# 1

@ R587
2
0_0402_5%
SPI_SI_JP52

R889 1 2 HOLD# 1 2 SPI_HOLD#_0

3.3K_0402_5% @ R588 0_0402_5%
+3VS +3VS_ACL +3VS_ACL_IO
FR D# 1 2 SPI_SO_JP52
@ R590 0_0402_5%
D45 R1535
2 1 1 2 ON/OFFBTN_LED# 1 2 ON/OFFBTNLED#
0_0603_5% 40,41 ON/OFFBTN_LED# @ R591 0_0402_5%
CH751H-40PT_SOD323-2
VCC1_PW RGD 1 2 VCC1PWRGD
+3VS_ACL 40 VCC1_PWRGD @ R592 0_0402_5%

U72
LIS302DL
1 1
+3VS_ACL 1 C1321 C1322
VDD_IO
+3VS_ACL_IO 6 VDD GND 2
4 0.1U_0402_16V4Z 10U_0805_6.3V6M
GND 2 2
26 PCI_PIRQH# 8 INT 1 GND 5
9 INT 2 GND 10
B B
12 SDO
15,28,32,35 ICH_SMBDATA 13 SDA / SDI / SDO
15,28,32,35 ICH_SMBCLK 14 R1539
SCL / SPC
RSVD 3 1 2 +3VS_ACL_IO
+3VS_ACL R1538 2 1 7 11 0_0603_5%
10K_0402_5% CS RSVD
LIS302DLTR_LGA14_3X5~D

Must be placed in the center of the system.

U72 & U77 must be close

Acceleromter-2 need to update CIS

@
U77
BMA150 9
VDDIO +3VS_ACL_IO
PCI_PIRQH# 4 2 +3VS_ACL
INT VDD
@ 10K_0402_5%
+3VS_ACL R2052 1 2 G_CS# 5 3
CSB GND
A ICH_SMBDATA A
6 SCK RSVD 1
RSVD 10
7 SDO
ICH_SMBCLK 8 11
SDI RSVD
RSVD 12

BMA150_LGA12
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 39 of 58
5 4 3 2 1
 +3VL_EC

0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 BATT_OVP
C809 C810 C811 C812 C813
+3VL +3VL_EC +EC_AVCC
1000P_0402_50V7K 2
2 2 2 2 2 R603 C829
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 0_0805_5%
100P_0402_50V8J
1
1212 Change to +3VL

111
125
+3VL +3VS

22
33
96

67
9
U37
SMB_EC_DA1 R605 1 2 4.7K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R606 1 2 4.7K_0402_5% 1106 Add EC_BEEP
SMB_EC_DA2 R607 1 2 4.7K_0402_5%
SMB_EC_CK2 R608 1 2 4.7K_0402_5%
GATEA20 1 21 INV_PWM R1630
27 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 17
KB_RST# 2 23 FAN_PWM 1 2 +3VL
27 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM 4
1025 Add Pull SIRQ 3 26 EC_BEEP 10K_0402_5%
28 SIRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP 34
@ @ LPC_FRAME# 4 27 ACOFF
up for GPI C815 R609
27,32,39 LPC_FRAME#
LPC_AD3 5
LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 46,47
100P_0402_50V8J
27,32,39 LPC_AD3 LAD3
1 2 1 2 27,32,39 LPC_AD2 LPC_AD2 7 PWM Output C816 2 1 ECAGND D53
33_0402_5% LPC_AD1 LAD2 BATT_TEMP AC_IN
27,32,39 LPC_AD1 8 LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP 45 2 1 ACIN 46
15P_0402_50V8J LPC_AD0 BATT_OVP
27,32,39 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 45
CH751H-40PT_SOD323-2
ADP_I/AD2/GPIO3A 65 ADP_I 46
CLK_PCI_EC 12 AD Input 66 ADP_ID 2
15 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_ID 45
PCI_RST# 13 75 TP_BTN# C822 1009 change
26,39 PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 TP_BTN# 41
+3VL R610 1 2 ECRST# 37 76 ANA_MIC_DET
47K_0402_5% EC_SCI# 20
ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET 36
100P_0402_50V8J diode D53
28 EC_SCI# SCI#/GPIO0E 1
27,34 HDA_RST#_CODEC 1 2 38 CLKRUN#/GPIO1D
direction
R2067 0_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 17
C817 2 1 1102 Change HAD_RST#_CODEC 70 VCTRL
EN_DFAN1/DA1/GPIO3D VCTRL 46
1

0205_Add Pull 0.1U_0402_16V4Z J1 from KBC pin 36 to pin 38 DA Output 71 IR EF

KSI0 IREF/DA2/GPIO3E AC_SET IREF 46
55 72
down R402 for JOPEN 1105 Add resistor KSI1 56
KSI0/GPIO30 DA3/GPIO3F AC_SET 46
2

KSI1/GPIO31
SUSP#. KSI2 57 KSI2/GPIO32
+5V
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 36,37
1102 Change R615 to 8.2k ohm add pull down on SYSON KSI4 59 84 USB_EN# R614 1 2 4.7K_0402_5%
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 38
KSI5 60 85 I2C_INT R617 1 2 4.7K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C MUTE_LED I2C_INT 41
+3VALW
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 MUTE_LED 42
SUSP# KSI7 62 87 TP_CLK
PCI_RST# KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 41
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 41
KSO1 40 @ R2077 0_0402_5%
KSO1/GPIO21
1

KSO2 41 1 2 @ R616 1102 For C0 -- R616 no stuff

KSO2/GPIO22 ISOLATEB 28,31
1
KSO3 42 97 1 2
8.2K_0402_5% KSO3/GPIO23 SDICS#/GPXOA00
1

R619 KSO4 43 98 DOCK_VOL_UP# 4.7K_0402_5% Select SPI ROM or LPC

R615 R618 100K_0402_5% KSO5 KSO4/GPIO24 SDICLK/GPXOA01 DOCK_VOL_DWN# DOCK_VOL_UP# 42
10K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 DOCK_VOL_DWN# 42 ROM SPI_CLK
45 KSO6/GPIO26 Matrix 109
2

KSO7 SDIDI/GPXID0
46 SPI Device Interface
2

KSO8 KSO7/GPIO27 R643

0214_Add Pull high 47
2

KSO9 KSO8/GPIO28 FR D# TP_BTN#

48 119 2 1 +3VS 2
SYSON resistor for LID_SW# and KSO10 49
KSO9/GPIO29 SPIDI/RD#
120 FWR#
FRD# 39
10K_0402_5% C828
KSO10/GPIO2A SPIDO/WR# FWR# 39
WL_BTN#. LID_SW# KSO11 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK
SPI_CLK 39
KSO12 51 128 FSEL# 15P_0402_50V8J
KSO12/GPIO2C SPICS# FSEL# 39
1

KSO13 1
52 KSO13/GPIO2D
KSO14 53
8.2K_0402_5% KSO15 KSO14/GPIO2E CIR_ IN
R2062
1114 R620 no stuff, SB internal pull up 54 KSO15/GPIO2F CIR_RX/GPIO40 73 CIR_IN 36,42
1212 Change power rail to +3VALW KSO16 81 74 VCC1_PW RGD R642
KSO16/GPIO48 CIR_RLC_TX/GPIO41 VCC1_PWRGD 39
KSO17 82 89 FSTCHG CIR_ IN 2 1 +5VL
FSTCHG 46
2

+3VALW KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 STD_ADP 10K_0402_5%

BATT_CHGI_LED#/GPIO52 90 STD_ADP 46
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 41
SMB_EC_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BAT_LED#
39,41,45 SMB_EC_CK1 SCL1/GPIO44 BAT_LED# 41
2

SMB_EC_DA1 78 93 ON/OFFBTN_LED# 1104 Change power rail from +3VL to +5VL

39,41,45 SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# 39,41
R620 SMB_EC_CK2 79 SM Bus 95 SYSON
4,20 SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 32,41,43,49
10K_0402_5% SMB_EC_DA2 80 121 VR_ON
4,20 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 51
AC_IN
AC_IN/GPIO59 127
2 1
For EMI
1

R621 10K_0402_5% @ CP1

SLP_S3# 6 100 EC_RSMRST# KSO14 1 8
28 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 28
SLP_S5# 14 101 R622 1 2 KSO11 2 7
28 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 28
@ R624 EC_SMI# 15 102 EC_ON 0_0402_5% KSO10 3 6
28 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 47
1 2 EC_PME# LID_SW# 16 103 WL_BLUE_LED# 1025 add to solve S4 can not work KSO15 4 5
26 PCI_PME# +3VL 41 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 WL_BLUE_LED# 41
0_0402_5% ESB_CLK 17 104 PM_PWROK
41 ESB_CLK
ESB_DAT 18
SUSP#/GPIO0B
GPO
ICH_PWROK/GPXO06
105 BKOFF# PM_PWROK 7,28 issue 100P_1206_8P4C_50V8
41 ESB_DAT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 17
EC_PME# 19 GPIO 106 M_PWROK @ CP2
EC_PME#/GPIO0D WL_OFF#/GPXO09 M_PWROK 7,28 17" INT_KBD
1

EC_THERM 25 107 TP_LED# KSO6 1 8

R630 CONA# EC_THERM#/GPIO11 GPXO10 LAN_DSM#_KBC TP_LED# 41 KSO3
28 108 2 7
4.7K_0402_5%
42 CONA#
UTX
29
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
GPXO11 LAN_DSM#_KBC 31
CONN.( TYPE "D" KSO12
KSO13
3 6
30 EC_TX/GPIO16 4 5
LANPWR#_R 31 110 SLP_S4#
SLP_S4# 28 KB) CONN@
2

ON/OFF EC_RX/GPIO17 PM_SLP_S4#/GPXID1 ENABLT JP34 100P_1206_8P4C_50V8

1106 Change LANPWR to KBC pin31 41 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENABLT 20
R543 1 2 0_0402_5% 34 114
42 DOCK_SLP_BTN# PWR_LED#/GPIO19 GPXID3 EAPD_CODEC 34
DIM_LED 36 GPI 115 THERM_SCI# KSO17 1 @ CP3
43 DIM_LED NUMLED#/GPIO1A GPXID4 THERM_SCI# 20,28 1
R2078 116 SUSP# KSO16 2 KSO2 1 8
LANPWR#_R GPXID5 PWRBTN_OUT# SUSP# 32,34,43,46,48,49,50,52 KSO15 2 KSO4
31 LANPWR# 1 2 GPXID6 117 PWRBTN_OUT# 28 3 3 2 7
0_0402_5% C RY1 118 NMI_DBG# KSO10 4 KSO7 3 6
C RY2 GPXID7 KSO11 4 KSO8
122 XCLK1 5 5 4 5
@ R455 C RY1 123 124 KSO14 6
EC 1 2 C RY2 XCLK0 V18R
2 1 KSO13 7
6
7
100P_1206_8P4C_50V8
AGND

C821 C2118 KSO12 8 @ CP4

GND
GND
GND
GND
GND

DEBUG
@
JP35 @
10M_0402_5%
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
KSO3
KSO6
9
8
9
KSO0
KSI2
1 8
1 1 10 10 2 7
1 2
port1 1
R2079 0_0402_5%
+5VL
C551 C584 KB926QFB0_LQFP128_14X14 KSO8 11 KSI3 3 6
11
24
35
94
113

69

URX 1 +3VL_EC 11
2 2 2 LANPWR#_R KSO7 12 12
KSO5 4 5
3 UTX 15P_0402_50V8J 15P_0402_50V8J KSO4 13
3 13
1

2 2 KSO2 100P_1206_8P4C_50V8
ECAGND

4 4 14 14
1

+EC_AVCC 1212 For C KSI0 15

OSC

OSC

ACES_85205-0400 Y4 L42 KSO1 15 @ CP5

16 16
32.768KHZ_12.5PF_9H03200413 0_0603_5% Revision KSO5 17 1 8
KSI3 17
18 18 2 7
L43 KSI2 KSO1
NC

NC

1019 change to 19 3 6
2

KSO0 19 KSI0
1 2 1 2 20 4 5
meet ME limit C820 0.1U_0402_16V4Z 0_0603_5% R1629 10K_0402_5% KSI5 21
20
2

+3VL KSI4 21 100P_1206_8P4C_50V8

1 2 +3VL 22 22
+3VS KSO9 23
ESB_CLK R639 23
1 2 4.7K_0402_5% 1212 Change power rail to +3VS KSI6 24 24
@ CP6
ESB_DAT R638 1 2 4.7K_0402_5% D52 KSI7 25 27 KSI1 1 8
25 G1
1

1025 Add Pull up NMI_DBG# 1 2 KSI1 26 28 KSI7 2 7

PCI_SERR# 26 26 G2
R625 KSI4 3 6
for ESB channel 10K_0402_5% CH751H-40PT_SOD323-2 KSI5 4 5
@ R2116 @ C2123 ACES_85201-26051
ESB_CLK 2 1 2 1 0908 SWAP 100P_1206_8P4C_50V8
2

EC_THERM
33_0402_5% 15P_0402_50V8J
1

R623 C

ESB_DAT
@ R2117 @ C2124
4,7,27 H_THERMTRIP# 1 2
10K_0402_5%
2
B
Q5 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 2 1 MMBT3904_NL_SOT23-3 Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
E
EC KB926/KB Conn.
3

33_0402_5% 15P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1225 Add R,C for EMI DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 40 of 58
 A B C D E

LED +3VS WL_BLUE_LED# 40

6
1009 lower LED power consumption 2N7002DW-7-F_SOT363-6
Q114A +3VS
White

3
D35 R1534 47K Q115 2
Cap Lock 38 BT_LED

1
40 CAPS_LED# 1 2 1 2 +5VS_LED
R2098

1
1
HT-F196BP5_WHITE 470_0402_5% 2 10K 10K_0402_5%
32 WL_LED#
R505
1 100K_0402_5% 1

2
DTA114YKAT146_SOT23-3
White

2
D28 R648 1212 Add R2098 for LED
System status LED

1
ON/OFFBTN_LED# 1 2 1 2 +5VALW_LED

3
HT-F196BP5_WHITE 470_0402_5%

WL_LED 2N7002DW-7-F_SOT363-6
White 5
Q114B
D34 R631 Battery Charge LED

4
40 BAT_LED# 1 2 1 2 +5VALW_LED

1
HT-F196BP5_WHITE 470_0402_5% R506
100K_0402_5%

2
D29
White
White
1 2 R633 1 2
27 SATA_LED# 820_0402_5%
+5VS_LED
HDD LED
R667 1 2 3 4 R2031 1 2 +3VS
28 GPIO19 0_0402_5% 470_0402_5%
AMBER 1009 lower LED power consumption
Amber QSMF-C16E_AMBER-WHITE
SWITCH BOARD. 1224 Add Cap
2
1025 change to follow IBT00 design +3VL 2
1102 Change GSENSOR LED control pin from SB to KBC 1009 Remove double pull up resisters
1106 Delete R668, control by SB
1
C2122
4.7U_0805_10V4Z
2

+5VS_LED CONN@
for debug only JP38
1 1
1212 Delete SW5,SW6 2 2
39,40 ON/OFFBTN_LED# 3 3
R652 1 2@ 0_0402_5% CAP_CLK 4
40 ESB_CLK 4
R641 1 2@ 0_0402_5% CAP_DAT 5
40 ESB_DAT 5
R644 1 2 0_0402_5% 6
39,40,45 SMB_EC_CK1 40 I2C_INT 6
R646 1 2 0_0402_5% +5VALW_LED 1 2 7
39,40,45 SMB_EC_DA1 7
R705 150_0402_5% 8
40 LID_SW# 8
Updated @1029 40 ON/OFF 1 2 9 9
10 10

1
1K_0402_5% 11 GND

2
10K_0402_5% R666 12
R640 GND
ACES_85201-1005N
1025 change Capactivity board pin defination

2
@ D83 PJDLC05_SOT23~D

1
3
K/B backlight 3

1212 Change TP power rail to +5VALW

CONN@
JP51 R2059
T/P Board (Inculde T/P_ON/OFF)
1 1 2 1212 EMI request +5VALW +5V
1 +5VS_LED Q29
2 0_0805_5%
2 +5V TP_BTN# TP_DATA SI2301BDS-T1-E3_SOT23-3
5 G1 3 3
6 4 TP_LED# TP_CLK
G2 4

D
3 1

2
ACES_85201-04051 1 @
C824 D87 D31

G
PSOT24C_SOT23-3 PSOT24C_SOT23-3

2
0.1U_0402_16V4Z @ @ R645
CONN@ 2 10K_0402_5%
JP33

1
1 1

2
2 2 +5VS_LED
3 3
4 4 TP_CLK 40
5 5 TP_DATA 40

1
TP_BTN# D
6 6 TP_LED#
TP_BTN# 40
SYSON Q31
7 7 TP_LED# 40 32,40,43,49 SYSON 2
G 2N7002_SOT23-3
8 8
GND 9 1 1 S

3
@ @
GND 10 C825 C826
ACES_85201-08051 100P_0402_50V8J 100P_0402_50V8J
2 2
4 0226_Change package from 0603 to 0402. 4
SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0
ACES_85201-0405N_4P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD, ON/OFF, SW, CIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 41 of 58
A B C D E
 DOCKVIN
DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off Atlas/ Saturn Dock
CONN@ 1
2.5V = Notebook S3, Dock on DOCKVIN JP40 C827

4V = Notebook S0, Dock on 43 43

1000P_0402_50V7K
2
44 44
+5VS
D43
R589 1 2 1K_0402_5% 2 GREEN 40 39
16 GREEN 40 39
1 DOCK_PW RON RED 38 37
16 RED 38 37
3 D_DDCDATA 36 35
16 D_DDCDATA 36 35
BLUE 34 33
+3VALW 16 BLUE 34 33
DAN202U_SC70 D_HSYNC 32 31 1009 Add pull up
16 D_HSYNC 32 31 +3VS
D_DDCCLK 30 29 CIR_ IN
16 D_DDCCLK 30 29 CIR_IN 36,40
R585 1 2 1K_0402_5% 28 27 DOCK_PW RON
28 USB20_N3 28 27
D_ VSYNC 26 25 MUTE_LED MUTE_LED 40
16 D_VSYNC 26 25
24 23 DOCK_SLP_BTN#
24 23 DOCK_SLP_BTN# 40
22 21 JACK_DET# DOCK_VOL_UP# R594 2 1 10K_0402_5%
28 USB20_P3 22 21 JACK_DET# 34,36
2 31 RJ45_MIDI3+
RJ45_MIDI3+ 20 20 19 19 R_VOL_UP# R649 1 2 200_0402_5% DOCK_VOL_UP# 40
1

D R593 RJ45_MIDI3- R_VOL_DWN# R650 1

31 RJ45_MIDI3- 18 18 17 17 2 200_0402_5% DOCK_VOL_DWN# 40 DOCK_VOL_DWN# R595 2 1 10K_0402_5%
2 10K_0402_5% RJ45_MIDI2+ 16 15 SPDIFO_L
43,50 SYSON# 31 RJ45_MIDI2+ 16 15
G RJ45_MIDI2- 14 13 AUDIO_OGND
31 RJ45_MIDI2- 14 13
S RJ45_MIDI1+ 12 11 DOCK_LOUT_R DOCK_LOUT_R 36
31 RJ45_MIDI1+
3

Q36 RJ45_MIDI1- 12 11 DOCK_LOUT_L

31 RJ45_MIDI1- 10 10 9 9 DOCK_LOUT_L 36
2N7002_SOT23-3 RJ45_MIDI0+ 8 7 DOCK_MIC_R_C
31 RJ45_MIDI0+ 8 7
RJ45_MIDI0- 6 5 DOCK_MIC_L_C
31 RJ45_MIDI0- 6 5
4 3 AUDIO_IGND
+V_BATTERY 4 3 DOCK_PRESENT
2 2 1 1
PJP3

1
1 2 41 45 R804 +1.5VS
B+ 41 SHIELD
42 46 2K_0402_5%
42 SHIELD
PAD-OPEN 2x2m

2
1112 Change power rail from +3VALW to +3VL @

2
FOX_QL1122L-H212AR-7F R1621

33_0402_5%
+3VL
need change to reverse type connector

1 1
@ C C894 R647 220_0402_5%
2

Q112 2 1 2 1 2 SPDIF_OUT_DOCK 34
R62 MMBT3904_NL_SOT23-3 B
10K_0402_5% E 0.1U_0402_16V7K

3
R1622

1
1212 Change value SPDIFO_L 1 2 1
1

0_0402_5% C895 R651

CONA# 40

1
DOCK_LOUT_R DOCK_MIC_R 1 220P_0402_25V8J 110_0402_5%
1

R1570 D DOCK_LOUT_L DOCK_MIC_L C902 R805 2

2
DOCK_PRESENT 1 2 2 1 1 1 1 2K_0402_5%

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
G Q14 1000P_0402_50V7K

2
22_0402_5% S 2N7002_SOT23-3 2
3
1

C942

C943

C923

C924
R61 2 2 2 2
2K_0402_5%
2

Need 600 Ohm 500 mA

R_VOL_UP# R_VOL_DWN# MIC_Dock L56
1 1 FBM-11-160808-601-T_0603
C830 C831 34 DOCK_MIC_R 1 2 DOCK_MIC_R_C

1000P_0402_50V7K 1000P_0402_50V7K 34 DOCK_MIC_L 1 2 DOCK_MIC_L_C

2 2 L55
FBM-11-160808-601-T_0603
1107 Delete C976,C977
1 1
C921 C922

220P_0402_50V7K 2 2 220P_0402_50V7K

1009 Remove TV components +3VS

SENSE_B# 34

1
+3VS
R915

6
10K_0402_5%

2
R914 2 Q100A
10K_0402_5% 2N7002DW-7-F_SOT363-6

1
2
5 Q100B
2N7002DW-7-F_SOT363-6

4
1
R912 10K_0402_5% C
DOCK_MIC_L_C 1 2 2 Q15
B

2
1 E MMBT3904_NL_SOT23-3

3
C978
R913
47K_0402_5% 1U_0603_10V6K
2

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 42 of 58
 5 4 3 2 1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer DIMM LED

B+ +5VALW +5VS B+ +3VALW +3VS
+5VALW +5VALW_LED
U39 U40 Q66
8 D SI2301BDS-T1-E3_SOT23-3
S 1 8 D S 1

1
1 7 D S 2 1 7 D S 2
1

S
C841 R656 C836

D
6 D S 3 6 D S 3 3 1
R2099 5 D 4 1 1 5 D 4 1 1
D 10U_0805_10V4Z G C837 C838 330K_0402_5% 10U_0805_10V4Z G C839 C840 D
1

1
330K_0402_5% 2 AO4466_SO8 2 AO4466_SO8 C905

G
2

2
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z R877 0.1U_0402_16V4Z
2

2 2 2 2 10K_0402_5%
RUNON 2

2
RUNON_5VS R657

6
470_0402_5% DIM_LED#
3

@ R2100 Q89A

2
Q89B

1
470_0402_5% SUSP D
2 1
SUSP 5 C842 DIM_LED 2 Q97
40 DIM_LED
2

1 1212 For power sequence 2N7002DW-7-F_SOT363-6 G 2N7002_SOT23-3

1
2N7002DW-7-F_SOT363-6 @ C2119 0.01U_0402_16V7K S
4

3
2
0.01U_0402_16V7K
2

1009 Add for LED power

+1.8V to +1.8VS Transfer +5VS
Q18
+5VS_LED

SI2301BDS-T1-E3_SOT23-3
+1.8V +1.8VS +5VL +5VL

D
3 1
U59

1
8 1 220U_6.3VM_R15 1
C D S R658 R659 C294 C

G
7 2

2
D S
6 D S 3 1
1 5 4 1 1 100K_0402_5% 100K_0402_5% 0.1U_0402_16V4Z
C963 D G C961 + C1618 C962 2

2
AO4466_SO8 42,50 SYSON# SYSON# SUSP SUSP 50
10U_0805_10V4Z DIM_LED#
2 2 2 2

3
Q96A Q96B 1212 Delete Q97B,R211
0.1U_0402_16V4Z 10U_0805_10V4Z

R1932 SYSON 2 5 SUSP#

32,40,41,49 SYSON SUSP# 32,34,40,46,48,49,50,52
RUNON 1 2 +1.8VS_ON
150K_0402_1% 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6

4
1
C2100
D78
1 2 0.1U_0402_16V4Z
2
H38 H37 H36
1SS355_SOD323-2
HOLEA HOLEA HOLEA

1
1212 Outline modify

H1 H2 H3 H5 H6 H7 H8 H9 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

B B

1
H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
Discharge circuit

1
+5VS +3VS +1.8V +1.5VS +VCCP +0.9V +1.8VS
1

1
R660 R661 R662 R663 R664 R665 R697
H21 H22 H23 H24 H25 H26 H27 H28 H29
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% HOLEA HOLEA HOLEA HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC
2

1
6

Q93A Q93B Q94A Q94B Q95A Q95B Q99

1
D
SUSP 2 SUSP 5 SYSON# 2 SUSP 5 SUSP 2 SUSP 5 SUSP 2 H31 H32
G HOLEA HOLEA H33 H34 H35
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 S HOLEA HOLEA HOLEA
1

2N7002_SOT23-3 3
FM1 FM2 FM3 FM4

1
1 1 1 1

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 43 of 58
5 4 3 2 1
 5 4 3 2 1

@ R2104
1 2
0_0402_5% 1212 Add 0 ohm
L70
HDMI_CLK- 1 2 HDMI_R_CLK-
19 HDMI_CLK- 1 2

19 HDMI_CLK+
HDMI_CLK+ 4 4 3
WCM-2012-900T_0805
3 HDMI_R_CLK+
HDMI Connector +5VS

@ R2105
1 2
1009 update correct CIS & P/N
0_0402_5%

1
@ R2106

2
1 2 D79
D 0_0402_5% BAT54AW_SOT323-3~D D41 D
L71
HDMI_TX0- 1 1 HDMI_R_TX0-
19 HDMI_TX0- 2 2 RB411D T146 _SOT23-3

1
HDMI_TX0+ 4 3 HDMI_R_TX0+
19 HDMI_TX0+ 4 3

2
WCM-2012-900T_0805 R1036 R1035
@ R2107 +5VS 2.2K_0402_5% 2.2K_0402_5%
1 2 CONN@
0_0402_5% JHDMI

1
@ R2108 0.1U_0402_16V4Z HDMI_HPD 19 HP_DET
1 2 18 +5V

2
0_0402_5% 1 2 17
L72 C1348 C1349 HDMIDAT DDC/CEC_GND
16 SDA
HDMI_TX1- 1 1 HDMI_R_TX1- R1571 R1572 HDMICLK
19 HDMI_TX1- 2 2 0.1U_0402_16V4Z
15 SCL
1 2 +3VS 14 Reserved
2 1
13

1
HDMI_TX1+ HDMI_R_TX1+ 2.2K_0402_5% HDMI_R_CLK- CEC
19 HDMI_TX1+ 4 4 3 3 12 CK- GND 20

5
1
100K_0402_5% 11 21
WCM-2012-900T_0805 HDMI_R_CLK+ CK_shield GND
10 22

P
OE#
@ R2109 HDMI_R_TX0- CK+ GND
2 A Y 4 HDMI_DETECT 20 9 D0- GND 23
1 2 8 D0_shield

G
0_0402_5% U75 HDMI_R_TX0+ 7
@ R2110 SN74AHCT1G125GW_SOT353-5 HDMI_R_TX1- D0+
6

3
D1-
1 2 5 D1_shield
0_0402_5% HDMI_R_TX1+ 4
L73 HDMI_R_TX2- D1+
3 D2-
HDMI_TX2- 1 1 HDMI_R_TX2-
19 HDMI_TX2- 2 2 HDMI_R_TX2+
2 D2_shield
1 D2+
HDMI_TX2+ 4 3 HDMI_R_TX2+ HDMI_R_TX0- @ C1249 1 2 100P_0402_50V8J SUYIN_100042MR019SX53ZL
C 19 HDMI_TX2+ 4 3 C
HDMI_R_TX0+ @ C1250 1 2 100P_0402_50V8J
WCM-2012-900T_0805
@ R2111 HDMI_R_TX1- @ C1251 1 2 100P_0402_50V8J
1 2 HDMI_R_TX1+ @ C1252 1 2 100P_0402_50V8J
0_0402_5%
HDMI_R_TX2- @ C1253 1 2 100P_0402_50V8J
HDMI_R_TX2+ @ C1254 1 2 100P_0402_50V8J

HDMI ESD
+3VS
2

Q98A

1 6 HDMIDAT
20 HDMIDAT_VGA
2N7002DW-7-F_SOT363-6

+3VS
5

Q98B

4 3 HDMICLK
20 HDMICLK_VGA
2N7002DW-7-F_SOT363-6

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4082P Vader Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 44 of 58
5 4 3 2 1
 A B C D

+3VALW
PQ3

3
TP0610K-T1-E3_SOT23-3

2 AC_LED 46
BATT
1 1

499K_0402_1% 340K_0402_1%
ADP_ID 40

PR1 1
+5VALW

2 1

@100P_0402_50V8J
1

0.01U_0402_25V7K
PR8

1
10K_0402_5%
100_0402_5%

2
PR2

PC7
PD4

1
PC1
RLZ3.6B_LL34
VIN DOCKVIN
1

PR4 1
2

2
ACES_88334-057N

2
ADP_SIGNAL 1 2
5 PR3
5 10K_0402_5%
4

2
4

8
3 PL1 PL2 PR5
3 SMB3025500YA_2P SMB3025500YA_2P 10K_0402_5%
2 3

P
2 ADPIN +
1 1 1 2 2 1 0 1 2 1 BATT_OVP 40
2 -

G
PJP1

105K_0402_1%
PR6 1
100P_0402_50V8J

0.01U_0402_25V7K

4
1
1000P_0402_50V7K
PU1A
2

PC6
100P_0402_50V8J
@PJSOT24C_SOT23-3

LM358ADT_SO8
1

1
PC5

2
PC4
PD1

2
PC3
2

2
PC2

1000P_0402_50V7K
1

2 2

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C
PR7
VMB +5VS 47K_0402_1%
PL3 BATT
3 PJP2 SMB3025500YA_2P CPU 1 2
3

1 1 1 2
2 2
3 EC_SMD PD2
3

1
4 EC_SMC @SM05_SOT23
4
5 5 3 PH1
1

6 6 1 10K_TH11-3H103FT_0603_1%
7 7 2
8 PC8 PC9 ENTRIP1 47
2

2
8 1000P_0402_50V7K 0.01U_0402_50V4Z PR10
GND 9

8
10 15K_0402_1%
GND
3

1
D
1 2 5

P
SUYIN_200275MR008GXOLZR + PQ1
0 7 2
+5VALW 1 2 6 G SSM3K7002FU_SC70-3
-

G
PR11 PU1B S

3
1

1 150K_0402_1%

4
1

1
PD3 LM358ADT_SO8
1

1
PC10 PR12
PR14 @SM24.TC_SOT23-3 2.55K_0402_1%
PR13 100_0402_5% 0.22U_0603_10V7K PR15
2

100_0402_5% 150K_0402_1% PC11

2

2
1000P_0402_50V7K ENTRIP2 47
2

2
SMB_EC_DA1 SMB_EC_DA1 39,40,41

1
D
SMB_EC_CK1 SMB_EC_CK1 39,40,41 2 PQ2
G SSM3K7002FU_SC70-3
BAT_ID 46 S

3
4 4

+3VL
PR16
6.49K_0402_1%
1 2
1

PR17
1K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
BATT_TEMP 40 Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 45 of 58
A B C D
 A B C D

P4 B+

BATT
VIN P2
PQ102
FDS6675BZ_SO8

PQ101 PQ103 1 8
1
PR102 PL101 2 7 1
AM4835EP-T1-PF_SO8 AM4835EP-T1-PF_SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
8 1 1 8 1 2 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%

4
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5 5 1 2 1 2 VIN
PR101

1
47P_0402_50V8J

47K_0402_5% PR104 ACDET PC102

1
0.1U_0603_25V7K

PC103

PC104

PC105
1 2 0_0402_5% 1U_0603_6.3V6M
40 AC_SET 1 2 ACSET

2
1

3
DTA144EUA_SC70-3 PR105
PC101

1
PQ104

0.22U_0603_16V7K
10K_0402_5%

PC108
1

1
2

2
1
PC109

200K_0402_5%
2 PC107 A COFF#

2
1

@0.1U_0603_25V7K

PC106

PR106
@0.01U_0402_16V7K

1
CHG_B+

2
PR107 CH GEN#

2
47K_0402_1% PR108 45 AC_LED PR139
10_1206_5% +3VL 100K_0402_5%
1 2 2
1

1
1 2 1 2 2 ACOFF 40,47

ACP
LPREF

ACSET

ACDET

LPMD

ACN

CHGEN

1
PQ105 D
TP 29
1

5
6
7
8
PQ107 D DTC115EUA_SC70-3 PR110 PC110 PA CIN PQ114
2
3

SSM3K7002FU_SC70-3 2 0_0402_5% 1U_0805_25V6K G SSM3K7002FU_SC70-3

3
1
G 32,34,40,43,48,49,50,52 SUSP# 1 2 8 28 1 2 S PQ106

3
IADSLP PVCC PC111 DTC115EUA_SC70-3
S
3

PR109 0.1U_0402_10V7K PQ108

150K_0402_5% 9 27 BST_CHG 1 2 4 AO4466_SO8
2 AGND BTST
PC112 BQ24740VREF PU101
1 2 10 VREF
BQ24740RHDR_QFN28_5X5
HIDRV 26 DH_CHG
PL102 PR112
BATT

3
2
1
PR111 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
1

3K_0402_1% D LX_CHG
11 VDAC PH 25 1 2 1 2
PA CIN 1 2 2 PQ109

1
G SSM3K7002FU_SC70-3 PD102

5
6
7
8
S PR113 VA DJ 12 24 RE GN 2 1
3

143K_0402_1% VADJ REGN

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 A COFF# 1 2 PR114 RLS4148_LL34-2 2

@0_0402_5% 13 23 DL _CHG
2
EXTPWR LODRV

1
PD101 40 VCTRL 1 2 PQ110

PC113

PC114

PC115

PC116
RLS4148_LL34-2 4 AO4466_SO8
1

14 22

2
ISYNSET PGND
1

DPMDET
1
PC117 PR115

IADAPT
1 2

SRSET

CELLS

1
1U_0603_6.3V6M 100K_0402_1% PC119

SRN

SRP
2

3
2
1
BAT
PR116
2

39K_0402_5% 1U_0603_10V6K PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5% BQ24740VREF

IADAPT
PR118
Charge Detector 1 2

1
10K_0402_5%
1 2 PR119
40 ADP_I 47K_0402_5%

1
D

100P_0402_50V8J
0.22U_0603_10V7K
1

1
2 BAT_ID 45

2
PC120

PC121
G
S PQ111

BATT
2

3
SSM3K7002FU_SC70-3

0.1U_0603_25V7K

@0.1U_0603_25V7K
PR120
2 1 IREF 40

PC122
PC124
133K_0402_1%

1
PC123
1

0.1U_0402_10V7K PR122

2
PR121 1M_0402_5%
200K_0402_1% 1 2
2

PR123
2

1M_0402_5%
3
1 2 3

P2 PR124
+3VL VIN 1K_0402_5%
VIN
1 2
1

+3VL ACIN 40

1
PR125
47_1206_5% PR126
1
100K_0402_5%

133K_0402_1% PR127
VIN PR130 10K_0402_1%
2

8
+3VL
10K_0402_1%

PR128

2.15K_0402_1% PU102B

2
1 2 5

P
+
1

PR129

7
2

O
1

PACIN
100K_0402_5%

PR131 6 -

G
133K_0402_1% PC125 CH GEN#
2

1
PR132

0.1U_0603_25V7K PC126 LM393DG_SO8

PR133
2

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
O 1 2
1

2 G SSM3K7002FU_SC70-3

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCHG#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D
1 2 P2
1.24VREF 40 FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP 40
PU104

4 REF CATHODE 3 1.24VREF

1 2 ACDET

1
PC127 2
PR137 NC
22P_0402_50V8J
1

100K_0402_1%

4
20K_0402_1% 5 1
4

2
ANODE NC
PR138

LMV431ACM5X_SOT23-5
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 46 of 58
A B C D
 A B C D E

2VREF_51125

0.22U_0603_10V7K

1
1 1

PC302

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
4.7U_0805_25V6-K
2200P_0402_50V7K

PR305 PR306
174K_0402_1% 133K_0402_1%
1

10U_0805_6.3V6M

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC301

PC303

2200P_0402_50V7K
1 2 1 2

1
PC304

PC313

PC305
2

2
6

5
6
7
8
PC306
PU301

8
7
6
5

ENTRIP2

TONSEL

VREF

ENTRIP1
VFB2

VFB1
25 PQ302
2
P PAD AO4466_SO8 2

2
PQ301
AO4466_SO8 7 24 4
VO2 VO1

UG1_5V
4
PR308 PC308

UG1_3V
8 VREG3 PGOOD 23
PR307 0_0402_5% 0.1U_0402_10V7K
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
1
2
3

PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303

4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
8
7
6
5

5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1

SKIPSEL

150U_D_6.3VM
VREG5
1

VCLK
GND
1

EN0

VIN
PC309
220U_6.3VM_R15

+ PQ303 TPS51125RGER_QFN24_4X4

PC310
AO4466_SO8 4 4 +

13

14

15

16

17

18
2
2

620K_0402_5%

1
1
2
3

3
2
1
VL PQ304

PR311
FDS6690AS_NL_SO8
1 2 PR316
1 2

1
R_EC_RSMRST# 28

10U_0805_10V6K
PC311
PR312 0_0805_5%
@0_0402_5%

2
3 3

PR317
0_0402_5%
45 ENTRIP1 45 ENTRIP2

1
1
B++

0.1U_0603_25V7K
2
PC312
2VREF_51125
1

D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL +5VL
+3VL PJP302 PJP304
PQ308 1 2 1 2 (4.5A,180mils ,Via NO.= 9) 2 1
SSM3K7002FU_SC70-3 VL +5VALWP +5VALW
PR313 PAD-OPEN 2x2m
PAD-OPEN 4x4m
5

PR315 100K_0402_5%
+3VLP +3VL
1

604K_0402_1% D D PQ307 PJP303

P

NC

2 4 1 2 2 2 1 2 +3VALW (3A,120mils ,Via NO.= 6) PJP301

A Y G G EC_ON 40 +3VALWP
2 1
G

S S SSM3K7002FU_SC70-3
40,46 ACOFF PAD-OPEN 4x4m
3

3
1

PU302 PAD-OPEN 2x2m

3

1
0.022U_0402_16V7K

74LVC1G14GW_SOT353-5
4 4
2

100K_0402_5%
PC314

PR314
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 47 of 58
A B C D E
 A B C D

1 1

B++
PR401

2200P_0402_50V7K
4.7K_0402_5%

4.7U_0805_25V6-K
,50,52 SUSP# 1 2

PC404
1

PC403
1

PR409

2
1

2 @10K_0402_5% 2

2
PC401
0.1U_0402_10V7K
2

+5VALW
2

5
6
7
8
BST_1.5V
1 2 BST1_1.5V 1 2

PR402 PC402 AO4466_SO8

1

0_0402_5% 0.1U_0402_10V7K PQ401

PR403

15

14
1
316_0402_1% PU401 4
PR404
EN_PSV

TP

VBST
255K_0402_1%
2

1 2 2 13 DH_1.5V PL402
TON DRVH 3.3UH_PCMC063T-3R3MN_6A_20%
PR405

3
2
1
+1.5VSP 2 1 3 12 LX_1.5V 1 2 +1.5VSP
VOUT LL
0_0402_5%
4 V5FILT TRIP 11 1 2

5
6
7
8

220U_B2_2.5VM
PR406
5 10 +5VALW 15.4K_0402_1%
VFB V5DRV
1
1

PC405 6 9 DL_1.5V AO4466_SO8

PGOOD DRVL
PGND

PQ402

PC409
1U_0603_10V6K +
GND

4
2

+1.5VSP PC406 2
PR407
7

1
1 2 4.7U_0805_10V6K
10K_0402_1%

3
2
1
2

3 3

TPS51117RGYR_QFN14_3.5x3.5
1

PR408 PJP401
10K_0402_1% 1 2 +1.5VS (4A,160mils ,Via NO.=8)
+1.5VSP
2

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 48 of 58
A B C D
 5 4 3 2 1

D D
PR501 PR502
29.4K_0402_1% 75K_0402_1% PR503 PR504
10.2K_0603_0.1% 14.3K_0603_0.1%
+1.05V_VCCP 1 2 1 2 1 2 1 2 +1.8VP
B+++

B+++

2
PR505 B+++ B+

2200P_0402_50V7K
0_0402_5% PL502
4.7U_0805_25V6-K

@4.7U_0805_25V6-K
HCB2012KF-121T50_0805
2 1

1
1

1
PC501

PC516

PC502
2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
8
7
6
5

5
6
7
8
PC503 PU501

1
@0.022U_0402_16V7K PQ502

VO2

VFB2

TONSEL

GND

VFB1

VO1

PC504

PC518

PC519

PC505
25 AO4466_SO8

2
PQ501 P PAD

2
AO4466_SO8 4 7 24 4
C
PGOOD2 PGOOD1 C
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.05V_VCCP 2 1 2 1 BST_1.05V 9 22 BST_1.8V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
+1.8VP
PL501 UG1_1.05V 2 1 UG_1.05V 10 21 UG_1.8V 2 1 UG1_1.8V PL503
2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 2.2UH_PCMB104E-2R2MS_14A_20%
+1.05V_VCCP 2 1 LX_1.05V 11 20 LX_1.8V 0_0402_5% 1 2 +1.8VP
LL2 LL1
LG_1.05V 12 19 LG_1.8V
DR VL2 DR VL1
8
7
6
5

5
6
7
8
PGND2

PGND1
1

V5FILT
TRIP2

TRIP1
PQ503 PQ504 1

V5IN

D
D
D
D
1

PC508 + AO4466_SO8 FDS6670AS_NL_SO8

330U_2V_M_R15M
PC517
220U_D2_4VM PC509 +
4.7U_0805_6.3V6K 4 TPS51124RGER_QFN24_4x4 PC510
2

13

14

15

16

17

18
2 4.7U_0805_6.3V6K
4

1
G 2

S
S
S
1
2
3

<BOM Structure> PR511

3
2
1
16.5K_0402_1% PR510
1 2 16.5K_0402_1%

2
PR513
0_0402_5% PR512
2 1 0_0402_5%
32,34,40,43,46,48,50,52 SUSP# 1 2
B
1 2
SYSON 32,40,41,43 B
+5VALW
PR514
3.3_0402_5%
1

1
PC513 PC514 PC515 PC512
@0.1U_0402_10V7K 1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K
2

2
PJP501
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.=12)
PAD-OPEN 4x4m

PJP502
+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V_VCCP/1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 49 of 58
5 4 3 2 1
 5 4 3 2 1

D D

+1.8V

PU601
1 VIN VCNTL 6 +5VALW
2 GND NC 5

1
PC601 3 7
VREF NC

1
10U_0805_10V4Z

2
PR601 PC603
4 VOUT NC 8
1K_0402_1% 1U_0603_10V6K

2
9

2
TP
G2992F1U_SO8

42,43 SYSON# 1 2

0.1U_0402_10V7K
PR602 +0.9VP

1
@0_0402_5%
PQ601
SSM3K7002FU_SC70-3 PR603

1
D
1K_0402_1%
1 2 2 PC605
43 SUSP

PC604
PR604 G 10U_0805_6.3V6M

2
0_0402_5% S

3
1
C PC606 C

2
@0.1U_0402_16V7K

+5VALWP

1
PC609 +1.5VS
1U_0603_10V6K

2
PJP601

+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4)

6
PU603

1
5

VCNTL
PAD-OPEN 3x3m VIN
7 PC610
POK 10U_0805_6.3V6M
9

2
VIN

VOUT 3

32,34,40,43,46,48,49,52 SUSP# 1 2 8 EN VOUT 4 +1.1V_PCIE

PR606

GND
1

1
0_0402_5% 2
FB PC612
B PJP603 PC611 22U_0805_6.3V6M B

2
1
1 2 +PCIE (3A,120mils ,Via NO.= 6) @0.01U_0402_16V7K
+1.1V_PCIE

1
PR607
PAD-OPEN 3x3m
40.2K_0402_1% PC613

2
APL5913-KAC-TRL_SO8 47P_0402_50V8J

2
1
PR608
105K_0402_1%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VSP/2.5VSP/1.2V_PCIE
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, December 26, 2007 Sheet 50 of 58
5 4 3 2 1
 8 7 6 5 4 3 2 1

+CPU_B+ PL200
SMB3025500YA_2P
1 2 B+

2200P_0402_50V7K

10U_1206_25V6M

10U_1206_25V6M
H H
1 1

68U_25V_M_R0.36

68U_25V_M_R0.36
1

1
PC202

PC203

PC204

PC200

PC201
+ +

2
2 2

5
6
7
8
+CPU_B+
PQ200

D
D
D
D
SI4684DY-T1-E3_SO8

G
S
S
S
PR201

4
3
2
1
10_0603_5%

0.01U_0402_25V7K
PR200 PC206

1
0_0402_5% 0.22U_0603_16V7K
G BST_CPU1_1 2 1BST_CPU1_21 2 PL201 G

DH_ CPU1 0.36H_ETQP4LR36WFC_24A_20%

1U_0603_10V6K
1

1
PC207
LX_CPU1 1 2 +VCC_CORE

1
PC205
PR252

2
1_0402_5%

5
6
7
8

5
6
7
8

4.7_1206_5%
PR203

2
4.7_1206_5%

PR230
PQ201 PQ202 10_0402_1%

2
+5VS

PR202
PR204 PC208
AO4456_SO8 AO4456_SO8 10K_0402_1% 0.22U_0603_16V7K

1
+3VS

10_0603_5%
+5VS 1 2 2 1

1
2
4 4

2200P_0603_50V7K1

2
PR205

14
PU201 PR206

1
PC224 5.11K_0402_1% 2 1

VCC
1

3
2
1

3
2
1

PC209
PR207

2
1U_0603_10V6K

11

1
BOOT1 @0_0402_5%
1

F PR208 F
1 2 3 PVCC
PC210

1.91K_0603_1% 12 VSUM VO
UGATE1
2

1U_0603_10V6K 13

1
PHASE1
15 PWM1
2 DL_CPU1 ISEN1
VGATE 15,28 LGATE1 PR209 +CPU_B+
16 10 BST_CPU2_1 2 1 BST_CPU2_2 PC217
PWM2 BOOT2 0.22U_0603_16V7K
9 0_0402_5% 1 2
19 UGATE2
20

18

39

40
4 FCCM

5
6
7
8

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
PU200 ISL6260CCRZ_QFN40_6X6 8
PHASE2 PQ203
VSS

3V3
VDD

VIN

PGOOD

D
D
D
D
LGATE2 6 SI4684DY-T1-E3_SO8

1
PC242

PC241
7 EN

PGND

PC212
4

GND
VR_TT#

G
S
S
S
TP

2
2 PR2101 3 27 PWM1

4
3
2
1
147K_0402_1% RBIAS PWM1

17

1
E E
5 ISL6210CRZ-T_QFN16_4X4
PC216 NTC
2 1 6 23 ISEN1
SOFT ISEN1 PL202
0.015U_0402_16V7K
2 PR2111 28 DH_ CPU2 0.36H_ETQP4LR36WFC_24A_20%
5 CPU_VID0 VID0
5 CPU_VID1 2 PR212 1 0_0402_5% 29 VID1
0_0402_5% 2 PR213 1 30 26 PWM2 LX_CPU2 1 2 +VCC_CORE
5 CPU_VID2 VID2 PWM2
5 CPU_VID3 2 PR214 1 0_0402_5% 31 VID3

2
5 CPU_VID4
0_0402_5% 2 PR215 1 32 VID4

5
6
7
8

5
6
7
8
5 CPU_VID5 2 PR216 1 0_0402_5% 33 VID5
PR250 PR219

2
4.7_1206_5%

4.7_1206_5%
0_0402_5% 2 PR217 1 34 22 ISEN2 0_0402_5% PQ204 PQ205 10_0402_1%
5 CPU_VID6 VID6 ISEN2

PR218

PR233
PR221 PC218
0_0402_5%
2 PR220 1 37 AO4456_SO8 AO4456_SO8 10K_0402_1% 0.22U_0603_16V7K

1
5,7,27 H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1
2 PR222 1 36 4 4

2200P_0603_50V7K 1

1
7,28 DPRSLPVR DPRSLPVR
499_0402_1%

2
2 PR223 1 1
D
5 H_PSI# PSI# PR224 D
0_0402_5%
2 24 5.11K_0402_1% 2 1

3
2
1

3
2
1
PMON FCCM

1
PR225

PC219
2 PR226 1 0_0402_5% 38 PR227
@0_0402_5%

1
15 CLK_ENABLE# CLK_EN#
2 1 +5VS

2
40 VR_ON 2 PR228 1 35 0_0402_5% VSUM VO
VR_ON
0_0402_5%
12 25 PR229 DL_CPU2
5 VCCSENSE PC220 VSEN PWM3
2 1 PWM3
2 1 13 @0_0402_5% ISEN2
RTN +CPU_B+
1

1000P_0402_50V7K 21 ISEN3
PC245 ISEN3 +5VS
11 VDIFF
PC221 @82n_0402_10V7K
2

2 1

@2200P_0402_50V7K

@4.7U_0805_25V6-K

@4.7U_0805_25V6-K

@4.7U_0805_25V6-K

@4.7U_0805_25V6-K
10 PR232
FB

5
6
7
8
1000P_0402_50V7K PR231 @0_0402_5%
7 2 1 2 1 PQ206

D
D
D
D
OCSET

1
@1U_0603_10V6K

PC226

PC227

PC244

PC243
BST_CPU3_1
11.5K_0402_1%

BST_CPU3_2
9
5 VSSSENSE COMP

PC225
C @SI4684DY-T1-E3_SO8 C

PC223
PR234 PC222 17 VSUM

2
VSUM

G
S
S
S
3K_0402_1%

180_0402_1% 1800P_0402_50V7K PR235 8 VW

1
1000P_0402_50V7K

2 1 1 2 2 1 2

4
3
2
1
PR237
DROOP

2 PR236 1 0_0402_5% 41 GND PC230

DFB

0.22U_0603_10V7K

1.2K_0402_1% PU203 @0.22U_0603_16V7K

VO

2
4.53K_0402_1%

PC229

5 1 1 2 PL203
2

VCC BOOT
2
PR239

PC231

1 2 2 PR238 1
14

15

16

6 8 DH_ CPU3 @0.36H_ETQP4LR36WFC_24A_20%

1

PC232 PC228 51K_0402_1% FCCM UGATE

2

1 2 0.022U_0402_16V7K 2 7 LX_CPU3 1 2 +VCC_CORE

PWM PHASE
0.1U_0402_10V7K

2
220P_0402_25V8J PC233 VO 3 4
10KB_0603_5%_ERTJ1VR103J

GND LGATE

5
6
7
8

5
6
7
8

@4.7_1206_5%
2 1 PR241

PR240
@ISL6208CRZ-T_QFN8 @10_0402_1%
1K_0402_1%

1000P_0402_50V7K PQ207 PQ208 PR243 PC235

1

@680P_0603_50V8J
PC234

PR242 @AO4456_SO8 @AO4456_SO8 @10K_0402_1% @0.22U_0603_16V7K

@1K_0402_1%

1
1

2 1 1 2 2 1

1 1
1

B B
PR244

6.98K_0402_1% PR245 PR246 4 4

2

PH200

5.11K_0603_1% 1K_0402_1%
PR247

2
PC236
2 1 2 1
PR248
2

2
@5.11K_0402_1% 2 1
2

3
2
1

3
2
1
PR249
PC238
@0_0402_5%

1
1

2 1
PC237 VSUM VO
0.01U_0402_16V7K 330P_0402_50V7K
2

DL_CPU3

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Montevina Consumer Discrete
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 51 of 58
8 7 6 5 4 3 2 1
 A B C D

1 PR719 1

0_0402_5%
2 1 +6269_VCC
PR702
47K_0402_5%
32,34,40,43,46,48,49,50 SUSP# 1 2
PC707

1
2.2U_0603_10V6K

1
PL701
HCB2012KF-121T50_0805

2
PC702 VGA_B+ 2 1 B+

2
0.1U_0402_10V7K

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

1
4

1
PC703

PC704

PC710
2 1 PC705
PC716 @680P_0402_50V7K

EN

VCC

VIN
FCCM

2
22P_0402_50V8J

2
PR720
PR721 2 1 2 1 5 COMP GND 17

5
6
7
8
18 VDD_SENSE 2 1 PC717 90.9K_0402_1%
PQ701

D
D
D
D
0_0402_5% 6800P_0402_25V7K
PGOOD 16 SI4684DY-T1-E3_SO8
PR712 1 2 6 PU701
10_0402_5% PR707 FB ISL6269ACRZ-T_QFN16_4X4

G
S
S
S
+NVVDDP 1 2 2.1K_0402_1% 2 1 15 LX_VGA
PHASE PR711
PR706

4
3
2
1
57.6K_0402_1% 7 0_0402_5%
FSET DH_VGA 1 DH_VGA_1
UG 14 2
2

2 2 1 PL702 2

1
PR714 PC715 0.33UH_PCMC063T-R33MN_20A_20%
8.66K_0402_1% 0.01U_0402_16V7K 8 13 BST_VGA 1 2 BST1_VGA 1 2 1 2 +NVVDDP
PR704 VO BOOT

PGND

PVCC
4.12K_0402_1% PR708 PC706

ISEN
1

0_0402_5% 0.22U_0603_16V7K

LG
2

5
6
7
8

1
5
6
7
8
PQ702 PR710

10

11

12
1

D PQ703 @4.7_1206_5%
1 1 1
+NVVDDP

AO4456_SO8

330U_D2E_2VM_R7M

330U_D2E_2VM_R7M

330U_D2E_2VM_R7M

330U_D2E_2VM_R7M
2 1 2 PQ705 PR713 6269_PVCC 1
20 GPU_VID1
0.022U_0402_16V7K

AO4456_SO8

PC713

PC714

PC718
G SSM3K7002FU_SC70-3 13K_0402_1% + + +
PR709

2 2
PR715

PC708
S 2 1 4 +
3

10K_0402_1%
1

0_0402_5% 4 PC709
1
1

2 2 2
PR717 @680P_0603_50V7K 2
PR705

1
PC712

10K_0402_1% 1 2
2

3
2
1
7.87K_0402_1%
2

3
2
1
+5VS
PR716
1

D
2 1 2 PQ704
20 GPU_VID0

1
G SSM3K7002FU_SC70-3
0.01U_0402_16V7K

S PR703
3

10K_0402_1%
1

PC711

0_0402_5%
PR718
10K_0402_1% PR722
2

2
+6269_VCC
3 2 1 6269_PVCC 3
2

PJP701
2.2_0603_5% 1 2 +NVVDD (12A,480mils ,Via NO.= 24)
+NVVDDP
1

PAD-OPEN 4x4m
PC701
2

2.2U_0603_10V6K PJP702
GPUID1 GPUID0 NB9P-GS 1 2

0 0 0.9V PAD-OPEN 4x4m

PJP703
0 1 1.0V 1 2
1 0 1.05V
PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 52 of 58
A B C D
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit

Request
Item Page# Title Date Owner Issue Description Solution Description Cut in
D D
43 DCIN/
BATTERY CONN
1 2006/09/07 HP R.L. Change charger control from HW to FW All the related components DB1B
44 Charger
50 ADP_OCP
2 50 ADP_OCP 2006/10/12 HP R.L. Identify 65W adapter as "light" Change PR223 from 180K to 147K DB2

VDD_CORE 2006/10/12 HP R.L. Change VGA chipset from ATi M62S to M64S Change PR355 from 11K to 9.76K
3 51 /PCIE_VDD Change PR392 from 33.2K to 24.9K DB2

+1.25VMP/ Change PR249 from 0 to 47K

4 52 +1.05V_VCCP 2006/10/12 HW For HW's requirement, fine tune +1.05V_VCCP sequence Add PC186 as 47pF
Tony J DB2
Install PD45

VDD_CORE Change PR358 from 47K to 49.9K

5 51 /PCIE_VDD 2006/10/12 PWR Fine tune PCIE_VDD Change PR359 from 150K to 100K DB2
Francis H
VDD_CORE SI
2006/11/08 HW
6
C
51 /PCIE_VDD Fine tune the GPU "Power Play" sequence Add PC196 as 1uf C
Tony J
8
51 VDD_CORE SI
/PCIE_VDD 2006/11/08 HW Fine tune the power sequence of PCIE_VDD Change PU31 pin5, 9 source from VDD_MEM18 to +1.8V
Tony J
9 Base on "Energy STAR" spec, reduce S5 and S3
44 Charger 2006/11/08 PWR power consumption (AC mode) Uninstall PQ11 SI
Francis H
10 48 1.8V/0.9V 2006/11/08 HP Add PM_SLP_M# sequence Add PR387 SI

+1.25VMP/ Change PR243 to 47K,

11 52 +1.05V_VCCP 2006/11/20 HW For HW's requirement, fine tune +2.5VS sequence Change PC170 to 0.1uF SI
Tony J

+1.25VMP/ HW Fine tune the +2.5VS power level to 2.57V (typ) Change PR244 from 13K to 13.7K SI2
12 52 +1.05V_VCCP 2007/2/28
Tony J

B 13 50 ADP_OCP 2007/2/28 HP R.L. System identity Change PR223 from 147K to 137K SI2 B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 53 of 58
5 4 3 2 1
 5 4 3 2 1

It em Fixed Issue Reason for change PAGE Modify List M.B. V er.

<2007.10.08> 1 Fix Audio disappear follow Intel SB design suggestion to separate HDA Bus 27 Add R439, R440, R442, R444 0.2

2 Add to determine board type and project 28 Add R777, R776, R774, R775
0.2
Meet EC request 28 non-stuff R419, R695
D D

Fix Audio disappear follow Intel SB design suggestion 29 Change power rail from +1.5v to +3v 0.2
3

4 meet SW debug request 32 Add Debug CLK and PLT_RST#

0.2

5 Fix Audio disappear follow Intel HDA bus design for Discrete platform 34 Change codec power rail from +1.5v to +3v 0.2

6 Fix can not power on issue Meet EC and SPI access sequence 39 change SPI power rail from+3valw to +3VL 0.2

7 Follow Intel design guide 7 Change R30 value 0.2

<2007.10.09> 1 Fix HDMI can not detect follow Nvidia design request 18 change HDMI I2C channel to I2C B channel 0.2

2 Meet HP request to remove TV 18 Remove TV all components at VGA side 0.2

3 update ODD footprint 30 update JODD footprint

0.2
C C

4 Fix ODD wrong pins lower system power consumption 33 change Card Reader LED power rail
0.2

5 Meet Sub-woofer pwoer request 37 change D81, D82

0.2

6 Solve EC always damage Solve EC always damage 40 change D53 direction

0.2

7 Double pull up and pwoer rail is different 41 Remove pull up resisters

0.2

8 lower system power consumption change Cap-lock, HDD LED power rail
41 0.2

9 Meet HP request to remove TV 42 Remove TV all components at Dock side 0.2

lower system power consumption and meet LED status 43 Add +5VS_LED (Inculde DIM function) 0.2
10

11 solve HDMI pull up update D79 footprint 0.2

B
44 B

<2007.10.19> 1 27 Change Y4 material 0.2

Meet ME limit area at KBC

2 Follow IDT suugestion 35 change R886 to 1206 0.2

3 Follow Nvidia suggestion 25 Change R193, R196 size to 0603 0.2

<2007.10.20> 1 follow correct power rail 38 change Touch screen power rail 0.2

2 Meet HP request 39 Change ST G-sensor P/N & package 0.2

3 Meet HP request for WLAN &TV slot swap 32 Swapped WLAN and TV all support components 0.2

1 Change LAN chip to meet Energy star spec 31 change LAN brand to Realtek 0.2
<2007.10.22>
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR(1)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 54 of 58
5 4 3 2 1
 5 4 3 2 1

It em Fixed Issue Reason for change PAGE Modify List M.B. V er.

28 Chnage all USB channel 0.2

<2007.10.23> 1 Fix USB loading of SB follow 14" Blade USB channel design
17 Change USB channel of Camera
32 Change USB channel of WLAN & TV Tuner & New card
38 Change USB channel of Left side, Right side, E-SATA
D
38 Change USB channel of Touch screen, Finger print D

42 Change USB channel of Dock

Follow JMicro CardReader Vendor Suggestion 33 Change R114 & R1546 value
2 0.2

Solve Speak no sound issue 36 add pullup at HP_DET#

3
36 Change Q203 to N-channel FET 0.2
34 Change R524 pin2 connect to JACK_DET#

1 Meet HP request for QC and DC co-lay 4 add GTLREF and XDP circuits

<2007.10.25> 5
0.2
6

2 Meet Intel request for CLK request Add R127 to meet Intel CLK design 0.2
15

3 Solve G-sensor LED control 28, 41 change G-sensor LED control to GPIO19 of SB 0.2

4
C C
Follow Capactivity board design 41 change Pin7 & 7 NET 0.2

<2007.10.31> 1 34 Use Audio Codec GPIO5 to shutdoown Sub-woofer

2 40 Connect HDA_RST#_CODEC to EC

3 34 Separate SPDIF out to VGA and Docking

<2007.11.02> 1 Common design 16 R204,R205 no stuff 0.3

2 Change +5VS_LOGO resistor size to 0805 17 R642 size to 0805 0.3

B B

3 Double pull up 20 R2046,R2047 no stuff 0.3

4 For card reader power 33 install R1553 0.3

5 For KBC C0 version 40 R616 no stuff 0.3

6 Add pull down resistor for SUSP# and SYSON 40 Change R615 to 8.2k and add R2062 0.3

7 Change HAD_RST#_CODEC from KBC pin 36 to pin 38 40 0.3

8 Change GSENSOR LED control pin from SB to KBC 41 Install R668, no install R667 0.3

9
A A
Add pull down for sub-woofer power-down 37 Add R2063 0.3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR(2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 55 of 58
5 4 3 2 1
 5 4 3 2 1

It em Fixed Issue Reason for change PAGE Modify List M.B. V er.

<2007.11.04> 1 Move resistor from LS4086P to MB 41 Add R2064 0.3

2 Change to dual type for layout space 16 Change Q69,Q70 to dual type 0.3
D D

3
Only use LIS302DLTR 39 U77, R2025 no install 0.3

4 Change CIR_IN power rail 40 Connect R642.1 to +5VL 0.3

<2007.11.05> 1 nVIDIA suggestion for NB9M-GS/GE 22 R1005 change to 475 ohm 0.3

nVIDIA suggestion -- add Pull up 2.2K on

2 HDMIDAT_VGA and HDMICLK_VGA to 18 Add R2065,R2066 0.3
+3VS. at VGA side

<2007.11.06>
1 EMI request CRT add resistor for EMI 16 Add R2069,R2070,R2071 0.3

2 HP suggestion 34 Change C746,C747,C748,C749 to 1000PF 0.3

C C

3 USB camere power and add GPO pin for shutdown 17 Add PJP5,R2072,R2073 0.3

1. USB camera – SB GPIO20

4 LAN DSM support 31 2. ISOLATE – SB GPIO18 0.3
3. LAN OGPIO – SB GPIO14

5 EC_BEEP 34 Add R2076 0.3

6 G-sensor LED control by SB 41 Delete R668 0.3

<2007.11.07> 1
Modify FPR connector pin assignment 38 Modify JP41 pin assignment 0.3

34 1. Add C2108,C2109,R2080,R2081
Modify Audio 36 2. Add R2082,R2083
2 37 0.3
42 3. Change C1008,C1009 to 1UF
4. Delete C976,C977
5. Delete R515,R516,C916
B B
6. Change C982,C980,C984 from 5900p to 0.039u
7. Change C983,C992 from 1000p to 100p
8. Add EC_MUTE# to sub-woofer shutdown pin and R2084

1. Delete strap pin

3 nVIDIA suggestion 20 2. Change R1020, R1015, R1010 to 475 ohm 0.3
3. Swap THERMDN and THERMDP

<2007.11.08> 1 EMI request 17 Add C2100,C2111 0.3

36
2 Audio Change C970,C971 to 22uF, add C2112, change D38 to dual type 0.3
37
Change HDMI DDC to I2CD
<2007.11.09> 19 R387,R388,R415,R422,R427 -- install
1 nVIDIA suggestion Change R415 to 10 ohm and no install 0.3
20 Delete R99, Change +IFPC_PLLVDD to +PCIE
Do not install R2030
2 JMicron suggestion 33 Add D86 for card reader wake up 0.3
Add SB GPIO22 for wake up event
A A

<2007.11.12> 1 HP request 4 Add EMC1403 for Qaud core 0.3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR(3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 56 of 58
5 4 3 2 1
 5 4 3 2 1

It em Fixed Issue Reason for change PAGE Modify List M.B. V er.

<2007.12.12> 1 MV DG for VDDC_QDAC 10 Chagne VCCD_QDAC to +1.5VS 0 .4

2 WLAN issue 32 Change XMIT_OFF#,WL_LED# and component to WLAN connector 0 .4

D D

3 PCIE issue 28 Swap GLAN and NewCard PCIE port 0 .4

4 Modify CardReader LED 33 Use 2N7002 to control LED 0 .4

Cha nge SMB_EC_DA1,SMB_EC_CK1 power rail from +5VL to +3VL

Add C2118 for KBC pin124
5 KBC 40 Chagne EC_THERM power rail to +3VS 0 .4

6 WL_BLUE_LED# issue 41 Add R2089 pull up for WL_BLUE_LED# 0 .4

7 Power sequence 43 Add R2099,R2100,C2119 a nd Q89 change to dual type 0 .4

8 DIM_LED 43 Delete Q97B,R2 11 0 .4

9 40 Change EC_PME# power rail to +3VALW 0 .4

C C
EC_PME#

10 WLAN issue 28 Add R2 101 0 .4

11 Change TP power rail 41 Change TP power rail to +5VALW 0 .4

12 G-sensor 41 G-sensor -- R2031 cha nge to 470 ohm and pull up to +3VS 0 .4

13 For Dock present 42 R1570 change to 22 ohm,R61 change to 2K ohm 0 .4

14 Clock generator 15 Add series R2102,R2103 for 27M_SSC and 27M_CLK 0 .4

15 HDCP ROM 19 R951 pull up,R959 no install 0 .4

B B

C272,C273,C2120 -- 470 pF
C 828,C798 -- 10pF
16 EMI request 17 C2 1 11 -- 220pF 0 .4
Add D87

17 Modify BT/FPR circuit 38 0 .4

<2007.12.24> 36
1 HP request Change value 0 .4
37

<2007.12.25> 1 For ENE cap board EMI issue 40 Add R and C 0 .4

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR(4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 57 of 58
5 4 3 2 1
 A

1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/11/24 Deciphered Date 2007/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 26, 2007 Sheet 58 of 58
A