This document provides information about a mid-semester test for an Advanced VLSI Design course. It includes details such as the course number, title, date and time of the exam, number of pages and questions. The 7 questions cover topics like clock skew, clock synchronization using PLL, positive edge triggered register circuit, multiplexer based flip-flop timing parameters, simultaneous switching noise reduction using slew-rate control, NMOS buffer working, and electrostatic discharge protection circuit and failures.
This document provides information about a mid-semester test for an Advanced VLSI Design course. It includes details such as the course number, title, date and time of the exam, number of pages and questions. The 7 questions cover topics like clock skew, clock synchronization using PLL, positive edge triggered register circuit, multiplexer based flip-flop timing parameters, simultaneous switching noise reduction using slew-rate control, NMOS buffer working, and electrostatic discharge protection circuit and failures.
This document provides information about a mid-semester test for an Advanced VLSI Design course. It includes details such as the course number, title, date and time of the exam, number of pages and questions. The 7 questions cover topics like clock skew, clock synchronization using PLL, positive edge triggered register circuit, multiplexer based flip-flop timing parameters, simultaneous switching noise reduction using slew-rate control, NMOS buffer working, and electrostatic discharge protection circuit and failures.
This document provides information about a mid-semester test for an Advanced VLSI Design course. It includes details such as the course number, title, date and time of the exam, number of pages and questions. The 7 questions cover topics like clock skew, clock synchronization using PLL, positive edge triggered register circuit, multiplexer based flip-flop timing parameters, simultaneous switching noise reduction using slew-rate control, NMOS buffer working, and electrostatic discharge protection circuit and failures.
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Birla Institute of Technology & Science, Pilani
Work-Integrated Learning Programmes Division
First Semester 2018-2019
Mid-Semester Test (EC-2 Regular)
Course No. : MEL ZG623
Course Title : ADVANCED VLSI DESIGN Nature of Exam : Closed Book Weightage : 30% No. of Pages =1 Duration : 2 Hours No. of Questions = 7 Date of Exam : 30/09/2018 (FN) Note: 1. Please follow all the Instructions to Candidates given on the cover page of the answer book. 2. All parts of a question should be answered consecutively. Each answer should start from a fresh page. 3. Assumptions made if any, should be stated clearly at the beginning of your answer.
Q.1. Define the term "Clock Skew". Explain the effects of Positive Clock Skew and Negative Clock Skew quantitatively. [1 + 2 + 2 = 5]
Q.2. What is the necessity of clock synchronization ? How Clock synchronization can be done using PLL ? [4]
Q.3. Draw the C2MOS positive edge triggered register circuit. Explain how this circuit is insensitive to clock overlap. [2 + 3 = 5]
Q.4. Draw the Multiplexer based positive edge triggered flip-flop. Give the expressions for setup time, hold time & Tc-q in terms of inverter and Transmission gate delays. [5]
Q.5. (a) What is Simultaneous Switching Noise?
(b) Explain how Slew-rate control technique is used to reduce SSN. [4]
Q.6. Explain the working of NMOS only Buffer [3]
Q.7. Explain the necessity of ESD protection circuit? Give a short notes on ESD related failures? [4]
Birla Institute of Technology & Science, Pilani Work-Integrated Learning Programmes Division First Semester 2019-2020 Comprehensive Examination (EC-3 Regular)
