74HCU04

Hex unbuffered inverter

Rev. 9 — 31 May 2021 Product data sheet

1. General description
The 74HCU04 is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Balanced propagation delays
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +125 °C

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature Name Description Version
range
74HCU04D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
74HCU04PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
74HCU04BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia 74HCU04
Hex unbuffered inverter

4. Functional diagram
1
1 2

1 1A 1Y 2 1
3 4

3 2A 2Y 4
1
5 6
5 3A 3Y 6
1
9 8
9 4A 4Y 8

1
11 5A 5Y 10 11 10

13 6A 6Y 12 1
13 12 A Y

mna342 mna343 mna045

Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one inverter)

5. Pinning information

5.1. Pinning

74HCU04
14 VCC
terminal 1
1A

index area
1

1Y 2 13 6A

2A 3 12 6Y
74HCU04 2Y 4 11 5A

3A 5 VCC(1) 10 5Y
1A 1 14 VCC
1Y 2 13 6A 3Y 6 9 4A
7

2A 3 12 6Y
GND

4Y

2Y 4 11 5A 001aal925
3A 5 10 5Y
Transparent top view
3Y 6 9 4A
(1) This is not a supply pin. There is no electrical or
GND 7 8 4Y
mechanical requirement to solder the pad. In case
001aal924 soldered, the solder land should remain floating or
connected to VCC.
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

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Nexperia 74HCU04
Hex unbuffered inverter

5.2. Pin description

Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input
1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output
GND 7 ground (0 V)
VCC 14 supply voltage

6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level
Input Output
nA nY
L H
H L

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7.0 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±50 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.0 5.0 6.0 V
VI input voltage 0 - VCC V
VO output voltage 0 - VCC V
Tamb ambient temperature -40 +25 +125 °C

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Nexperia 74HCU04
Hex unbuffered inverter

9. Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
VIH HIGH-level VCC = 2.0 V 1.7 1.4 - 1.7 - 1.7 - V
input voltage VCC = 4.5 V 3.6 2.6 - 3.6 - 3.6 - V
VCC = 5.5 V 4.8 3.4 - 4.8 - 4.8 - V
VIL LOW-level VCC = 2.0 V - 0.6 0.3 - 0.3 - 0.3 V
input voltage VCC = 4.5 V - 1.9 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - 2.6 1.2 - 1.2 - 1.2 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = -20 μA; VCC = 2.0 V 1.8 2.0 - 1.8 - 1.8 - V
IO = -20 μA; VCC = 4.5 V 4.0 4.5 - 4.0 - 4.0 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -20 μA; VCC = 6.0 V 5.5 6.0 - 5.5 - 5.5 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 μA; VCC = 2.0 V - 0 0.2 - 0.2 - 0.2 V
IO = 20 μA; VCC = 4.5 V - 0 0.5 - 0.5 - 0.5 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 20 μA; VCC = 6.0 V - 0 0.5 - 0.5 - 0.5 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 2 - 20 - 20 μA
VCC = 6.0 V
CI input - 3.5 - - - - - pF
capacitance

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Nexperia 74HCU04
Hex unbuffered inverter

10. Dynamic characteristics

Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); tr = tf = 6.0 ns; For test circuit see Fig. 7.
Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit
+85 °C +125 °C
Typ Max Max Max
tpd propagation delay nA to nY; see Fig. 6 [1]
VCC = 2.0 V; CL = 50 pF 19 70 90 105 ns
VCC = 4.5 V; CL = 50 pF 7 14 18 21 ns
VCC = 5.0 V; CL = 15 pF 5 - - - ns
VCC = 6.0 V; CL = 50 pF 6 12 15 18 ns
tt transition time see Fig. 6 [2]
VCC = 2.0 V; CL = 50 pF 19 75 95 110 ns
VCC = 4.5 V; CL = 50 pF 7 15 19 22 ns
VCC = 6.0 V; CL = 50 pF 6 13 16 19 ns
CPD power dissipation per inverter; VI = GND to VCC [3] 10 - - - pF
capacitance

[1] tpd is the same as tPHL, tPLH.

[2] tt is the same as tTHL, tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
Σ(CL x VCC x fo) = sum of outputs.

10.1. Waveform and test circuit

VI
VCC
nA input VM VM
VI VO
GND PULSE
DUT
t PHL t PLH GENERATOR
CL
RT
VOH 50 pF
90 %
nY output VM VM
mna034
10 %
VOL Definitions for test circuit:
t THL t TLH
CL = Load capacitance including jig and probe
mna722 capacitance.
VM = 0.5 x VCC; VI = GND to VCC. RT = Termination resistance should be equal to
output impedance Zo of the pulse generator.
Fig. 6. The input (nA) to output (nY) propagation delay
times Fig. 7. Test circuit for measuring switching times

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Nexperia 74HCU04
Hex unbuffered inverter

11. Typical transfer characteristics

001aal928 001aal927
2.4 1.2 6 24

VO (1) ID VO ID
(V) (mA) (V) (1) (mA)

1.6 0.8 4 16

0.8 0.4 2 8

(2) (2)
0 0 0 0
0 0.8 1.6 2.4 0 2 4 6
VI (V) VI (V)

Tamb = 25 °C. Tamb = 25 °C.

Fig. 8. VCC = 2.0 V; IO = 0 A Fig. 9. VCC = 4.5 V; IO = 0 A

001aal926
6 60
(1)

VO ID
(V) (mA)

4 40

Rbias = 560 kΩ

VCC
2 20

0.47 µF input output 100 µF

(2)
VI
A IO
(f = 1 kHz)
0 0
0 2 4 6 GND
VI (V) mna050

Tamb = 25 °C.

fi = 1 kHz at VO is constant

Fig. 10. VCC = 6.0 V; IO = 0 A Fig. 11. Test set-up for measuring forward
transconductance

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Nexperia 74HCU04
Hex unbuffered inverter

mna355
40
g fs
(mA/V)

30

20

10

0
0 2 4 6
VCC (V)

Tamb = 25 °C.
Fig. 12. Typical forward transconductance as a function of the supply voltage

12. Application information

Some applications are:
• Linear amplifier (see Fig. 13)
• Crystal oscillator design (see Fig. 14)
• Astable multivibrator (see Fig. 15)
Remark: All values given are typical unless otherwise specified.

R2
R1

VCC
R2
1 µF R1 U04
U04
C1 C2
ZL out

mna052 mna053

Maximum Vo(p-p) = VCC - 2.0 V centered at 0.5VCC. C1 = 47 pF (typical)

C2 = 33 pF (typical)
R1 = 1 MΩ to 10 MΩ (typical
R2 optimum value depends on the frequency
Gol = open loop gain
and required stability against changes in VCC or
Gv = voltage gain average minimum ICC.
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ ICC is typically 5 mA at VCC = 5 V and fi = 10 MHz.
ZL > 10 kΩ; Gol = 20 (typical)
VCC = 6.0 V
Typical unity gain bandwidth product is 5 MHz.

Fig. 13. Linear amplifier Fig. 14. Crystal oscillator

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Nexperia 74HCU04
Hex unbuffered inverter

Table 8. External components for resonator (f < 1 MHz)

All values given are typical and must be used as an initial set-up.
Frequency R1 R2 C1 C2
10 kHz to 15.9 kHz 22 MΩ 220 kΩ 56 pF 20 pF
16 kHz to 24.9 kHz 22 MΩ 220 kΩ 56 pF 10 pF
25 kHz to 54.9 kHz 22 MΩ 100 kΩ 56 pF 10 pF
55 kHz to 129.9 kHz 22 MΩ 100 kΩ 47 pF 5 pF
130 kHz to 199.9 kHz 22 MΩ 47 kΩ 47 pF 5 pF
200 kHz to 349.9 kHz 10 MΩ 47 kΩ 47 pF 5 pF
350 kHz to 600 kHz 10 MΩ 47 kΩ 47 pF 5 pF

Table 9. Optimum value for R2

Frequency R2 Optimum for
3 kHz 2.0 kΩ minimum required ICC
8.0 kΩ minimum influence due to change in VCC
6 kHz 1.0 kΩ minimum required ICC
4.7 kΩ minimum influence by VCC
10 kHz 0.5 kΩ minimum required ICC
2.0 kΩ minimum influence by VCC
14 kHz 0.5 kΩ minimum required ICC
1.0 kΩ minimum influence by VCC
>14 kHz - replace R2 by C3 with a typical value of 35 pF

001aal930
80
input
capacitance (1)
(pF)
60
(2)

(3)
40
(4)
(5)

20
U04 U04

RS R C
0
0 2 4 6 8
001aah115 VI (V)

(1) VCC = 2.0 V

(2) VCC = 3.0 V
(3) VCC = 4.0 V
The average ICC (mA) is approximately (4) VCC = 5.0 V
3.5 + 0.05 × f (MHz) × C (pF) at VCC = 5.0 V. (5) VCC = 6.0 V
Tamb = 25 °C.

Fig. 15. Astable multivibrator Fig. 16. Input capacitance as function of input voltage

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Hex unbuffered inverter

13. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

y HE v M A

14 8

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT108-1 076E06 MS-012
03-02-19

Fig. 17. Package outline SOT108-1 (SO14)

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Hex unbuffered inverter

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

Q
A2 (A 3 )
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.38 0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT402-1 MO-153
03-02-18

Fig. 18. Package outline SOT402-1 (TSSOP14)

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Hex unbuffered inverter

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1

D B A

A
A1
E c

terminal 1 detail X
index area

terminal 1 C
e1
index area v C A B
e b y1 C y
w C
2 6
L

1 7
Eh e
14 8
k

13 9
Dh
X
k

0 2 4 mm
scale
Dimensions (mm are the original dimensions)

Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1

max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5

mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1
min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
15-04-10
SOT762-1 MO-241 15-05-05

Fig. 19. Package outline SOT762-1 (DHVQFN14)

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Nexperia 74HCU04
Hex unbuffered inverter

14. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

15. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HCU04 v.9 20210531 Product data sheet - 74HCU04 v.8
Modifications: • Type number 74HCU04DB (SOT337-1/SSOP14) removed.
• Section 10: tr and tf parameters added to table description. (errata)
74HCU04 v.8 20200716 Product data sheet - 74HCU04 v.7
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 2 updated.
• Section 7: Derating values for Ptot total power dissipation have been updated.
74HCU04 v.7 20151208 Product data sheet - 74HCU04 v.6
Modifications: • Type number 74HCU04N (SOT27-1) removed.
• Conditions VIL and VIH corrected (errata).
74HCU04 v.6 20121227 Product data sheet - 74HCU04 v.5
Modifications: • New general description.
74HCU04 v.5 20120806 Product data sheet - 74HCU04 v.4
Modifications: • Measurement points added to figure 6 (errata).
74HCU04 v.4 20111212 Product data sheet - 74HCU04 v.3
Modifications: • Legal pages updated.
74HCU04 v.3 20100916 Product data sheet - 74HCU04_CNV v.2
74HCU04_CNV v.2 19970826 Product specification - -

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Hex unbuffered inverter
injury, death or severe property or environmental damage. Nexperia and its

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document, and as such is not complete, exhaustive or legally binding.
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Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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of an Nexperia product can reasonably be expected to result in personal

74HCU04 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 9 — 31 May 2021 13 / 14

Nexperia 74HCU04
Hex unbuffered inverter

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 3
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveform and test circuit.......................................... 5
11. Typical transfer characteristics................................. 6
12. Application information............................................. 7
13. Package outline.......................................................... 9
14. Abbreviations............................................................ 12
15. Revision history........................................................12
16. Legal information......................................................13

© Nexperia B.V. 2021. All rights reserved

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Date of release: 31 May 2021

74HCU04 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 9 — 31 May 2021 14 / 14