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Lecture17 SystemC Part3

The document discusses Transaction Level Modeling (TLM) 2.0 and the IEEE 1666-2011 standard. It describes TLM 2.0 coding styles like loosely-timed and approximately-timed, and the core interfaces, sockets, and generic payload that enable interoperability. The presentation also outlines the classes in TLM 2.0 like initiators, targets, blocking/non-blocking transports, and analysis ports.

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0% found this document useful (0 votes)
20 views

Lecture17 SystemC Part3

The document discusses Transaction Level Modeling (TLM) 2.0 and the IEEE 1666-2011 standard. It describes TLM 2.0 coding styles like loosely-timed and approximately-timed, and the core interfaces, sockets, and generic payload that enable interoperability. The presentation also outlines the classes in TLM 2.0 like initiators, targets, blocking/non-blocking transports, and analysis ports.

Uploaded by

kavitha tala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

Selected Slides for EECS 222,

Track 3: ESL and SystemC Part 3 (RD, 03/11/19)

The Definitive Guide to SystemC:


TLM-2.0
and the IEEE 1666-2011 Standard

David C Black, Doulos

Track 3: The Definitive Guide to SystemC

TLM-2.0 and IEEE 1666-2011

• What is IEEE-1666-2011
• Transaction Level Modeling
• The architecture of TLM-2.0
• Initiator, interconnect, target & Sockets
• The generic payload
• Loosely-timed coding style
• Extensions & Interoperability
Doulos Ltd

• Process Control
byLtd

• sc_vector
2013 Doulos
Copyright © 2014-2015

11
Transaction Level Modeling

Functional
RTL
Model

Pin Accurate Function Call

write(address,data)

Functional
Doulos Ltd

RTL
Model
byLtd
2013 Doulos
Copyright © 2014-2015

Simulate every event! 100-10,000 X faster simulation!

12

Track 3: The Definitive Guide to SystemC

TLM-2.0 and IEEE 1666-2011

• What is IEEE-1666-2011
• Transaction Level Modeling
• The architecture of TLM-2.0
• Initiator, interconnect, target & Sockets
• The generic payload
• Loosely-timed coding style
• Extensions & Interoperability
Doulos Ltd

• Process Control
byLtd

• sc_vector
2013 Doulos
Copyright © 2014-2015

16
Use Cases, Coding Styles
and Mechanisms
Use cases
Software Software Architectural Hardware
development performance analysis verification

TLM-2 Coding styles (just guidelines)

Loosely-timed

Approximately-timed
Doulos Ltd

Mechanisms (definitive API for TLM-2.0 enabling interoperability)


byLtd
2013 Doulos

Blocking Generic Non-blocking


Copyright © 2014-2015

DMI Quantum Sockets Phases


transport payload transport

17

Coding Styles

• Loosely-timed = as fast as possible

• Register-accurate
• Only sufficient timing detail to boot O/S and run multi-core systems
• b_transport – each transaction completes in one function call
• Temporal decoupling
• Direct memory interface (DMI)

• Approximately-timed = just accurate enough for performance modeling

• aka cycle-approximate or cycle-count-accurate


• Sufficient for architectural exploration
Doulos Ltd

• nb_transport – each transaction has 4 timing points (extensible)


byLtd
2013 Doulos
Copyright © 2014-2015

• Guidelines only – not definitive

18
The TLM 2.0 Classes

Utilities:
Interoperability layer for bus modeling Convenience sockets
Payload event queues
Generic payload Phases Quantum keeper
Instance-specific extn

Initiator and target sockets

TLM-1 standard TLM-2 core interfaces:


Analysis ports
Blocking transport interface
Non-blocking transport interface
Doulos Ltd

Direct memory interface


Debug transport interface Analysis interface
byLtd
2013 Doulos
Copyright © 2014-2015

IEEE 1666™ SystemC

19

Interoperability Layer

1. Core interfaces and


sockets

Initiator Target

2. Generic payload 3. Base protocol

Command BEGIN REQ


BEGIN_REQ
Address Either write bytes
Data END REQ
END_REQ
Doulos Ltd

Byte enables
Response status
byLtd

BEGIN RESP
BEGIN_RESP
or read bytes
2013 Doulos
Copyright © 2014-2015

Extensions
END RESP
END_RESP

• Maximal interoperability for memory-mapped bus models


20
Initiators, Targets and Interconnect

Initiator Target Initiator Target


socket socket socket socket

Forward Forward
path Interconnect path
Initiator component Target
0, 1 or many
Backward Backward
path path
Doulos Ltd

Transaction
object
byLtd
2013 Doulos
Copyright © 2014-2015

• Single transaction object for request and response


• References to the object are passed along the forward and backward paths
22

TLM-2 Connectivity

Initiator Target

Initiator Interconnect Interconnect Target

Target/ Target/
Doulos Ltd

Initiator Target
Initiator Initiator
byLtd
2013 Doulos
Copyright © 2014-2015

• Roles are dynamic; a component can choose whether to act as interconnect or target
• Transaction memory management needed
23
Convergent Paths

Initiator Target

Interconnect

Initiator Target
2013 Doulos
Copyright © 2014-2015 Doulos Ltd
byLtd

• Paths not predefined; routing may depend on transaction attributes (e.g. address)
• Whether arbitration is needed depends on the coding style
24

Track 3: The Definitive Guide to SystemC

TLM-2.0 and IEEE 1666-2011

• What is IEEE-1666-2011
• Transaction Level Modeling
• The architecture of TLM-2.0
• Initiator, interconnect, target & Sockets
• The generic payload
• Loosely-timed coding style
• Extensions & Interoperability
Doulos Ltd

• Process Control
byLtd

• sc_vector
2013 Doulos
Copyright © 2014-2015

25
Initiator and Target Sockets

Interface methods
Initiator Target
socket class tlm_fw_transport_if<> socket
b_transport ()
nb_transport_fw()
Initiator Target
get_direct_mem_ptr()
transport_dbg()

class tlm_bw_transport_if<>
Doulos Ltd

nb_transport_bw()
byLtd

invalidate_direct_mem_ptr()
2013 Doulos
Copyright © 2014-2015

• Sockets provide fw and bw paths, and group interfaces


26

Initiator Socket
#include "tlm.h"
struct Initiator: sc_module, tlm::tlm_bw_transport_if<> Combined interface required by socket
{
tlm::tlm_initiator_socket<> init_socket; Protocol type defaults to base protocol

SC_CTOR(Initiator) : init_socket("init_socket") {
SC_THREAD(thread);
init_socket.bind( *this ); Initiator socket bound to initiator itself
}

void thread() { ...


init_socket->b_transport( trans, delay );
init_socket->nb_transport_fw( trans, phase, delay );
init_socket->get_direct_mem_ptr( trans, dmi_data ); Calls on forward path
init_socket->transport_dbg( trans );
Doulos Ltd

}
yLtd

virtual tlm::tlm_sync_enum nb_transport_bw( ... ) { ... }


by
2013 Doulos
Copyright © 2014-2015

virtual void invalidate_direct_mem_ptr( ... ) { ... } Methods for backward path


};

tlm_initiator_socket must be bound to object that implements entire bw interface


27
Target Socket

struct Target: sc_module, tlm::tlm_fw_transport_if<> Combined interface required by socket

{
tlm::tlm_target_socket<> targ_socket; Protocol type default to base protocol

SC_CTOR(Target) : targ_socket("targ_socket") {
targ_socket.bind( *this ); Target socket bound to target itself

}
virual void b_transport( ... ) { ... }
virtual tlm::tlm_sync_enum nb_transport_fw( ... ) { ... }
Methods for forward path
Doulos Ltd

virtual bool get_direct_mem_ptr( ... ) { ... }


yLtd

virtual unsigned int transport_dbg( ... ) { ... }


by
2013 Doulos
Copyright © 2014-2015

};

tlm_target_socket must be bound to object that implements entire fw interface


28

Socket Binding

SC_MODULE(Top) {

Initiator *init;

Target *targ;

SC_CTOR(Top) {

init = new Initiator("init");

targ = new Target("targ");


Doulos Ltd

init->init_socket.bind( targ->targ_socket ); Bind initiator socket to target socket


byLtd
2013 Doulos

}
Copyright © 2014-2015

...

29
Track 3: The Definitive Guide to SystemC

TLM-2.0 and IEEE 1666-2011

• What is IEEE-1666-2011
• Transaction Level Modeling
• The architecture of TLM-2.0
• Initiator, interconnect, target & Sockets
• The generic payload
• Loosely-timed coding style
• Extensions & Interoperability
Doulos Ltd

• Process Control
byLtd

• sc_vector
2013 Doulos
Copyright © 2014-2015

30

The Generic Payload

• Has typical attributes of a memory-mapped bus

Attribute Type Modifiable?


Command tlm_command No
Address uint64 Interconnect only
Data pointer unsigned char* No (array – yes)
Data length unsigned int No
Byte enable pointer unsigned char* No
Byte enable length unsigned int No
Doulos Ltd

Streaming width unsigned int No


DMI hint bool Yes
byLtd
2013 Doulos
Copyright © 2014-2015

Response status tlm_response_status Target only


Extensions (tlm_extension_base*)[ ] Yes

31
Response Status

enum tlm_response_status Meaning


TLM_OK_RESPONSE Successful

TLM_INCOMPLETE_RESPONSE Transaction not delivered to target (default)

TLM_ADDRESS_ERROR_RESPONSE Unable to act on address

TLM_COMMAND_ERROR_RESPONSE Unable to execute command

TLM_BURST_ERROR_RESPONSE Unable to act on data length/ streaming width

TLM_BYTE_ENABLE_ERROR_RESPONSE Unable to act on byte enable

TLM_GENERIC_ERROR_RESPONSE Any other error


Doulos Ltd

• Set to TLM_INCOMPLETE_RESPONSE by the initiator


byLtd


2013 Doulos

May be modified by the target


Copyright © 2014-2015

• Checked by the initiator when transaction is complete

32

Generic Payload - Initiator

void thread_process() { // The initiator


tlm::tlm_generic_payload trans; Would usually pool transactions
sc_time delay = SC_ZERO_TIME;

trans.set_command( tlm::TLM_WRITE_COMMAND );
trans.set_data_length( 4 ); 8 attributes you must set
trans.set_streaming_width( 4 );
trans.set_byte_enable_ptr( 0 );

for ( int i = 0; i < RUN_LENGTH; i += 4 ) {


int word = i;
trans.set_address( i );
trans.set_data_ptr( (unsigned char*)( &word ) );
trans.set_dmi_allowed( false );
trans.set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
Doulos Ltd

init_socket->b_transport( trans, delay );


byLtd
2013 Doulos
Copyright © 2014-2015

if ( trans.is_response_error() )
SC_REPORT_ERROR("TLM-2", trans.get_response_string().c_str());
...
}
33
Generic Payload - Target
virtual void b_transport( // The target
tlm::tlm_generic_payload& trans, sc_core::sc_time& t )
{
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr(); 6 attributes you must check
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
Target supports 1-word transfers
if ( byt != 0 || len > 4 || wid < len || adr+len > memsize ) {
trans.set_response_status( tlm::TLM_GENERIC_ERROR_RESPONSE );
return;
}
Doulos Ltd

if ( cmd == tlm::TLM_WRITE_COMMAND ) Execute command


memcpy( &m_storage[adr], ptr, len );
byLtd

else if ( cmd == tlm::TLM_READ_COMMAND )


2013 Doulos
Copyright © 2014-2015

memcpy( ptr, &m_storage[adr], len );

trans.set_response_status( tlm::TLM_OK_RESPONSE ); Successful completion


}
34

Track 3: The Definitive Guide to SystemC

TLM-2.0 and IEEE 1666-2011

• What is IEEE-1666-2011
• Transaction Level Modeling
• The architecture of TLM-2.0
• Initiator, interconnect, target & Sockets
• The generic payload
• Loosely-timed coding style
• Extensions & Interoperability
Doulos Ltd

• Process Control
byLtd

• sc_vector
2013 Doulos
Copyright © 2014-2015

35
Causality with b_transport
Initiator Interconnect Interconnect Target

Initiator sets
attributes b_transport
Modifies
address b_transport

Modifies
address b_transport

Target
modifies
attributes
return
Doulos Ltd

return
byLtd

return
2013 Doulos
Copyright © 2014-2015

Initiator
checks
response

41

Timing Annotation and b_transport

virtual void b_transport ( TRANS& trans , sc_core::sc_time& delay )


{
Behave as if method were called at sc_time_stamp() + delay
...
delay = delay + latency;
}

socket->b_transport( transaction, delay );

Behave as if method returned at sc_time_stamp() + delay


Doulos Ltd

• Recipient may
byLtd


2013 Doulos

Execute transactions immediately, out-of-order – Loosely-timed


Copyright © 2014-2015

• Schedule transactions to execute at proper time – Approx-timed


• Pass on the transaction with the timing annotation

42
Temporal Decoupling

Initiator Target
Simulation time = 100ns

Local time offset


Call b_transport(t, 0ns)

+5ns
b_transport(t, 5ns) Return

Call b_transport(t, 20ns)


+20ns
+25ns
b_transport(t, 25ns) Return
Doulos Ltd

Call b_transport(t, 30ns)


+30ns
byLtd
2013 Doulos
Copyright © 2014-2015

Simulation time = 140ns wait(40ns)

+5ns
b_transport(t, 5ns) Return

43

Direct Memory Interface

Granted/denied Access requested Access granted

status = get_direct_mem_ptr( transaction, dmi_data );

Command DMI pointer


Address Start/end address
Read/write granted
Read/write latency

Forward path Forward path


Interconnect
Initiator Target
component
Doulos Ltd

Initiator Target
byLtd

Initiator Target
2013 Doulos
Copyright © 2014-2015

DMI pointer bypasses interconnect


46

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